usr/src/uts/common/io/e1000api/e1000_80003es2lan.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2011, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
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  10       this list of conditions and the following disclaimer.
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  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
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  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
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  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_80003ES2LAN_H_
  36 #define _E1000_80003ES2LAN_H_
  37
  38 #ifdef __cplusplus
  39 extern "C" {
  40 #endif
  41
  42 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL      0x00
  43 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL       0x02
  44 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL        0x10
  45 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
  46
  47 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS   0x0008
  48 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS   0x0800
  49 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING  0x0010
  50
  51 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  52 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT  0x0000
  53 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE         0x2000
  54
  55 #define E1000_KMRNCTRLSTA_OPMODE_MASK           0x000C
  56 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO    0x0004
  57
  58 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  59 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN       0x00010000
  60
  61 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN      0x8
  62 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN    0x9
  63
  64 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  65 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE  0x0002 /* 1=Reversal Disabled */
  66 #define GG82563_PSCR_CROSSOVER_MODE_MASK        0x0060
  67 #define GG82563_PSCR_CROSSOVER_MODE_MDI         0x0000 /* 00=Manual MDI */
  68 #define GG82563_PSCR_CROSSOVER_MODE_MDIX        0x0020 /* 01=Manual MDIX */
  69 #define GG82563_PSCR_CROSSOVER_MODE_AUTO        0x0060 /* 11=Auto crossover */
  70
  71 /* PHY Specific Control Register 2 (Page 0, Register 26) */
  72 #define GG82563_PSCR2_REVERSE_AUTO_NEG          0x2000 /* 1=Reverse Auto-Nego */
  73
  74 /* MAC Specific Control Register (Page 2, Register 21) */
  75 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  76 #define GG82563_MSCR_TX_CLK_MASK                0x0007
  77 #define GG82563_MSCR_TX_CLK_10MBPS_2_5          0x0004
  78 #define GG82563_MSCR_TX_CLK_100MBPS_25          0x0005
  79 #define GG82563_MSCR_TX_CLK_1000MBPS_2_5        0x0006
  80 #define GG82563_MSCR_TX_CLK_1000MBPS_25         0x0007
  81
  82 #define GG82563_MSCR_ASSERT_CRS_ON_TX           0x0010 /* 1=Assert */
  83
  84 /* DSP Distance Register (Page 5, Register 26) */
  85 /*
  86  * 0 = <50M
  87  * 1 = 50-80M
  88  * 2 = 80-100M
  89  * 3 = 110-140M
  90  * 4 = >140M
  91  */
  92 #define GG82563_DSPD_CABLE_LENGTH               0x0007
  93
  94 /* Kumeran Mode Control Register (Page 193, Register 16) */
  95 #define GG82563_KMCR_PASS_FALSE_CARRIER         0x0800
  96
  97 /* Max number of times Kumeran read/write should be validated */
  98 #define GG82563_MAX_KMRN_RETRY                  0x5
  99
 100 /* Power Management Control Register (Page 193, Register 20) */
 101 /* 1=Enable SERDES Electrical Idle */
 102 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE     0x0001
 103
 104 /* In-Band Control Register (Page 194, Register 18) */
 105 #define GG82563_ICR_DIS_PADDING                 0x0010 /* Disable Padding */
 106
 107 #ifdef __cplusplus
 108 }
 109 #endif
 110
 111 #endif  /* _E1000_80003ES2LAN_H_ */