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15325 bhyve upstream sync 2023 January
[illumos-gate.git] / usr / src / contrib / bhyve / dev / nvme / nvme.h
blobbf088f09a4328b0c4cc38dc981b1edab3c3bfe06
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (C) 2012-2013 Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 *
30 * Copyright 2019 Joyent, Inc.
31 */
32
33 /*
34 * illumos port notes:
35 *
36 * The upstream version of this file uses conditionals of the form
37 * #if _BYTE_ORDER != _LITTLE_ENDIAN
38 * Rather than keep this file in compat with only that little bit changed,
39 * this is locally patched below.
40 *
41 * There is also a static assertion which has been commented out due to a
42 * problem with smatch.
43 */
44
45 #ifndef __NVME_H__
46 #define __NVME_H__
47
48 #ifdef _KERNEL
49 #include <sys/types.h>
50 #endif
51
52 #include <sys/param.h>
53 #include <sys/endian.h>
54
55 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command)
56 #define NVME_RESET_CONTROLLER _IO('n', 1)
57 #define NVME_GET_NSID _IOR('n', 2, struct nvme_get_nsid)
58 #define NVME_GET_MAX_XFER_SIZE _IOR('n', 3, uint64_t)
59
60 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test)
61 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test)
62
63 /*
64 * Macros to deal with NVME revisions, as defined VS register
65 */
66 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8))
67 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff)
68 #define NVME_MINOR(r) (((r) >> 8) & 0xff)
69
70 /*
71 * Use to mark a command to apply to all namespaces, or to retrieve global
72 * log pages.
73 */
74 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF)
75
76 /* Host memory buffer sizes are always in 4096 byte chunks */
77 #define NVME_HMB_UNITS 4096
78
79 /* Many items are expressed in terms of power of two times MPS */
80 #define NVME_MPS_SHIFT 12
81
82 /* Register field definitions */
83 #define NVME_CAP_LO_REG_MQES_SHIFT (0)
84 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF)
85 #define NVME_CAP_LO_REG_CQR_SHIFT (16)
86 #define NVME_CAP_LO_REG_CQR_MASK (0x1)
87 #define NVME_CAP_LO_REG_AMS_SHIFT (17)
88 #define NVME_CAP_LO_REG_AMS_MASK (0x3)
89 #define NVME_CAP_LO_REG_TO_SHIFT (24)
90 #define NVME_CAP_LO_REG_TO_MASK (0xFF)
91 #define NVME_CAP_LO_MQES(x) \
92 (((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK)
93 #define NVME_CAP_LO_CQR(x) \
94 (((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK)
95 #define NVME_CAP_LO_AMS(x) \
96 (((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK)
97 #define NVME_CAP_LO_TO(x) \
98 (((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK)
99
100 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0)
101 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF)
102 #define NVME_CAP_HI_REG_NSSRS_SHIFT (4)
103 #define NVME_CAP_HI_REG_NSSRS_MASK (0x1)
104 #define NVME_CAP_HI_REG_CSS_SHIFT (5)
105 #define NVME_CAP_HI_REG_CSS_MASK (0xff)
106 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5)
107 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1)
108 #define NVME_CAP_HI_REG_BPS_SHIFT (13)
109 #define NVME_CAP_HI_REG_BPS_MASK (0x1)
110 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16)
111 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF)
112 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20)
113 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF)
114 #define NVME_CAP_HI_REG_PMRS_SHIFT (24)
115 #define NVME_CAP_HI_REG_PMRS_MASK (0x1)
116 #define NVME_CAP_HI_REG_CMBS_SHIFT (25)
117 #define NVME_CAP_HI_REG_CMBS_MASK (0x1)
118 #define NVME_CAP_HI_DSTRD(x) \
119 (((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK)
120 #define NVME_CAP_HI_NSSRS(x) \
121 (((x) >> NVME_CAP_HI_REG_NSSRS_SHIFT) & NVME_CAP_HI_REG_NSSRS_MASK)
122 #define NVME_CAP_HI_CSS(x) \
123 (((x) >> NVME_CAP_HI_REG_CSS_SHIFT) & NVME_CAP_HI_REG_CSS_MASK)
124 #define NVME_CAP_HI_CSS_NVM(x) \
125 (((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK)
126 #define NVME_CAP_HI_BPS(x) \
127 (((x) >> NVME_CAP_HI_REG_BPS_SHIFT) & NVME_CAP_HI_REG_BPS_MASK)
128 #define NVME_CAP_HI_MPSMIN(x) \
129 (((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK)
130 #define NVME_CAP_HI_MPSMAX(x) \
131 (((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK)
132 #define NVME_CAP_HI_PMRS(x) \
133 (((x) >> NVME_CAP_HI_REG_PMRS_SHIFT) & NVME_CAP_HI_REG_PMRS_MASK)
134 #define NVME_CAP_HI_CMBS(x) \
135 (((x) >> NVME_CAP_HI_REG_CMBS_SHIFT) & NVME_CAP_HI_REG_CMBS_MASK)
136
137 #define NVME_CC_REG_EN_SHIFT (0)
138 #define NVME_CC_REG_EN_MASK (0x1)
139 #define NVME_CC_REG_CSS_SHIFT (4)
140 #define NVME_CC_REG_CSS_MASK (0x7)
141 #define NVME_CC_REG_MPS_SHIFT (7)
142 #define NVME_CC_REG_MPS_MASK (0xF)
143 #define NVME_CC_REG_AMS_SHIFT (11)
144 #define NVME_CC_REG_AMS_MASK (0x7)
145 #define NVME_CC_REG_SHN_SHIFT (14)
146 #define NVME_CC_REG_SHN_MASK (0x3)
147 #define NVME_CC_REG_IOSQES_SHIFT (16)
148 #define NVME_CC_REG_IOSQES_MASK (0xF)
149 #define NVME_CC_REG_IOCQES_SHIFT (20)
150 #define NVME_CC_REG_IOCQES_MASK (0xF)
151
152 #define NVME_CSTS_REG_RDY_SHIFT (0)
153 #define NVME_CSTS_REG_RDY_MASK (0x1)
154 #define NVME_CSTS_REG_CFS_SHIFT (1)
155 #define NVME_CSTS_REG_CFS_MASK (0x1)
156 #define NVME_CSTS_REG_SHST_SHIFT (2)
157 #define NVME_CSTS_REG_SHST_MASK (0x3)
158 #define NVME_CSTS_REG_NVSRO_SHIFT (4)
159 #define NVME_CSTS_REG_NVSRO_MASK (0x1)
160 #define NVME_CSTS_REG_PP_SHIFT (5)
161 #define NVME_CSTS_REG_PP_MASK (0x1)
162
163 #define NVME_CSTS_GET_SHST(csts) (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK)
164
165 #define NVME_AQA_REG_ASQS_SHIFT (0)
166 #define NVME_AQA_REG_ASQS_MASK (0xFFF)
167 #define NVME_AQA_REG_ACQS_SHIFT (16)
168 #define NVME_AQA_REG_ACQS_MASK (0xFFF)
169
170 #define NVME_PMRCAP_REG_RDS_SHIFT (3)
171 #define NVME_PMRCAP_REG_RDS_MASK (0x1)
172 #define NVME_PMRCAP_REG_WDS_SHIFT (4)
173 #define NVME_PMRCAP_REG_WDS_MASK (0x1)
174 #define NVME_PMRCAP_REG_BIR_SHIFT (5)
175 #define NVME_PMRCAP_REG_BIR_MASK (0x7)
176 #define NVME_PMRCAP_REG_PMRTU_SHIFT (8)
177 #define NVME_PMRCAP_REG_PMRTU_MASK (0x3)
178 #define NVME_PMRCAP_REG_PMRWBM_SHIFT (10)
179 #define NVME_PMRCAP_REG_PMRWBM_MASK (0xf)
180 #define NVME_PMRCAP_REG_PMRTO_SHIFT (16)
181 #define NVME_PMRCAP_REG_PMRTO_MASK (0xff)
182 #define NVME_PMRCAP_REG_CMSS_SHIFT (24)
183 #define NVME_PMRCAP_REG_CMSS_MASK (0x1)
184
185 #define NVME_PMRCAP_RDS(x) \
186 (((x) >> NVME_PMRCAP_REG_RDS_SHIFT) & NVME_PMRCAP_REG_RDS_MASK)
187 #define NVME_PMRCAP_WDS(x) \
188 (((x) >> NVME_PMRCAP_REG_WDS_SHIFT) & NVME_PMRCAP_REG_WDS_MASK)
189 #define NVME_PMRCAP_BIR(x) \
190 (((x) >> NVME_PMRCAP_REG_BIR_SHIFT) & NVME_PMRCAP_REG_BIR_MASK)
191 #define NVME_PMRCAP_PMRTU(x) \
192 (((x) >> NVME_PMRCAP_REG_PMRTU_SHIFT) & NVME_PMRCAP_REG_PMRTU_MASK)
193 #define NVME_PMRCAP_PMRWBM(x) \
194 (((x) >> NVME_PMRCAP_REG_PMRWBM_SHIFT) & NVME_PMRCAP_REG_PMRWBM_MASK)
195 #define NVME_PMRCAP_PMRTO(x) \
196 (((x) >> NVME_PMRCAP_REG_PMRTO_SHIFT) & NVME_PMRCAP_REG_PMRTO_MASK)
197 #define NVME_PMRCAP_CMSS(x) \
198 (((x) >> NVME_PMRCAP_REG_CMSS_SHIFT) & NVME_PMRCAP_REG_CMSS_MASK)
199
200 /* Command field definitions */
201
202 #define NVME_CMD_FUSE_SHIFT (8)
203 #define NVME_CMD_FUSE_MASK (0x3)
204
205 #define NVME_STATUS_P_SHIFT (0)
206 #define NVME_STATUS_P_MASK (0x1)
207 #define NVME_STATUS_SC_SHIFT (1)
208 #define NVME_STATUS_SC_MASK (0xFF)
209 #define NVME_STATUS_SCT_SHIFT (9)
210 #define NVME_STATUS_SCT_MASK (0x7)
211 #define NVME_STATUS_CRD_SHIFT (12)
212 #define NVME_STATUS_CRD_MASK (0x3)
213 #define NVME_STATUS_M_SHIFT (14)
214 #define NVME_STATUS_M_MASK (0x1)
215 #define NVME_STATUS_DNR_SHIFT (15)
216 #define NVME_STATUS_DNR_MASK (0x1)
217
218 #define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK)
219 #define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK)
220 #define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK)
221 #define NVME_STATUS_GET_CRD(st) (((st) >> NVME_STATUS_CRD_SHIFT) & NVME_STATUS_CRD_MASK)
222 #define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK)
223 #define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK)
224
225 #define NVME_PWR_ST_MPS_SHIFT (0)
226 #define NVME_PWR_ST_MPS_MASK (0x1)
227 #define NVME_PWR_ST_NOPS_SHIFT (1)
228 #define NVME_PWR_ST_NOPS_MASK (0x1)
229 #define NVME_PWR_ST_RRT_SHIFT (0)
230 #define NVME_PWR_ST_RRT_MASK (0x1F)
231 #define NVME_PWR_ST_RRL_SHIFT (0)
232 #define NVME_PWR_ST_RRL_MASK (0x1F)
233 #define NVME_PWR_ST_RWT_SHIFT (0)
234 #define NVME_PWR_ST_RWT_MASK (0x1F)
235 #define NVME_PWR_ST_RWL_SHIFT (0)
236 #define NVME_PWR_ST_RWL_MASK (0x1F)
237 #define NVME_PWR_ST_IPS_SHIFT (6)
238 #define NVME_PWR_ST_IPS_MASK (0x3)
239 #define NVME_PWR_ST_APW_SHIFT (0)
240 #define NVME_PWR_ST_APW_MASK (0x7)
241 #define NVME_PWR_ST_APS_SHIFT (6)
242 #define NVME_PWR_ST_APS_MASK (0x3)
243
244 /** Controller Multi-path I/O and Namespace Sharing Capabilities */
245 /* More then one port */
246 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0)
247 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1)
248 /* More then one controller */
249 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1)
250 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1)
251 /* SR-IOV Virtual Function */
252 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2)
253 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1)
254 /* Asymmetric Namespace Access Reporting */
255 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3)
256 #define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1)
257
258 /** OAES - Optional Asynchronous Events Supported */
259 /* supports Namespace Attribute Notices event */
260 #define NVME_CTRLR_DATA_OAES_NS_ATTR_SHIFT (8)
261 #define NVME_CTRLR_DATA_OAES_NS_ATTR_MASK (0x1)
262 /* supports Firmware Activation Notices event */
263 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_SHIFT (9)
264 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_MASK (0x1)
265 /* supports Asymmetric Namespace Access Change Notices event */
266 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_SHIFT (11)
267 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_MASK (0x1)
268 /* supports Predictable Latency Event Aggregate Log Change Notices event */
269 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_SHIFT (12)
270 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_MASK (0x1)
271 /* supports LBA Status Information Notices event */
272 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_SHIFT (13)
273 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_MASK (0x1)
274 /* supports Endurance Group Event Aggregate Log Page Changes Notices event */
275 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_SHIFT (14)
276 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_MASK (0x1)
277 /* supports Normal NVM Subsystem Shutdown event */
278 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_SHIFT (15)
279 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_MASK (0x1)
280 /* supports Zone Descriptor Changed Notices event */
281 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_SHIFT (27)
282 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_MASK (0x1)
283 /* supports Discovery Log Page Change Notification event */
284 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_SHIFT (31)
285 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_MASK (0x1)
286
287 /** OACS - optional admin command support */
288 /* supports security send/receive commands */
289 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0)
290 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1)
291 /* supports format nvm command */
292 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1)
293 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1)
294 /* supports firmware activate/download commands */
295 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2)
296 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1)
297 /* supports namespace management commands */
298 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3)
299 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1)
300 /* supports Device Self-test command */
301 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4)
302 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1)
303 /* supports Directives */
304 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5)
305 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1)
306 /* supports NVMe-MI Send/Receive */
307 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6)
308 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1)
309 /* supports Virtualization Management */
310 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7)
311 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1)
312 /* supports Doorbell Buffer Config */
313 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8)
314 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1)
315 /* supports Get LBA Status */
316 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9)
317 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1)
318
319 /** firmware updates */
320 /* first slot is read-only */
321 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0)
322 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1)
323 /* number of firmware slots */
324 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1)
325 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7)
326 /* firmware activation without reset */
327 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4)
328 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1)
329
330 /** log page attributes */
331 /* per namespace smart/health log page */
332 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0)
333 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1)
334
335 /** AVSCC - admin vendor specific command configuration */
336 /* admin vendor specific commands use spec format */
337 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0)
338 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1)
339
340 /** Autonomous Power State Transition Attributes */
341 /* Autonomous Power State Transitions supported */
342 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0)
343 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1)
344
345 /** Sanitize Capabilities */
346 /* Crypto Erase Support */
347 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0)
348 #define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1)
349 /* Block Erase Support */
350 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1)
351 #define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1)
352 /* Overwrite Support */
353 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2)
354 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1)
355 /* No-Deallocate Inhibited */
356 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29)
357 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1)
358 /* No-Deallocate Modifies Media After Sanitize */
359 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30)
360 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3)
361 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0)
362 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1)
363 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2)
364
365 /** submission queue entry size */
366 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0)
367 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF)
368 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4)
369 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF)
370
371 /** completion queue entry size */
372 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0)
373 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF)
374 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4)
375 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF)
376
377 /** optional nvm command support */
378 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0)
379 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1)
380 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1)
381 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1)
382 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2)
383 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1)
384 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3)
385 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1)
386 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4)
387 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1)
388 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5)
389 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1)
390 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6)
391 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1)
392 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7)
393 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1)
394
395 /** Fused Operation Support */
396 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0)
397 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1)
398
399 /** Format NVM Attributes */
400 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0)
401 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1)
402 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1)
403 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1)
404 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2)
405 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1)
406
407 /** volatile write cache */
408 /* volatile write cache present */
409 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0)
410 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1)
411 /* flush all namespaces supported */
412 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1)
413 #define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3)
414 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0)
415 #define NVME_CTRLR_DATA_VWC_ALL_NO (2)
416 #define NVME_CTRLR_DATA_VWC_ALL_YES (3)
417
418 /** namespace features */
419 /* thin provisioning */
420 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0)
421 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1)
422 /* NAWUN, NAWUPF, and NACWU fields are valid */
423 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1)
424 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1)
425 /* Deallocated or Unwritten Logical Block errors supported */
426 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2)
427 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1)
428 /* NGUID and EUI64 fields are not reusable */
429 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3)
430 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1)
431 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
432 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4)
433 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1)
434
435 /** formatted lba size */
436 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0)
437 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF)
438 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4)
439 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1)
440
441 /** metadata capabilities */
442 /* metadata can be transferred as part of data prp list */
443 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0)
444 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1)
445 /* metadata can be transferred with separate metadata pointer */
446 #define NVME_NS_DATA_MC_POINTER_SHIFT (1)
447 #define NVME_NS_DATA_MC_POINTER_MASK (0x1)
448
449 /** end-to-end data protection capabilities */
450 /* protection information type 1 */
451 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0)
452 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1)
453 /* protection information type 2 */
454 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1)
455 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1)
456 /* protection information type 3 */
457 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2)
458 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1)
459 /* first eight bytes of metadata */
460 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3)
461 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1)
462 /* last eight bytes of metadata */
463 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4)
464 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1)
465
466 /** end-to-end data protection type settings */
467 /* protection information type */
468 #define NVME_NS_DATA_DPS_PIT_SHIFT (0)
469 #define NVME_NS_DATA_DPS_PIT_MASK (0x7)
470 /* 1 == protection info transferred at start of metadata */
471 /* 0 == protection info transferred at end of metadata */
472 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3)
473 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1)
474
475 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
476 /* the namespace may be attached to two or more controllers */
477 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0)
478 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1)
479
480 /** Reservation Capabilities */
481 /* Persist Through Power Loss */
482 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0)
483 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1)
484 /* supports the Write Exclusive */
485 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1)
486 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1)
487 /* supports the Exclusive Access */
488 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2)
489 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1)
490 /* supports the Write Exclusive – Registrants Only */
491 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3)
492 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1)
493 /* supports the Exclusive Access - Registrants Only */
494 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4)
495 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1)
496 /* supports the Write Exclusive – All Registrants */
497 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5)
498 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1)
499 /* supports the Exclusive Access - All Registrants */
500 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6)
501 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1)
502 /* Ignore Existing Key is used as defined in revision 1.3 or later */
503 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7)
504 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1)
505
506 /** Format Progress Indicator */
507 /* percentage of the Format NVM command that remains to be completed */
508 #define NVME_NS_DATA_FPI_PERC_SHIFT (0)
509 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f)
510 /* namespace supports the Format Progress Indicator */
511 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7)
512 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1)
513
514 /** Deallocate Logical Block Features */
515 /* deallocated logical block read behavior */
516 #define NVME_NS_DATA_DLFEAT_READ_SHIFT (0)
517 #define NVME_NS_DATA_DLFEAT_READ_MASK (0x07)
518 #define NVME_NS_DATA_DLFEAT_READ_NR (0x00)
519 #define NVME_NS_DATA_DLFEAT_READ_00 (0x01)
520 #define NVME_NS_DATA_DLFEAT_READ_FF (0x02)
521 /* supports the Deallocate bit in the Write Zeroes */
522 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3)
523 #define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01)
524 /* Guard field for deallocated logical blocks is set to the CRC */
525 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4)
526 #define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01)
527
528 /** lba format support */
529 /* metadata size */
530 #define NVME_NS_DATA_LBAF_MS_SHIFT (0)
531 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF)
532 /* lba data size */
533 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16)
534 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF)
535 /* relative performance */
536 #define NVME_NS_DATA_LBAF_RP_SHIFT (24)
537 #define NVME_NS_DATA_LBAF_RP_MASK (0x3)
538
539 enum nvme_critical_warning_state {
540 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1,
541 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2,
542 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4,
543 NVME_CRIT_WARN_ST_READ_ONLY = 0x8,
544 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10,
545 };
546 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xE0)
547 #define NVME_ASYNC_EVENT_NS_ATTRIBUTE (0x100)
548 #define NVME_ASYNC_EVENT_FW_ACTIVATE (0x200)
549
550 /* slot for current FW */
551 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0)
552 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7)
553
554 /* Commands Supported and Effects */
555 #define NVME_CE_PAGE_CSUP_SHIFT (0)
556 #define NVME_CE_PAGE_CSUP_MASK (0x1)
557 #define NVME_CE_PAGE_LBCC_SHIFT (1)
558 #define NVME_CE_PAGE_LBCC_MASK (0x1)
559 #define NVME_CE_PAGE_NCC_SHIFT (2)
560 #define NVME_CE_PAGE_NCC_MASK (0x1)
561 #define NVME_CE_PAGE_NIC_SHIFT (3)
562 #define NVME_CE_PAGE_NIC_MASK (0x1)
563 #define NVME_CE_PAGE_CCC_SHIFT (4)
564 #define NVME_CE_PAGE_CCC_MASK (0x1)
565 #define NVME_CE_PAGE_CSE_SHIFT (16)
566 #define NVME_CE_PAGE_CSE_MASK (0x7)
567 #define NVME_CE_PAGE_UUID_SHIFT (19)
568 #define NVME_CE_PAGE_UUID_MASK (0x1)
569
570 /* Sanitize Status */
571 #define NVME_SS_PAGE_SSTAT_STATUS_SHIFT (0)
572 #define NVME_SS_PAGE_SSTAT_STATUS_MASK (0x7)
573 #define NVME_SS_PAGE_SSTAT_STATUS_NEVER (0)
574 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED (1)
575 #define NVME_SS_PAGE_SSTAT_STATUS_INPROG (2)
576 #define NVME_SS_PAGE_SSTAT_STATUS_FAILED (3)
577 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD (4)
578 #define NVME_SS_PAGE_SSTAT_PASSES_SHIFT (3)
579 #define NVME_SS_PAGE_SSTAT_PASSES_MASK (0x1f)
580 #define NVME_SS_PAGE_SSTAT_GDE_SHIFT (8)
581 #define NVME_SS_PAGE_SSTAT_GDE_MASK (0x1)
582
583 /* Features */
584 /* Get Features */
585 #define NVME_FEAT_GET_SEL_SHIFT (8)
586 #define NVME_FEAT_GET_SEL_MASK (0x7)
587 #define NVME_FEAT_GET_FID_SHIFT (0)
588 #define NVME_FEAT_GET_FID_MASK (0xff)
589
590 /* Set Features */
591 #define NVME_FEAT_SET_SV_SHIFT (31)
592 #define NVME_FEAT_SET_SV_MASK (0x1)
593 #define NVME_FEAT_SET_FID_SHIFT (0)
594 #define NVME_FEAT_SET_FID_MASK (0xff)
595
596 /* Helper macro to combine *_MASK and *_SHIFT defines */
597 #define NVMEB(name) (name##_MASK << name##_SHIFT)
598
599 /* Helper macro to extract value from x */
600 #define NVMEV(name, x) (((x) >> name##_SHIFT) & name##_MASK)
601
602 /* CC register SHN field values */
603 enum shn_value {
604 NVME_SHN_NORMAL = 0x1,
605 NVME_SHN_ABRUPT = 0x2,
606 };
607
608 /* CSTS register SHST field values */
609 enum shst_value {
610 NVME_SHST_NORMAL = 0x0,
611 NVME_SHST_OCCURRING = 0x1,
612 NVME_SHST_COMPLETE = 0x2,
613 };
614
615 struct nvme_registers {
616 uint32_t cap_lo; /* controller capabilities */
617 uint32_t cap_hi;
618 uint32_t vs; /* version */
619 uint32_t intms; /* interrupt mask set */
620 uint32_t intmc; /* interrupt mask clear */
621 uint32_t cc; /* controller configuration */
622 uint32_t reserved1;
623 uint32_t csts; /* controller status */
624 uint32_t nssr; /* NVM Subsystem Reset */
625 uint32_t aqa; /* admin queue attributes */
626 uint64_t asq; /* admin submission queue base addr */
627 uint64_t acq; /* admin completion queue base addr */
628 uint32_t cmbloc; /* Controller Memory Buffer Location */
629 uint32_t cmbsz; /* Controller Memory Buffer Size */
630 uint32_t bpinfo; /* Boot Partition Information */
631 uint32_t bprsel; /* Boot Partition Read Select */
632 uint64_t bpmbl; /* Boot Partition Memory Buffer Location */
633 uint64_t cmbmsc; /* Controller Memory Buffer Memory Space Control */
634 uint32_t cmbsts; /* Controller Memory Buffer Status */
635 uint8_t reserved3[3492]; /* 5Ch - DFFh */
636 uint32_t pmrcap; /* Persistent Memory Capabilities */
637 uint32_t pmrctl; /* Persistent Memory Region Control */
638 uint32_t pmrsts; /* Persistent Memory Region Status */
639 uint32_t pmrebs; /* Persistent Memory Region Elasticity Buffer Size */
640 uint32_t pmrswtp; /* Persistent Memory Region Sustained Write Throughput */
641 uint32_t pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */
642 uint32_t pmrmsc_hi;
643 uint8_t reserved4[484]; /* E1Ch - FFFh */
644 struct {
645 uint32_t sq_tdbl; /* submission queue tail doorbell */
646 uint32_t cq_hdbl; /* completion queue head doorbell */
647 } doorbell[1];
648 };
649
650 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers");
651
652 struct nvme_command {
653 /* dword 0 */
654 uint8_t opc; /* opcode */
655 uint8_t fuse; /* fused operation */
656 uint16_t cid; /* command identifier */
657
658 /* dword 1 */
659 uint32_t nsid; /* namespace identifier */
660
661 /* dword 2-3 */
662 uint32_t rsvd2;
663 uint32_t rsvd3;
664
665 /* dword 4-5 */
666 uint64_t mptr; /* metadata pointer */
667
668 /* dword 6-7 */
669 uint64_t prp1; /* prp entry 1 */
670
671 /* dword 8-9 */
672 uint64_t prp2; /* prp entry 2 */
673
674 /* dword 10-15 */
675 uint32_t cdw10; /* command-specific */
676 uint32_t cdw11; /* command-specific */
677 uint32_t cdw12; /* command-specific */
678 uint32_t cdw13; /* command-specific */
679 uint32_t cdw14; /* command-specific */
680 uint32_t cdw15; /* command-specific */
681 };
682
683 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command");
684
685 struct nvme_completion {
686 /* dword 0 */
687 uint32_t cdw0; /* command-specific */
688
689 /* dword 1 */
690 uint32_t rsvd1;
691
692 /* dword 2 */
693 uint16_t sqhd; /* submission queue head pointer */
694 uint16_t sqid; /* submission queue identifier */
695
696 /* dword 3 */
697 uint16_t cid; /* command identifier */
698 uint16_t status;
699 } __aligned(8); /* riscv: nvme_qpair_process_completions has better code gen */
700
701 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
702
703 struct nvme_dsm_range {
704 uint32_t attributes;
705 uint32_t length;
706 uint64_t starting_lba;
707 };
708
709 /* Largest DSM Trim that can be done */
710 #define NVME_MAX_DSM_TRIM 4096
711
712 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage");
713
714 /* status code types */
715 enum nvme_status_code_type {
716 NVME_SCT_GENERIC = 0x0,
717 NVME_SCT_COMMAND_SPECIFIC = 0x1,
718 NVME_SCT_MEDIA_ERROR = 0x2,
719 NVME_SCT_PATH_RELATED = 0x3,
720 /* 0x3-0x6 - reserved */
721 NVME_SCT_VENDOR_SPECIFIC = 0x7,
722 };
723
724 /* generic command status codes */
725 enum nvme_generic_command_status_code {
726 NVME_SC_SUCCESS = 0x00,
727 NVME_SC_INVALID_OPCODE = 0x01,
728 NVME_SC_INVALID_FIELD = 0x02,
729 NVME_SC_COMMAND_ID_CONFLICT = 0x03,
730 NVME_SC_DATA_TRANSFER_ERROR = 0x04,
731 NVME_SC_ABORTED_POWER_LOSS = 0x05,
732 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06,
733 NVME_SC_ABORTED_BY_REQUEST = 0x07,
734 NVME_SC_ABORTED_SQ_DELETION = 0x08,
735 NVME_SC_ABORTED_FAILED_FUSED = 0x09,
736 NVME_SC_ABORTED_MISSING_FUSED = 0x0a,
737 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b,
738 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c,
739 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d,
740 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e,
741 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f,
742 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10,
743 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11,
744 NVME_SC_INVALID_USE_OF_CMB = 0x12,
745 NVME_SC_PRP_OFFET_INVALID = 0x13,
746 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14,
747 NVME_SC_OPERATION_DENIED = 0x15,
748 NVME_SC_SGL_OFFSET_INVALID = 0x16,
749 /* 0x17 - reserved */
750 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18,
751 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19,
752 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a,
753 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b,
754 NVME_SC_SANITIZE_FAILED = 0x1c,
755 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d,
756 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e,
757 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f,
758 NVME_SC_NAMESPACE_IS_WRITE_PROTECTED = 0x20,
759 NVME_SC_COMMAND_INTERRUPTED = 0x21,
760 NVME_SC_TRANSIENT_TRANSPORT_ERROR = 0x22,
761
762 NVME_SC_LBA_OUT_OF_RANGE = 0x80,
763 NVME_SC_CAPACITY_EXCEEDED = 0x81,
764 NVME_SC_NAMESPACE_NOT_READY = 0x82,
765 NVME_SC_RESERVATION_CONFLICT = 0x83,
766 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
767 };
768
769 /* command specific status codes */
770 enum nvme_command_specific_status_code {
771 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00,
772 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01,
773 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02,
774 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03,
775 /* 0x04 - reserved */
776 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
777 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06,
778 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07,
779 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08,
780 NVME_SC_INVALID_LOG_PAGE = 0x09,
781 NVME_SC_INVALID_FORMAT = 0x0a,
782 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b,
783 NVME_SC_INVALID_QUEUE_DELETION = 0x0c,
784 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d,
785 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e,
786 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f,
787 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10,
788 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11,
789 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12,
790 NVME_SC_FW_ACT_PROHIBITED = 0x13,
791 NVME_SC_OVERLAPPING_RANGE = 0x14,
792 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15,
793 NVME_SC_NS_ID_UNAVAILABLE = 0x16,
794 /* 0x17 - reserved */
795 NVME_SC_NS_ALREADY_ATTACHED = 0x18,
796 NVME_SC_NS_IS_PRIVATE = 0x19,
797 NVME_SC_NS_NOT_ATTACHED = 0x1a,
798 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b,
799 NVME_SC_CTRLR_LIST_INVALID = 0x1c,
800 NVME_SC_SELF_TEST_IN_PROGRESS = 0x1d,
801 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e,
802 NVME_SC_INVALID_CTRLR_ID = 0x1f,
803 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20,
804 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21,
805 NVME_SC_INVALID_RESOURCE_ID = 0x22,
806 NVME_SC_SANITIZE_PROHIBITED_WPMRE = 0x23,
807 NVME_SC_ANA_GROUP_ID_INVALID = 0x24,
808 NVME_SC_ANA_ATTACH_FAILED = 0x25,
809
810 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80,
811 NVME_SC_INVALID_PROTECTION_INFO = 0x81,
812 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82,
813 };
814
815 /* media error status codes */
816 enum nvme_media_error_status_code {
817 NVME_SC_WRITE_FAULTS = 0x80,
818 NVME_SC_UNRECOVERED_READ_ERROR = 0x81,
819 NVME_SC_GUARD_CHECK_ERROR = 0x82,
820 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83,
821 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84,
822 NVME_SC_COMPARE_FAILURE = 0x85,
823 NVME_SC_ACCESS_DENIED = 0x86,
824 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87,
825 };
826
827 /* path related status codes */
828 enum nvme_path_related_status_code {
829 NVME_SC_INTERNAL_PATH_ERROR = 0x00,
830 NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01,
831 NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE = 0x02,
832 NVME_SC_ASYMMETRIC_ACCESS_TRANSITION = 0x03,
833 NVME_SC_CONTROLLER_PATHING_ERROR = 0x60,
834 NVME_SC_HOST_PATHING_ERROR = 0x70,
835 NVME_SC_COMMAND_ABOTHED_BY_HOST = 0x71,
836 };
837
838 /* admin opcodes */
839 enum nvme_admin_opcode {
840 NVME_OPC_DELETE_IO_SQ = 0x00,
841 NVME_OPC_CREATE_IO_SQ = 0x01,
842 NVME_OPC_GET_LOG_PAGE = 0x02,
843 /* 0x03 - reserved */
844 NVME_OPC_DELETE_IO_CQ = 0x04,
845 NVME_OPC_CREATE_IO_CQ = 0x05,
846 NVME_OPC_IDENTIFY = 0x06,
847 /* 0x07 - reserved */
848 NVME_OPC_ABORT = 0x08,
849 NVME_OPC_SET_FEATURES = 0x09,
850 NVME_OPC_GET_FEATURES = 0x0a,
851 /* 0x0b - reserved */
852 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c,
853 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d,
854 /* 0x0e-0x0f - reserved */
855 NVME_OPC_FIRMWARE_ACTIVATE = 0x10,
856 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11,
857 /* 0x12-0x13 - reserved */
858 NVME_OPC_DEVICE_SELF_TEST = 0x14,
859 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15,
860 /* 0x16-0x17 - reserved */
861 NVME_OPC_KEEP_ALIVE = 0x18,
862 NVME_OPC_DIRECTIVE_SEND = 0x19,
863 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a,
864 /* 0x1b - reserved */
865 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c,
866 NVME_OPC_NVME_MI_SEND = 0x1d,
867 NVME_OPC_NVME_MI_RECEIVE = 0x1e,
868 /* 0x1f-0x7b - reserved */
869 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c,
870
871 NVME_OPC_FORMAT_NVM = 0x80,
872 NVME_OPC_SECURITY_SEND = 0x81,
873 NVME_OPC_SECURITY_RECEIVE = 0x82,
874 /* 0x83 - reserved */
875 NVME_OPC_SANITIZE = 0x84,
876 /* 0x85 - reserved */
877 NVME_OPC_GET_LBA_STATUS = 0x86,
878 };
879
880 /* nvme nvm opcodes */
881 enum nvme_nvm_opcode {
882 NVME_OPC_FLUSH = 0x00,
883 NVME_OPC_WRITE = 0x01,
884 NVME_OPC_READ = 0x02,
885 /* 0x03 - reserved */
886 NVME_OPC_WRITE_UNCORRECTABLE = 0x04,
887 NVME_OPC_COMPARE = 0x05,
888 /* 0x06-0x07 - reserved */
889 NVME_OPC_WRITE_ZEROES = 0x08,
890 NVME_OPC_DATASET_MANAGEMENT = 0x09,
891 /* 0x0a-0x0b - reserved */
892 NVME_OPC_VERIFY = 0x0c,
893 NVME_OPC_RESERVATION_REGISTER = 0x0d,
894 NVME_OPC_RESERVATION_REPORT = 0x0e,
895 /* 0x0f-0x10 - reserved */
896 NVME_OPC_RESERVATION_ACQUIRE = 0x11,
897 /* 0x12-0x14 - reserved */
898 NVME_OPC_RESERVATION_RELEASE = 0x15,
899 };
900
901 enum nvme_feature {
902 /* 0x00 - reserved */
903 NVME_FEAT_ARBITRATION = 0x01,
904 NVME_FEAT_POWER_MANAGEMENT = 0x02,
905 NVME_FEAT_LBA_RANGE_TYPE = 0x03,
906 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04,
907 NVME_FEAT_ERROR_RECOVERY = 0x05,
908 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06,
909 NVME_FEAT_NUMBER_OF_QUEUES = 0x07,
910 NVME_FEAT_INTERRUPT_COALESCING = 0x08,
911 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
912 NVME_FEAT_WRITE_ATOMICITY = 0x0A,
913 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B,
914 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
915 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D,
916 NVME_FEAT_TIMESTAMP = 0x0E,
917 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F,
918 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10,
919 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11,
920 NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG = 0x12,
921 NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13,
922 NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14,
923 NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15,
924 NVME_FEAT_HOST_BEHAVIOR_SUPPORT = 0x16,
925 NVME_FEAT_SANITIZE_CONFIG = 0x17,
926 NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18,
927 /* 0x19-0x77 - reserved */
928 /* 0x78-0x7f - NVMe Management Interface */
929 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80,
930 NVME_FEAT_HOST_IDENTIFIER = 0x81,
931 NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82,
932 NVME_FEAT_RESERVATION_PERSISTENCE = 0x83,
933 NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84,
934 /* 0x85-0xBF - command set specific (reserved) */
935 /* 0xC0-0xFF - vendor specific */
936 };
937
938 enum nvme_dsm_attribute {
939 NVME_DSM_ATTR_INTEGRAL_READ = 0x1,
940 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2,
941 NVME_DSM_ATTR_DEALLOCATE = 0x4,
942 };
943
944 enum nvme_activate_action {
945 NVME_AA_REPLACE_NO_ACTIVATE = 0x0,
946 NVME_AA_REPLACE_ACTIVATE = 0x1,
947 NVME_AA_ACTIVATE = 0x2,
948 };
949
950 struct nvme_power_state {
951 /** Maximum Power */
952 uint16_t mp; /* Maximum Power */
953 uint8_t ps_rsvd1;
954 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */
955
956 uint32_t enlat; /* Entry Latency */
957 uint32_t exlat; /* Exit Latency */
958
959 uint8_t rrt; /* Relative Read Throughput */
960 uint8_t rrl; /* Relative Read Latency */
961 uint8_t rwt; /* Relative Write Throughput */
962 uint8_t rwl; /* Relative Write Latency */
963
964 uint16_t idlp; /* Idle Power */
965 uint8_t ips; /* Idle Power Scale */
966 uint8_t ps_rsvd8;
967
968 uint16_t actp; /* Active Power */
969 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */
970 uint8_t ps_rsvd10[9];
971 } __packed;
972
973 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state");
974
975 #define NVME_SERIAL_NUMBER_LENGTH 20
976 #define NVME_MODEL_NUMBER_LENGTH 40
977 #define NVME_FIRMWARE_REVISION_LENGTH 8
978
979 struct nvme_controller_data {
980 /* bytes 0-255: controller capabilities and features */
981
982 /** pci vendor id */
983 uint16_t vid;
984
985 /** pci subsystem vendor id */
986 uint16_t ssvid;
987
988 /** serial number */
989 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH];
990
991 /** model number */
992 uint8_t mn[NVME_MODEL_NUMBER_LENGTH];
993
994 /** firmware revision */
995 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH];
996
997 /** recommended arbitration burst */
998 uint8_t rab;
999
1000 /** ieee oui identifier */
1001 uint8_t ieee[3];
1002
1003 /** multi-interface capabilities */
1004 uint8_t mic;
1005
1006 /** maximum data transfer size */
1007 uint8_t mdts;
1008
1009 /** Controller ID */
1010 uint16_t ctrlr_id;
1011
1012 /** Version */
1013 uint32_t ver;
1014
1015 /** RTD3 Resume Latency */
1016 uint32_t rtd3r;
1017
1018 /** RTD3 Enter Latency */
1019 uint32_t rtd3e;
1020
1021 /** Optional Asynchronous Events Supported */
1022 uint32_t oaes; /* bitfield really */
1023
1024 /** Controller Attributes */
1025 uint32_t ctratt; /* bitfield really */
1026
1027 /** Read Recovery Levels Supported */
1028 uint16_t rrls;
1029
1030 uint8_t reserved1[9];
1031
1032 /** Controller Type */
1033 uint8_t cntrltype;
1034
1035 /** FRU Globally Unique Identifier */
1036 uint8_t fguid[16];
1037
1038 /** Command Retry Delay Time 1 */
1039 uint16_t crdt1;
1040
1041 /** Command Retry Delay Time 2 */
1042 uint16_t crdt2;
1043
1044 /** Command Retry Delay Time 3 */
1045 uint16_t crdt3;
1046
1047 uint8_t reserved2[122];
1048
1049 /* bytes 256-511: admin command set attributes */
1050
1051 /** optional admin command support */
1052 uint16_t oacs;
1053
1054 /** abort command limit */
1055 uint8_t acl;
1056
1057 /** asynchronous event request limit */
1058 uint8_t aerl;
1059
1060 /** firmware updates */
1061 uint8_t frmw;
1062
1063 /** log page attributes */
1064 uint8_t lpa;
1065
1066 /** error log page entries */
1067 uint8_t elpe;
1068
1069 /** number of power states supported */
1070 uint8_t npss;
1071
1072 /** admin vendor specific command configuration */
1073 uint8_t avscc;
1074
1075 /** Autonomous Power State Transition Attributes */
1076 uint8_t apsta;
1077
1078 /** Warning Composite Temperature Threshold */
1079 uint16_t wctemp;
1080
1081 /** Critical Composite Temperature Threshold */
1082 uint16_t cctemp;
1083
1084 /** Maximum Time for Firmware Activation */
1085 uint16_t mtfa;
1086
1087 /** Host Memory Buffer Preferred Size */
1088 uint32_t hmpre;
1089
1090 /** Host Memory Buffer Minimum Size */
1091 uint32_t hmmin;
1092
1093 /** Name space capabilities */
1094 struct {
1095 /* if nsmgmt, report tnvmcap and unvmcap */
1096 uint8_t tnvmcap[16];
1097 uint8_t unvmcap[16];
1098 } __packed untncap;
1099
1100 /** Replay Protected Memory Block Support */
1101 uint32_t rpmbs; /* Really a bitfield */
1102
1103 /** Extended Device Self-test Time */
1104 uint16_t edstt;
1105
1106 /** Device Self-test Options */
1107 uint8_t dsto; /* Really a bitfield */
1108
1109 /** Firmware Update Granularity */
1110 uint8_t fwug;
1111
1112 /** Keep Alive Support */
1113 uint16_t kas;
1114
1115 /** Host Controlled Thermal Management Attributes */
1116 uint16_t hctma; /* Really a bitfield */
1117
1118 /** Minimum Thermal Management Temperature */
1119 uint16_t mntmt;
1120
1121 /** Maximum Thermal Management Temperature */
1122 uint16_t mxtmt;
1123
1124 /** Sanitize Capabilities */
1125 uint32_t sanicap; /* Really a bitfield */
1126
1127 /** Host Memory Buffer Minimum Descriptor Entry Size */
1128 uint32_t hmminds;
1129
1130 /** Host Memory Maximum Descriptors Entries */
1131 uint16_t hmmaxd;
1132
1133 /** NVM Set Identifier Maximum */
1134 uint16_t nsetidmax;
1135
1136 /** Endurance Group Identifier Maximum */
1137 uint16_t endgidmax;
1138
1139 /** ANA Transition Time */
1140 uint8_t anatt;
1141
1142 /** Asymmetric Namespace Access Capabilities */
1143 uint8_t anacap;
1144
1145 /** ANA Group Identifier Maximum */
1146 uint32_t anagrpmax;
1147
1148 /** Number of ANA Group Identifiers */
1149 uint32_t nanagrpid;
1150
1151 /** Persistent Event Log Size */
1152 uint32_t pels;
1153
1154 uint8_t reserved3[156];
1155 /* bytes 512-703: nvm command set attributes */
1156
1157 /** submission queue entry size */
1158 uint8_t sqes;
1159
1160 /** completion queue entry size */
1161 uint8_t cqes;
1162
1163 /** Maximum Outstanding Commands */
1164 uint16_t maxcmd;
1165
1166 /** number of namespaces */
1167 uint32_t nn;
1168
1169 /** optional nvm command support */
1170 uint16_t oncs;
1171
1172 /** fused operation support */
1173 uint16_t fuses;
1174
1175 /** format nvm attributes */
1176 uint8_t fna;
1177
1178 /** volatile write cache */
1179 uint8_t vwc;
1180
1181 /** Atomic Write Unit Normal */
1182 uint16_t awun;
1183
1184 /** Atomic Write Unit Power Fail */
1185 uint16_t awupf;
1186
1187 /** NVM Vendor Specific Command Configuration */
1188 uint8_t nvscc;
1189
1190 /** Namespace Write Protection Capabilities */
1191 uint8_t nwpc;
1192
1193 /** Atomic Compare & Write Unit */
1194 uint16_t acwu;
1195 uint16_t reserved6;
1196
1197 /** SGL Support */
1198 uint32_t sgls;
1199
1200 /** Maximum Number of Allowed Namespaces */
1201 uint32_t mnan;
1202
1203 /* bytes 540-767: Reserved */
1204 uint8_t reserved7[224];
1205
1206 /** NVM Subsystem NVMe Qualified Name */
1207 uint8_t subnqn[256];
1208
1209 /* bytes 1024-1791: Reserved */
1210 uint8_t reserved8[768];
1211
1212 /* bytes 1792-2047: NVMe over Fabrics specification */
1213 uint8_t reserved9[256];
1214
1215 /* bytes 2048-3071: power state descriptors */
1216 struct nvme_power_state power_state[32];
1217
1218 /* bytes 3072-4095: vendor specific */
1219 uint8_t vs[1024];
1220 } __packed __aligned(4);
1221
1222 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data");
1223
1224 struct nvme_namespace_data {
1225 /** namespace size */
1226 uint64_t nsze;
1227
1228 /** namespace capacity */
1229 uint64_t ncap;
1230
1231 /** namespace utilization */
1232 uint64_t nuse;
1233
1234 /** namespace features */
1235 uint8_t nsfeat;
1236
1237 /** number of lba formats */
1238 uint8_t nlbaf;
1239
1240 /** formatted lba size */
1241 uint8_t flbas;
1242
1243 /** metadata capabilities */
1244 uint8_t mc;
1245
1246 /** end-to-end data protection capabilities */
1247 uint8_t dpc;
1248
1249 /** end-to-end data protection type settings */
1250 uint8_t dps;
1251
1252 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
1253 uint8_t nmic;
1254
1255 /** Reservation Capabilities */
1256 uint8_t rescap;
1257
1258 /** Format Progress Indicator */
1259 uint8_t fpi;
1260
1261 /** Deallocate Logical Block Features */
1262 uint8_t dlfeat;
1263
1264 /** Namespace Atomic Write Unit Normal */
1265 uint16_t nawun;
1266
1267 /** Namespace Atomic Write Unit Power Fail */
1268 uint16_t nawupf;
1269
1270 /** Namespace Atomic Compare & Write Unit */
1271 uint16_t nacwu;
1272
1273 /** Namespace Atomic Boundary Size Normal */
1274 uint16_t nabsn;
1275
1276 /** Namespace Atomic Boundary Offset */
1277 uint16_t nabo;
1278
1279 /** Namespace Atomic Boundary Size Power Fail */
1280 uint16_t nabspf;
1281
1282 /** Namespace Optimal IO Boundary */
1283 uint16_t noiob;
1284
1285 /** NVM Capacity */
1286 uint8_t nvmcap[16];
1287
1288 /** Namespace Preferred Write Granularity */
1289 uint16_t npwg;
1290
1291 /** Namespace Preferred Write Alignment */
1292 uint16_t npwa;
1293
1294 /** Namespace Preferred Deallocate Granularity */
1295 uint16_t npdg;
1296
1297 /** Namespace Preferred Deallocate Alignment */
1298 uint16_t npda;
1299
1300 /** Namespace Optimal Write Size */
1301 uint16_t nows;
1302
1303 /* bytes 74-91: Reserved */
1304 uint8_t reserved5[18];
1305
1306 /** ANA Group Identifier */
1307 uint32_t anagrpid;
1308
1309 /* bytes 96-98: Reserved */
1310 uint8_t reserved6[3];
1311
1312 /** Namespace Attributes */
1313 uint8_t nsattr;
1314
1315 /** NVM Set Identifier */
1316 uint16_t nvmsetid;
1317
1318 /** Endurance Group Identifier */
1319 uint16_t endgid;
1320
1321 /** Namespace Globally Unique Identifier */
1322 uint8_t nguid[16];
1323
1324 /** IEEE Extended Unique Identifier */
1325 uint8_t eui64[8];
1326
1327 /** lba format support */
1328 uint32_t lbaf[16];
1329
1330 uint8_t reserved7[192];
1331
1332 uint8_t vendor_specific[3712];
1333 } __packed __aligned(4);
1334
1335 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data");
1336
1337 enum nvme_log_page {
1338 /* 0x00 - reserved */
1339 NVME_LOG_ERROR = 0x01,
1340 NVME_LOG_HEALTH_INFORMATION = 0x02,
1341 NVME_LOG_FIRMWARE_SLOT = 0x03,
1342 NVME_LOG_CHANGED_NAMESPACE = 0x04,
1343 NVME_LOG_COMMAND_EFFECT = 0x05,
1344 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1345 NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07,
1346 NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08,
1347 NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09,
1348 NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a,
1349 NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b,
1350 NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS = 0x0c,
1351 NVME_LOG_PERSISTENT_EVENT_LOG = 0x0d,
1352 NVME_LOG_LBA_STATUS_INFORMATION = 0x0e,
1353 NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f,
1354 /* 0x06-0x7F - reserved */
1355 /* 0x80-0xBF - I/O command set specific */
1356 NVME_LOG_RES_NOTIFICATION = 0x80,
1357 NVME_LOG_SANITIZE_STATUS = 0x81,
1358 /* 0x82-0xBF - reserved */
1359 /* 0xC0-0xFF - vendor specific */
1360
1361 /*
1362 * The following are Intel Specific log pages, but they seem
1363 * to be widely implemented.
1364 */
1365 INTEL_LOG_READ_LAT_LOG = 0xc1,
1366 INTEL_LOG_WRITE_LAT_LOG = 0xc2,
1367 INTEL_LOG_TEMP_STATS = 0xc5,
1368 INTEL_LOG_ADD_SMART = 0xca,
1369 INTEL_LOG_DRIVE_MKT_NAME = 0xdd,
1370
1371 /*
1372 * HGST log page, with lots ofs sub pages.
1373 */
1374 HGST_INFO_LOG = 0xc1,
1375 };
1376
1377 struct nvme_error_information_entry {
1378 uint64_t error_count;
1379 uint16_t sqid;
1380 uint16_t cid;
1381 uint16_t status;
1382 uint16_t error_location;
1383 uint64_t lba;
1384 uint32_t nsid;
1385 uint8_t vendor_specific;
1386 uint8_t trtype;
1387 uint16_t reserved30;
1388 uint64_t csi;
1389 uint16_t ttsi;
1390 uint8_t reserved[22];
1391 } __packed __aligned(4);
1392
1393 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry");
1394
1395 struct nvme_health_information_page {
1396 uint8_t critical_warning;
1397 uint16_t temperature;
1398 uint8_t available_spare;
1399 uint8_t available_spare_threshold;
1400 uint8_t percentage_used;
1401
1402 uint8_t reserved[26];
1403
1404 /*
1405 * Note that the following are 128-bit values, but are
1406 * defined as an array of 2 64-bit values.
1407 */
1408 /* Data Units Read is always in 512-byte units. */
1409 uint64_t data_units_read[2];
1410 /* Data Units Written is always in 512-byte units. */
1411 uint64_t data_units_written[2];
1412 /* For NVM command set, this includes Compare commands. */
1413 uint64_t host_read_commands[2];
1414 uint64_t host_write_commands[2];
1415 /* Controller Busy Time is reported in minutes. */
1416 uint64_t controller_busy_time[2];
1417 uint64_t power_cycles[2];
1418 uint64_t power_on_hours[2];
1419 uint64_t unsafe_shutdowns[2];
1420 uint64_t media_errors[2];
1421 uint64_t num_error_info_log_entries[2];
1422 uint32_t warning_temp_time;
1423 uint32_t error_temp_time;
1424 uint16_t temp_sensor[8];
1425 /* Thermal Management Temperature 1 Transition Count */
1426 uint32_t tmt1tc;
1427 /* Thermal Management Temperature 2 Transition Count */
1428 uint32_t tmt2tc;
1429 /* Total Time For Thermal Management Temperature 1 */
1430 uint32_t ttftmt1;
1431 /* Total Time For Thermal Management Temperature 2 */
1432 uint32_t ttftmt2;
1433
1434 uint8_t reserved2[280];
1435 } __packed __aligned(4);
1436
1437 /* Currently sparse/smatch incorrectly packs this struct in some situations. */
1438 #ifndef __CHECKER__
1439 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page");
1440 #endif
1441
1442 struct nvme_firmware_page {
1443 uint8_t afi;
1444 uint8_t reserved[7];
1445 uint64_t revision[7]; /* revisions for 7 slots */
1446 uint8_t reserved2[448];
1447 } __packed __aligned(4);
1448
1449 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page");
1450
1451 struct nvme_ns_list {
1452 uint32_t ns[1024];
1453 } __packed __aligned(4);
1454
1455 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list");
1456
1457 struct nvme_command_effects_page {
1458 uint32_t acs[256];
1459 uint32_t iocs[256];
1460 uint8_t reserved[2048];
1461 } __packed __aligned(4);
1462
1463 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096,
1464 "bad size for nvme_command_effects_page");
1465
1466 struct nvme_device_self_test_page {
1467 uint8_t curr_operation;
1468 uint8_t curr_compl;
1469 uint8_t rsvd2[2];
1470 struct {
1471 uint8_t status;
1472 uint8_t segment_num;
1473 uint8_t valid_diag_info;
1474 uint8_t rsvd3;
1475 uint64_t poh;
1476 uint32_t nsid;
1477 /* Define as an array to simplify alignment issues */
1478 uint8_t failing_lba[8];
1479 uint8_t status_code_type;
1480 uint8_t status_code;
1481 uint8_t vendor_specific[2];
1482 } __packed result[20];
1483 } __packed __aligned(4);
1484
1485 /* Currently sparse/smatch incorrectly packs this struct in some situations. */
1486 #ifndef __CHECKER__
1487 _Static_assert(sizeof(struct nvme_device_self_test_page) == 564,
1488 "bad size for nvme_device_self_test_page");
1489 #endif
1490
1491 struct nvme_res_notification_page {
1492 uint64_t log_page_count;
1493 uint8_t log_page_type;
1494 uint8_t available_log_pages;
1495 uint8_t reserved2;
1496 uint32_t nsid;
1497 uint8_t reserved[48];
1498 } __packed __aligned(4);
1499
1500 _Static_assert(sizeof(struct nvme_res_notification_page) == 64,
1501 "bad size for nvme_res_notification_page");
1502
1503 struct nvme_sanitize_status_page {
1504 uint16_t sprog;
1505 uint16_t sstat;
1506 uint32_t scdw10;
1507 uint32_t etfo;
1508 uint32_t etfbe;
1509 uint32_t etfce;
1510 uint32_t etfownd;
1511 uint32_t etfbewnd;
1512 uint32_t etfcewnd;
1513 uint8_t reserved[480];
1514 } __packed __aligned(4);
1515
1516 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512,
1517 "bad size for nvme_sanitize_status_page");
1518
1519 struct intel_log_temp_stats {
1520 uint64_t current;
1521 uint64_t overtemp_flag_last;
1522 uint64_t overtemp_flag_life;
1523 uint64_t max_temp;
1524 uint64_t min_temp;
1525 uint64_t _rsvd[5];
1526 uint64_t max_oper_temp;
1527 uint64_t min_oper_temp;
1528 uint64_t est_offset;
1529 } __packed __aligned(4);
1530
1531 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats");
1532
1533 struct nvme_resv_reg_ctrlr {
1534 uint16_t ctrlr_id; /* Controller ID */
1535 uint8_t rcsts; /* Reservation Status */
1536 uint8_t reserved3[5];
1537 uint64_t hostid; /* Host Identifier */
1538 uint64_t rkey; /* Reservation Key */
1539 } __packed __aligned(4);
1540
1541 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr");
1542
1543 struct nvme_resv_reg_ctrlr_ext {
1544 uint16_t ctrlr_id; /* Controller ID */
1545 uint8_t rcsts; /* Reservation Status */
1546 uint8_t reserved3[5];
1547 uint64_t rkey; /* Reservation Key */
1548 uint64_t hostid[2]; /* Host Identifier */
1549 uint8_t reserved32[32];
1550 } __packed __aligned(4);
1551
1552 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext");
1553
1554 struct nvme_resv_status {
1555 uint32_t gen; /* Generation */
1556 uint8_t rtype; /* Reservation Type */
1557 uint8_t regctl[2]; /* Number of Registered Controllers */
1558 uint8_t reserved7[2];
1559 uint8_t ptpls; /* Persist Through Power Loss State */
1560 uint8_t reserved10[14];
1561 struct nvme_resv_reg_ctrlr ctrlr[0];
1562 } __packed __aligned(4);
1563
1564 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status");
1565
1566 struct nvme_resv_status_ext {
1567 uint32_t gen; /* Generation */
1568 uint8_t rtype; /* Reservation Type */
1569 uint8_t regctl[2]; /* Number of Registered Controllers */
1570 uint8_t reserved7[2];
1571 uint8_t ptpls; /* Persist Through Power Loss State */
1572 uint8_t reserved10[14];
1573 uint8_t reserved24[40];
1574 struct nvme_resv_reg_ctrlr_ext ctrlr[0];
1575 } __packed __aligned(4);
1576
1577 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext");
1578
1579 #define NVME_TEST_MAX_THREADS 128
1580
1581 struct nvme_io_test {
1582 enum nvme_nvm_opcode opc;
1583 uint32_t size;
1584 uint32_t time; /* in seconds */
1585 uint32_t num_threads;
1586 uint32_t flags;
1587 uint64_t io_completed[NVME_TEST_MAX_THREADS];
1588 };
1589
1590 enum nvme_io_test_flags {
1591 /*
1592 * Specifies whether dev_refthread/dev_relthread should be
1593 * called during NVME_BIO_TEST. Ignored for other test
1594 * types.
1595 */
1596 NVME_TEST_FLAG_REFTHREAD = 0x1,
1597 };
1598
1599 struct nvme_pt_command {
1600 /*
1601 * cmd is used to specify a passthrough command to a controller or
1602 * namespace.
1603 *
1604 * The following fields from cmd may be specified by the caller:
1605 * * opc (opcode)
1606 * * nsid (namespace id) - for admin commands only
1607 * * cdw10-cdw15
1608 *
1609 * Remaining fields must be set to 0 by the caller.
1610 */
1611 struct nvme_command cmd;
1612
1613 /*
1614 * cpl returns completion status for the passthrough command
1615 * specified by cmd.
1616 *
1617 * The following fields will be filled out by the driver, for
1618 * consumption by the caller:
1619 * * cdw0
1620 * * status (except for phase)
1621 *
1622 * Remaining fields will be set to 0 by the driver.
1623 */
1624 struct nvme_completion cpl;
1625
1626 /* buf is the data buffer associated with this passthrough command. */
1627 void * buf;
1628
1629 /*
1630 * len is the length of the data buffer associated with this
1631 * passthrough command.
1632 */
1633 uint32_t len;
1634
1635 /*
1636 * is_read = 1 if the passthrough command will read data into the
1637 * supplied buffer from the controller.
1638 *
1639 * is_read = 0 if the passthrough command will write data from the
1640 * supplied buffer to the controller.
1641 */
1642 uint32_t is_read;
1643
1644 /*
1645 * driver_lock is used by the driver only. It must be set to 0
1646 * by the caller.
1647 */
1648 struct mtx * driver_lock;
1649 };
1650
1651 struct nvme_get_nsid {
1652 char cdev[SPECNAMELEN + 1];
1653 uint32_t nsid;
1654 };
1655
1656 struct nvme_hmb_desc {
1657 uint64_t addr;
1658 uint32_t size;
1659 uint32_t reserved;
1660 };
1661
1662 #define nvme_completion_is_error(cpl) \
1663 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0)
1664
1665 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen);
1666
1667 #ifdef _KERNEL
1668
1669 struct bio;
1670 struct thread;
1671
1672 struct nvme_namespace;
1673 struct nvme_controller;
1674 struct nvme_consumer;
1675
1676 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
1677
1678 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
1679 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
1680 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
1681 uint32_t, void *, uint32_t);
1682 typedef void (*nvme_cons_fail_fn_t)(void *);
1683
1684 enum nvme_namespace_flags {
1685 NVME_NS_DEALLOCATE_SUPPORTED = 0x1,
1686 NVME_NS_FLUSH_SUPPORTED = 0x2,
1687 };
1688
1689 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1690 struct nvme_pt_command *pt,
1691 uint32_t nsid, int is_user_buffer,
1692 int is_admin_cmd);
1693
1694 /* Admin functions */
1695 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
1696 uint8_t feature, uint32_t cdw11,
1697 uint32_t cdw12, uint32_t cdw13,
1698 uint32_t cdw14, uint32_t cdw15,
1699 void *payload, uint32_t payload_size,
1700 nvme_cb_fn_t cb_fn, void *cb_arg);
1701 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
1702 uint8_t feature, uint32_t cdw11,
1703 void *payload, uint32_t payload_size,
1704 nvme_cb_fn_t cb_fn, void *cb_arg);
1705 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
1706 uint8_t log_page, uint32_t nsid,
1707 void *payload, uint32_t payload_size,
1708 nvme_cb_fn_t cb_fn, void *cb_arg);
1709
1710 /* NVM I/O functions */
1711 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
1712 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1713 void *cb_arg);
1714 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
1715 nvme_cb_fn_t cb_fn, void *cb_arg);
1716 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
1717 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1718 void *cb_arg);
1719 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
1720 nvme_cb_fn_t cb_fn, void *cb_arg);
1721 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
1722 uint8_t num_ranges, nvme_cb_fn_t cb_fn,
1723 void *cb_arg);
1724 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
1725 void *cb_arg);
1726 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset,
1727 size_t len);
1728
1729 /* Registration functions */
1730 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn,
1731 nvme_cons_ctrlr_fn_t ctrlr_fn,
1732 nvme_cons_async_fn_t async_fn,
1733 nvme_cons_fail_fn_t fail_fn);
1734 void nvme_unregister_consumer(struct nvme_consumer *consumer);
1735
1736 /* Controller helper functions */
1737 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
1738 const struct nvme_controller_data *
1739 nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
1740 static inline bool
1741 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd)
1742 {
1743 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */
1744 return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) &
1745 NVME_CTRLR_DATA_ONCS_DSM_MASK);
1746 }
1747
1748 /* Namespace helper functions */
1749 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
1750 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns);
1751 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns);
1752 uint64_t nvme_ns_get_size(struct nvme_namespace *ns);
1753 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns);
1754 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns);
1755 const char * nvme_ns_get_model_number(struct nvme_namespace *ns);
1756 const struct nvme_namespace_data *
1757 nvme_ns_get_data(struct nvme_namespace *ns);
1758 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns);
1759
1760 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
1761 nvme_cb_fn_t cb_fn);
1762 int nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd,
1763 caddr_t arg, int flag, struct thread *td);
1764
1765 /*
1766 * Command building helper functions -- shared with CAM
1767 * These functions assume allocator zeros out cmd structure
1768 * CAM's xpt_get_ccb and the request allocator for nvme both
1769 * do zero'd allocations.
1770 */
1771 static inline
1772 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid)
1773 {
1774
1775 cmd->opc = NVME_OPC_FLUSH;
1776 cmd->nsid = htole32(nsid);
1777 }
1778
1779 static inline
1780 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid,
1781 uint64_t lba, uint32_t count)
1782 {
1783 cmd->opc = rwcmd;
1784 cmd->nsid = htole32(nsid);
1785 cmd->cdw10 = htole32(lba & 0xffffffffu);
1786 cmd->cdw11 = htole32(lba >> 32);
1787 cmd->cdw12 = htole32(count-1);
1788 }
1789
1790 static inline
1791 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid,
1792 uint64_t lba, uint32_t count)
1793 {
1794 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count);
1795 }
1796
1797 static inline
1798 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid,
1799 uint64_t lba, uint32_t count)
1800 {
1801 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count);
1802 }
1803
1804 static inline
1805 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid,
1806 uint32_t num_ranges)
1807 {
1808 cmd->opc = NVME_OPC_DATASET_MANAGEMENT;
1809 cmd->nsid = htole32(nsid);
1810 cmd->cdw10 = htole32(num_ranges - 1);
1811 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE);
1812 }
1813
1814 extern int nvme_use_nvd;
1815
1816 #endif /* _KERNEL */
1817
1818 /* Endianess conversion functions for NVMe structs */
1819 static inline
1820 void nvme_completion_swapbytes(struct nvme_completion *s __unused)
1821 {
1822 #ifndef _LITTLE_ENDIAN
1823
1824 s->cdw0 = le32toh(s->cdw0);
1825 /* omit rsvd1 */
1826 s->sqhd = le16toh(s->sqhd);
1827 s->sqid = le16toh(s->sqid);
1828 /* omit cid */
1829 s->status = le16toh(s->status);
1830 #endif
1831 }
1832
1833 static inline
1834 void nvme_power_state_swapbytes(struct nvme_power_state *s __unused)
1835 {
1836 #ifndef _LITTLE_ENDIAN
1837
1838 s->mp = le16toh(s->mp);
1839 s->enlat = le32toh(s->enlat);
1840 s->exlat = le32toh(s->exlat);
1841 s->idlp = le16toh(s->idlp);
1842 s->actp = le16toh(s->actp);
1843 #endif
1844 }
1845
1846 static inline
1847 void nvme_controller_data_swapbytes(struct nvme_controller_data *s __unused)
1848 {
1849 #ifndef _LITTLE_ENDIAN
1850 int i;
1851
1852 s->vid = le16toh(s->vid);
1853 s->ssvid = le16toh(s->ssvid);
1854 s->ctrlr_id = le16toh(s->ctrlr_id);
1855 s->ver = le32toh(s->ver);
1856 s->rtd3r = le32toh(s->rtd3r);
1857 s->rtd3e = le32toh(s->rtd3e);
1858 s->oaes = le32toh(s->oaes);
1859 s->ctratt = le32toh(s->ctratt);
1860 s->rrls = le16toh(s->rrls);
1861 s->crdt1 = le16toh(s->crdt1);
1862 s->crdt2 = le16toh(s->crdt2);
1863 s->crdt3 = le16toh(s->crdt3);
1864 s->oacs = le16toh(s->oacs);
1865 s->wctemp = le16toh(s->wctemp);
1866 s->cctemp = le16toh(s->cctemp);
1867 s->mtfa = le16toh(s->mtfa);
1868 s->hmpre = le32toh(s->hmpre);
1869 s->hmmin = le32toh(s->hmmin);
1870 s->rpmbs = le32toh(s->rpmbs);
1871 s->edstt = le16toh(s->edstt);
1872 s->kas = le16toh(s->kas);
1873 s->hctma = le16toh(s->hctma);
1874 s->mntmt = le16toh(s->mntmt);
1875 s->mxtmt = le16toh(s->mxtmt);
1876 s->sanicap = le32toh(s->sanicap);
1877 s->hmminds = le32toh(s->hmminds);
1878 s->hmmaxd = le16toh(s->hmmaxd);
1879 s->nsetidmax = le16toh(s->nsetidmax);
1880 s->endgidmax = le16toh(s->endgidmax);
1881 s->anagrpmax = le32toh(s->anagrpmax);
1882 s->nanagrpid = le32toh(s->nanagrpid);
1883 s->pels = le32toh(s->pels);
1884 s->maxcmd = le16toh(s->maxcmd);
1885 s->nn = le32toh(s->nn);
1886 s->oncs = le16toh(s->oncs);
1887 s->fuses = le16toh(s->fuses);
1888 s->awun = le16toh(s->awun);
1889 s->awupf = le16toh(s->awupf);
1890 s->acwu = le16toh(s->acwu);
1891 s->sgls = le32toh(s->sgls);
1892 s->mnan = le32toh(s->mnan);
1893 for (i = 0; i < 32; i++)
1894 nvme_power_state_swapbytes(&s->power_state[i]);
1895 #endif
1896 }
1897
1898 static inline
1899 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s __unused)
1900 {
1901 #ifndef _LITTLE_ENDIAN
1902 int i;
1903
1904 s->nsze = le64toh(s->nsze);
1905 s->ncap = le64toh(s->ncap);
1906 s->nuse = le64toh(s->nuse);
1907 s->nawun = le16toh(s->nawun);
1908 s->nawupf = le16toh(s->nawupf);
1909 s->nacwu = le16toh(s->nacwu);
1910 s->nabsn = le16toh(s->nabsn);
1911 s->nabo = le16toh(s->nabo);
1912 s->nabspf = le16toh(s->nabspf);
1913 s->noiob = le16toh(s->noiob);
1914 s->npwg = le16toh(s->npwg);
1915 s->npwa = le16toh(s->npwa);
1916 s->npdg = le16toh(s->npdg);
1917 s->npda = le16toh(s->npda);
1918 s->nows = le16toh(s->nows);
1919 s->anagrpid = le32toh(s->anagrpid);
1920 s->nvmsetid = le16toh(s->nvmsetid);
1921 s->endgid = le16toh(s->endgid);
1922 for (i = 0; i < 16; i++)
1923 s->lbaf[i] = le32toh(s->lbaf[i]);
1924 #endif
1925 }
1926
1927 static inline
1928 void nvme_error_information_entry_swapbytes(
1929 struct nvme_error_information_entry *s __unused)
1930 {
1931 #ifndef _LITTLE_ENDIAN
1932
1933 s->error_count = le64toh(s->error_count);
1934 s->sqid = le16toh(s->sqid);
1935 s->cid = le16toh(s->cid);
1936 s->status = le16toh(s->status);
1937 s->error_location = le16toh(s->error_location);
1938 s->lba = le64toh(s->lba);
1939 s->nsid = le32toh(s->nsid);
1940 s->csi = le64toh(s->csi);
1941 s->ttsi = le16toh(s->ttsi);
1942 #endif
1943 }
1944
1945 static inline
1946 void nvme_le128toh(void *p __unused)
1947 {
1948 #ifndef _LITTLE_ENDIAN
1949 /* Swap 16 bytes in place */
1950 char *tmp = (char*)p;
1951 char b;
1952 int i;
1953 for (i = 0; i < 8; i++) {
1954 b = tmp[i];
1955 tmp[i] = tmp[15-i];
1956 tmp[15-i] = b;
1957 }
1958 #endif
1959 }
1960
1961 static inline
1962 void nvme_health_information_page_swapbytes(
1963 struct nvme_health_information_page *s __unused)
1964 {
1965 #ifndef _LITTLE_ENDIAN
1966 int i;
1967
1968 s->temperature = le16toh(s->temperature);
1969 nvme_le128toh((void *)s->data_units_read);
1970 nvme_le128toh((void *)s->data_units_written);
1971 nvme_le128toh((void *)s->host_read_commands);
1972 nvme_le128toh((void *)s->host_write_commands);
1973 nvme_le128toh((void *)s->controller_busy_time);
1974 nvme_le128toh((void *)s->power_cycles);
1975 nvme_le128toh((void *)s->power_on_hours);
1976 nvme_le128toh((void *)s->unsafe_shutdowns);
1977 nvme_le128toh((void *)s->media_errors);
1978 nvme_le128toh((void *)s->num_error_info_log_entries);
1979 s->warning_temp_time = le32toh(s->warning_temp_time);
1980 s->error_temp_time = le32toh(s->error_temp_time);
1981 for (i = 0; i < 8; i++)
1982 s->temp_sensor[i] = le16toh(s->temp_sensor[i]);
1983 s->tmt1tc = le32toh(s->tmt1tc);
1984 s->tmt2tc = le32toh(s->tmt2tc);
1985 s->ttftmt1 = le32toh(s->ttftmt1);
1986 s->ttftmt2 = le32toh(s->ttftmt2);
1987 #endif
1988 }
1989
1990 static inline
1991 void nvme_firmware_page_swapbytes(struct nvme_firmware_page *s __unused)
1992 {
1993 #ifndef _LITTLE_ENDIAN
1994 int i;
1995
1996 for (i = 0; i < 7; i++)
1997 s->revision[i] = le64toh(s->revision[i]);
1998 #endif
1999 }
2000
2001 static inline
2002 void nvme_ns_list_swapbytes(struct nvme_ns_list *s __unused)
2003 {
2004 #ifndef _LITTLE_ENDIAN
2005 int i;
2006
2007 for (i = 0; i < 1024; i++)
2008 s->ns[i] = le32toh(s->ns[i]);
2009 #endif
2010 }
2011
2012 static inline
2013 void nvme_command_effects_page_swapbytes(
2014 struct nvme_command_effects_page *s __unused)
2015 {
2016 #ifndef _LITTLE_ENDIAN
2017 int i;
2018
2019 for (i = 0; i < 256; i++)
2020 s->acs[i] = le32toh(s->acs[i]);
2021 for (i = 0; i < 256; i++)
2022 s->iocs[i] = le32toh(s->iocs[i]);
2023 #endif
2024 }
2025
2026 static inline
2027 void nvme_res_notification_page_swapbytes(
2028 struct nvme_res_notification_page *s __unused)
2029 {
2030 #ifndef _LITTLE_ENDIAN
2031 s->log_page_count = le64toh(s->log_page_count);
2032 s->nsid = le32toh(s->nsid);
2033 #endif
2034 }
2035
2036 static inline
2037 void nvme_sanitize_status_page_swapbytes(
2038 struct nvme_sanitize_status_page *s __unused)
2039 {
2040 #ifndef _LITTLE_ENDIAN
2041 s->sprog = le16toh(s->sprog);
2042 s->sstat = le16toh(s->sstat);
2043 s->scdw10 = le32toh(s->scdw10);
2044 s->etfo = le32toh(s->etfo);
2045 s->etfbe = le32toh(s->etfbe);
2046 s->etfce = le32toh(s->etfce);
2047 s->etfownd = le32toh(s->etfownd);
2048 s->etfbewnd = le32toh(s->etfbewnd);
2049 s->etfcewnd = le32toh(s->etfcewnd);
2050 #endif
2051 }
2052
2053 static inline
2054 void intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s __unused)
2055 {
2056 #ifndef _LITTLE_ENDIAN
2057
2058 s->current = le64toh(s->current);
2059 s->overtemp_flag_last = le64toh(s->overtemp_flag_last);
2060 s->overtemp_flag_life = le64toh(s->overtemp_flag_life);
2061 s->max_temp = le64toh(s->max_temp);
2062 s->min_temp = le64toh(s->min_temp);
2063 /* omit _rsvd[] */
2064 s->max_oper_temp = le64toh(s->max_oper_temp);
2065 s->min_oper_temp = le64toh(s->min_oper_temp);
2066 s->est_offset = le64toh(s->est_offset);
2067 #endif
2068 }
2069
2070 static inline
2071 void nvme_resv_status_swapbytes(struct nvme_resv_status *s __unused,
2072 size_t size __unused)
2073 {
2074 #ifndef _LITTLE_ENDIAN
2075 size_t i, n;
2076
2077 s->gen = le32toh(s->gen);
2078 n = (s->regctl[1] << 8) | s->regctl[0];
2079 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2080 for (i = 0; i < n; i++) {
2081 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2082 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid);
2083 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2084 }
2085 #endif
2086 }
2087
2088 static inline
2089 void nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s __unused,
2090 size_t size __unused)
2091 {
2092 #ifndef _LITTLE_ENDIAN
2093 size_t i, n;
2094
2095 s->gen = le32toh(s->gen);
2096 n = (s->regctl[1] << 8) | s->regctl[0];
2097 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2098 for (i = 0; i < n; i++) {
2099 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2100 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2101 nvme_le128toh((void *)s->ctrlr[i].hostid);
2102 }
2103 #endif
2104 }
2105
2106 static inline void
2107 nvme_device_self_test_swapbytes(struct nvme_device_self_test_page *s __unused)
2108 {
2109 #ifndef _LITTLE_ENDIAN
2110 uint8_t *tmp;
2111 uint32_t r, i;
2112 uint8_t b;
2113
2114 for (r = 0; r < 20; r++) {
2115 s->result[r].poh = le64toh(s->result[r].poh);
2116 s->result[r].nsid = le32toh(s->result[r].nsid);
2117 /* Unaligned 64-bit loads fail on some architectures */
2118 tmp = s->result[r].failing_lba;
2119 for (i = 0; i < 4; i++) {
2120 b = tmp[i];
2121 tmp[i] = tmp[7-i];
2122 tmp[7-i] = b;
2123 }
2124 }
2125 #endif
2126 }
2127 #endif /* __NVME_H__ */
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