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15325 bhyve upstream sync 2023 January
[illumos-gate.git] / usr / src / cmd / bhyve / pci_xhci.c
blob278df0d35574b4292386abb56815fdb071fb99f7
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com>
5 * Copyright 2018 Joyent, Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29 /*
30 XHCI options:
31 -s <n>,xhci,{devices}
32
33 devices:
34 tablet USB tablet mouse
35 */
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38
39 #include <sys/param.h>
40 #include <sys/uio.h>
41 #include <sys/types.h>
42 #include <sys/queue.h>
43
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <stdint.h>
47 #include <string.h>
48 #include <errno.h>
49 #include <pthread.h>
50 #include <unistd.h>
51
52 #include <dev/usb/usbdi.h>
53 #include <dev/usb/usb.h>
54 #include <dev/usb/usb_freebsd.h>
55 #include <xhcireg.h>
56
57 #include "bhyverun.h"
58 #include "config.h"
59 #include "debug.h"
60 #include "pci_emul.h"
61 #include "pci_xhci.h"
62 #include "usb_emul.h"
63
64
65 static int xhci_debug = 0;
66 #define DPRINTF(params) if (xhci_debug) PRINTLN params
67 #define WPRINTF(params) PRINTLN params
68
69
70 #define XHCI_NAME "xhci"
71 #define XHCI_MAX_DEVS 8 /* 4 USB3 + 4 USB2 devs */
72
73 #define XHCI_MAX_SLOTS 64 /* min allowed by Windows drivers */
74
75 /*
76 * XHCI data structures can be up to 64k, but limit paddr_guest2host mapping
77 * to 4k to avoid going over the guest physical memory barrier.
78 */
79 #define XHCI_PADDR_SZ 4096 /* paddr_guest2host max size */
80
81 #define XHCI_ERST_MAX 0 /* max 2^entries event ring seg tbl */
82
83 #define XHCI_CAPLEN (4*8) /* offset of op register space */
84 #define XHCI_HCCPRAMS2 0x1C /* offset of HCCPARAMS2 register */
85 #define XHCI_PORTREGS_START 0x400
86 #define XHCI_DOORBELL_MAX 256
87
88 #define XHCI_STREAMS_MAX 1 /* 4-15 in XHCI spec */
89
90 /* caplength and hci-version registers */
91 #define XHCI_SET_CAPLEN(x) ((x) & 0xFF)
92 #define XHCI_SET_HCIVERSION(x) (((x) & 0xFFFF) << 16)
93 #define XHCI_GET_HCIVERSION(x) (((x) >> 16) & 0xFFFF)
94
95 /* hcsparams1 register */
96 #define XHCI_SET_HCSP1_MAXSLOTS(x) ((x) & 0xFF)
97 #define XHCI_SET_HCSP1_MAXINTR(x) (((x) & 0x7FF) << 8)
98 #define XHCI_SET_HCSP1_MAXPORTS(x) (((x) & 0xFF) << 24)
99
100 /* hcsparams2 register */
101 #define XHCI_SET_HCSP2_IST(x) ((x) & 0x0F)
102 #define XHCI_SET_HCSP2_ERSTMAX(x) (((x) & 0x0F) << 4)
103 #define XHCI_SET_HCSP2_MAXSCRATCH_HI(x) (((x) & 0x1F) << 21)
104 #define XHCI_SET_HCSP2_MAXSCRATCH_LO(x) (((x) & 0x1F) << 27)
105
106 /* hcsparams3 register */
107 #define XHCI_SET_HCSP3_U1EXITLATENCY(x) ((x) & 0xFF)
108 #define XHCI_SET_HCSP3_U2EXITLATENCY(x) (((x) & 0xFFFF) << 16)
109
110 /* hccparams1 register */
111 #define XHCI_SET_HCCP1_AC64(x) ((x) & 0x01)
112 #define XHCI_SET_HCCP1_BNC(x) (((x) & 0x01) << 1)
113 #define XHCI_SET_HCCP1_CSZ(x) (((x) & 0x01) << 2)
114 #define XHCI_SET_HCCP1_PPC(x) (((x) & 0x01) << 3)
115 #define XHCI_SET_HCCP1_PIND(x) (((x) & 0x01) << 4)
116 #define XHCI_SET_HCCP1_LHRC(x) (((x) & 0x01) << 5)
117 #define XHCI_SET_HCCP1_LTC(x) (((x) & 0x01) << 6)
118 #define XHCI_SET_HCCP1_NSS(x) (((x) & 0x01) << 7)
119 #define XHCI_SET_HCCP1_PAE(x) (((x) & 0x01) << 8)
120 #define XHCI_SET_HCCP1_SPC(x) (((x) & 0x01) << 9)
121 #define XHCI_SET_HCCP1_SEC(x) (((x) & 0x01) << 10)
122 #define XHCI_SET_HCCP1_CFC(x) (((x) & 0x01) << 11)
123 #define XHCI_SET_HCCP1_MAXPSA(x) (((x) & 0x0F) << 12)
124 #define XHCI_SET_HCCP1_XECP(x) (((x) & 0xFFFF) << 16)
125
126 /* hccparams2 register */
127 #define XHCI_SET_HCCP2_U3C(x) ((x) & 0x01)
128 #define XHCI_SET_HCCP2_CMC(x) (((x) & 0x01) << 1)
129 #define XHCI_SET_HCCP2_FSC(x) (((x) & 0x01) << 2)
130 #define XHCI_SET_HCCP2_CTC(x) (((x) & 0x01) << 3)
131 #define XHCI_SET_HCCP2_LEC(x) (((x) & 0x01) << 4)
132 #define XHCI_SET_HCCP2_CIC(x) (((x) & 0x01) << 5)
133
134 /* other registers */
135 #define XHCI_SET_DOORBELL(x) ((x) & ~0x03)
136 #define XHCI_SET_RTSOFFSET(x) ((x) & ~0x0F)
137
138 /* register masks */
139 #define XHCI_PS_PLS_MASK (0xF << 5) /* port link state */
140 #define XHCI_PS_SPEED_MASK (0xF << 10) /* port speed */
141 #define XHCI_PS_PIC_MASK (0x3 << 14) /* port indicator */
142
143 /* port register set */
144 #define XHCI_PORTREGS_BASE 0x400 /* base offset */
145 #define XHCI_PORTREGS_PORT0 0x3F0
146 #define XHCI_PORTREGS_SETSZ 0x10 /* size of a set */
147
148 #define MASK_64_HI(x) ((x) & ~0xFFFFFFFFULL)
149 #define MASK_64_LO(x) ((x) & 0xFFFFFFFFULL)
150
151 #define FIELD_REPLACE(a,b,m,s) (((a) & ~((m) << (s))) | \
152 (((b) & (m)) << (s)))
153 #define FIELD_COPY(a,b,m,s) (((a) & ~((m) << (s))) | \
154 (((b) & ((m) << (s)))))
155
156 struct pci_xhci_trb_ring {
157 uint64_t ringaddr; /* current dequeue guest address */
158 uint32_t ccs; /* consumer cycle state */
159 };
160
161 /* device endpoint transfer/stream rings */
162 struct pci_xhci_dev_ep {
163 union {
164 struct xhci_trb *_epu_tr;
165 struct xhci_stream_ctx *_epu_sctx;
166 } _ep_trbsctx;
167 #define ep_tr _ep_trbsctx._epu_tr
168 #define ep_sctx _ep_trbsctx._epu_sctx
169
170 /*
171 * Caches the value of MaxPStreams from the endpoint context
172 * when an endpoint is initialized and is used to validate the
173 * use of ep_ringaddr vs ep_sctx_trbs[] as well as the length
174 * of ep_sctx_trbs[].
175 */
176 uint32_t ep_MaxPStreams;
177 union {
178 struct pci_xhci_trb_ring _epu_trb;
179 struct pci_xhci_trb_ring *_epu_sctx_trbs;
180 } _ep_trb_rings;
181 #define ep_ringaddr _ep_trb_rings._epu_trb.ringaddr
182 #define ep_ccs _ep_trb_rings._epu_trb.ccs
183 #define ep_sctx_trbs _ep_trb_rings._epu_sctx_trbs
184
185 struct usb_data_xfer *ep_xfer; /* transfer chain */
186 };
187
188 /* device context base address array: maps slot->device context */
189 struct xhci_dcbaa {
190 uint64_t dcba[USB_MAX_DEVICES+1]; /* xhci_dev_ctx ptrs */
191 };
192
193 /* port status registers */
194 struct pci_xhci_portregs {
195 uint32_t portsc; /* port status and control */
196 uint32_t portpmsc; /* port pwr mgmt status & control */
197 uint32_t portli; /* port link info */
198 uint32_t porthlpmc; /* port hardware LPM control */
199 } __packed;
200 #define XHCI_PS_SPEED_SET(x) (((x) & 0xF) << 10)
201
202 /* xHC operational registers */
203 struct pci_xhci_opregs {
204 uint32_t usbcmd; /* usb command */
205 uint32_t usbsts; /* usb status */
206 uint32_t pgsz; /* page size */
207 uint32_t dnctrl; /* device notification control */
208 uint64_t crcr; /* command ring control */
209 uint64_t dcbaap; /* device ctx base addr array ptr */
210 uint32_t config; /* configure */
211
212 /* guest mapped addresses: */
213 struct xhci_trb *cr_p; /* crcr dequeue */
214 struct xhci_dcbaa *dcbaa_p; /* dev ctx array ptr */
215 };
216
217 /* xHC runtime registers */
218 struct pci_xhci_rtsregs {
219 uint32_t mfindex; /* microframe index */
220 struct { /* interrupter register set */
221 uint32_t iman; /* interrupter management */
222 uint32_t imod; /* interrupter moderation */
223 uint32_t erstsz; /* event ring segment table size */
224 uint32_t rsvd;
225 uint64_t erstba; /* event ring seg-tbl base addr */
226 uint64_t erdp; /* event ring dequeue ptr */
227 } intrreg __packed;
228
229 /* guest mapped addresses */
230 struct xhci_event_ring_seg *erstba_p;
231 struct xhci_trb *erst_p; /* event ring segment tbl */
232 int er_deq_seg; /* event ring dequeue segment */
233 int er_enq_idx; /* event ring enqueue index - xHCI */
234 int er_enq_seg; /* event ring enqueue segment */
235 uint32_t er_events_cnt; /* number of events in ER */
236 uint32_t event_pcs; /* producer cycle state flag */
237 };
238
239
240 struct pci_xhci_softc;
241
242
243 /*
244 * USB device emulation container.
245 * This is referenced from usb_hci->hci_sc; 1 pci_xhci_dev_emu for each
246 * emulated device instance.
247 */
248 struct pci_xhci_dev_emu {
249 struct pci_xhci_softc *xsc;
250
251 /* XHCI contexts */
252 struct xhci_dev_ctx *dev_ctx;
253 struct pci_xhci_dev_ep eps[XHCI_MAX_ENDPOINTS];
254 int dev_slotstate;
255
256 struct usb_devemu *dev_ue; /* USB emulated dev */
257 void *dev_sc; /* device's softc */
258
259 struct usb_hci hci;
260 };
261
262 struct pci_xhci_softc {
263 struct pci_devinst *xsc_pi;
264
265 pthread_mutex_t mtx;
266
267 uint32_t caplength; /* caplen & hciversion */
268 uint32_t hcsparams1; /* structural parameters 1 */
269 uint32_t hcsparams2; /* structural parameters 2 */
270 uint32_t hcsparams3; /* structural parameters 3 */
271 uint32_t hccparams1; /* capability parameters 1 */
272 uint32_t dboff; /* doorbell offset */
273 uint32_t rtsoff; /* runtime register space offset */
274 uint32_t hccparams2; /* capability parameters 2 */
275
276 uint32_t regsend; /* end of configuration registers */
277
278 struct pci_xhci_opregs opregs;
279 struct pci_xhci_rtsregs rtsregs;
280
281 struct pci_xhci_portregs *portregs;
282 struct pci_xhci_dev_emu **devices; /* XHCI[port] = device */
283 struct pci_xhci_dev_emu **slots; /* slots assigned from 1 */
284
285 int usb2_port_start;
286 int usb3_port_start;
287 };
288
289
290 /* portregs and devices arrays are set up to start from idx=1 */
291 #define XHCI_PORTREG_PTR(x,n) &(x)->portregs[(n)]
292 #define XHCI_DEVINST_PTR(x,n) (x)->devices[(n)]
293 #define XHCI_SLOTDEV_PTR(x,n) (x)->slots[(n)]
294
295 #define XHCI_HALTED(sc) ((sc)->opregs.usbsts & XHCI_STS_HCH)
296
297 #define XHCI_GADDR(sc,a) paddr_guest2host((sc)->xsc_pi->pi_vmctx, \
298 (a), \
299 XHCI_PADDR_SZ - ((a) & (XHCI_PADDR_SZ-1)))
300
301 static int xhci_in_use;
302
303 /* map USB errors to XHCI */
304 static const int xhci_usb_errors[USB_ERR_MAX] = {
305 [USB_ERR_NORMAL_COMPLETION] = XHCI_TRB_ERROR_SUCCESS,
306 [USB_ERR_PENDING_REQUESTS] = XHCI_TRB_ERROR_RESOURCE,
307 [USB_ERR_NOT_STARTED] = XHCI_TRB_ERROR_ENDP_NOT_ON,
308 [USB_ERR_INVAL] = XHCI_TRB_ERROR_INVALID,
309 [USB_ERR_NOMEM] = XHCI_TRB_ERROR_RESOURCE,
310 [USB_ERR_CANCELLED] = XHCI_TRB_ERROR_STOPPED,
311 [USB_ERR_BAD_ADDRESS] = XHCI_TRB_ERROR_PARAMETER,
312 [USB_ERR_BAD_BUFSIZE] = XHCI_TRB_ERROR_PARAMETER,
313 [USB_ERR_BAD_FLAG] = XHCI_TRB_ERROR_PARAMETER,
314 [USB_ERR_NO_CALLBACK] = XHCI_TRB_ERROR_STALL,
315 [USB_ERR_IN_USE] = XHCI_TRB_ERROR_RESOURCE,
316 [USB_ERR_NO_ADDR] = XHCI_TRB_ERROR_RESOURCE,
317 [USB_ERR_NO_PIPE] = XHCI_TRB_ERROR_RESOURCE,
318 [USB_ERR_ZERO_NFRAMES] = XHCI_TRB_ERROR_UNDEFINED,
319 [USB_ERR_ZERO_MAXP] = XHCI_TRB_ERROR_UNDEFINED,
320 [USB_ERR_SET_ADDR_FAILED] = XHCI_TRB_ERROR_RESOURCE,
321 [USB_ERR_NO_POWER] = XHCI_TRB_ERROR_ENDP_NOT_ON,
322 [USB_ERR_TOO_DEEP] = XHCI_TRB_ERROR_RESOURCE,
323 [USB_ERR_IOERROR] = XHCI_TRB_ERROR_TRB,
324 [USB_ERR_NOT_CONFIGURED] = XHCI_TRB_ERROR_ENDP_NOT_ON,
325 [USB_ERR_TIMEOUT] = XHCI_TRB_ERROR_CMD_ABORTED,
326 [USB_ERR_SHORT_XFER] = XHCI_TRB_ERROR_SHORT_PKT,
327 [USB_ERR_STALLED] = XHCI_TRB_ERROR_STALL,
328 [USB_ERR_INTERRUPTED] = XHCI_TRB_ERROR_CMD_ABORTED,
329 [USB_ERR_DMA_LOAD_FAILED] = XHCI_TRB_ERROR_DATA_BUF,
330 [USB_ERR_BAD_CONTEXT] = XHCI_TRB_ERROR_TRB,
331 [USB_ERR_NO_ROOT_HUB] = XHCI_TRB_ERROR_UNDEFINED,
332 [USB_ERR_NO_INTR_THREAD] = XHCI_TRB_ERROR_UNDEFINED,
333 [USB_ERR_NOT_LOCKED] = XHCI_TRB_ERROR_UNDEFINED,
334 };
335 #define USB_TO_XHCI_ERR(e) ((e) < USB_ERR_MAX ? xhci_usb_errors[(e)] : \
336 XHCI_TRB_ERROR_INVALID)
337
338 static int pci_xhci_insert_event(struct pci_xhci_softc *sc,
339 struct xhci_trb *evtrb, int do_intr);
340 static void pci_xhci_dump_trb(struct xhci_trb *trb);
341 static void pci_xhci_assert_interrupt(struct pci_xhci_softc *sc);
342 static void pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot);
343 static void pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm);
344 static void pci_xhci_update_ep_ring(struct pci_xhci_softc *sc,
345 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
346 struct xhci_endp_ctx *ep_ctx, uint32_t streamid,
347 uint64_t ringaddr, int ccs);
348
349 static void
350 pci_xhci_set_evtrb(struct xhci_trb *evtrb, uint64_t port, uint32_t errcode,
351 uint32_t evtype)
352 {
353 evtrb->qwTrb0 = port << 24;
354 evtrb->dwTrb2 = XHCI_TRB_2_ERROR_SET(errcode);
355 evtrb->dwTrb3 = XHCI_TRB_3_TYPE_SET(evtype);
356 }
357
358
359 /* controller reset */
360 static void
361 pci_xhci_reset(struct pci_xhci_softc *sc)
362 {
363 int i;
364
365 sc->rtsregs.er_enq_idx = 0;
366 sc->rtsregs.er_events_cnt = 0;
367 sc->rtsregs.event_pcs = 1;
368
369 for (i = 1; i <= XHCI_MAX_SLOTS; i++) {
370 pci_xhci_reset_slot(sc, i);
371 }
372 }
373
374 static uint32_t
375 pci_xhci_usbcmd_write(struct pci_xhci_softc *sc, uint32_t cmd)
376 {
377 int do_intr = 0;
378 int i;
379
380 if (cmd & XHCI_CMD_RS) {
381 do_intr = (sc->opregs.usbcmd & XHCI_CMD_RS) == 0;
382
383 sc->opregs.usbcmd |= XHCI_CMD_RS;
384 sc->opregs.usbsts &= ~XHCI_STS_HCH;
385 sc->opregs.usbsts |= XHCI_STS_PCD;
386
387 /* Queue port change event on controller run from stop */
388 if (do_intr)
389 for (i = 1; i <= XHCI_MAX_DEVS; i++) {
390 struct pci_xhci_dev_emu *dev;
391 struct pci_xhci_portregs *port;
392 struct xhci_trb evtrb;
393
394 if ((dev = XHCI_DEVINST_PTR(sc, i)) == NULL)
395 continue;
396
397 port = XHCI_PORTREG_PTR(sc, i);
398 port->portsc |= XHCI_PS_CSC | XHCI_PS_CCS;
399 port->portsc &= ~XHCI_PS_PLS_MASK;
400
401 /*
402 * XHCI 4.19.3 USB2 RxDetect->Polling,
403 * USB3 Polling->U0
404 */
405 if (dev->dev_ue->ue_usbver == 2)
406 port->portsc |=
407 XHCI_PS_PLS_SET(UPS_PORT_LS_POLL);
408 else
409 port->portsc |=
410 XHCI_PS_PLS_SET(UPS_PORT_LS_U0);
411
412 pci_xhci_set_evtrb(&evtrb, i,
413 XHCI_TRB_ERROR_SUCCESS,
414 XHCI_TRB_EVENT_PORT_STS_CHANGE);
415
416 if (pci_xhci_insert_event(sc, &evtrb, 0) !=
417 XHCI_TRB_ERROR_SUCCESS)
418 break;
419 }
420 } else {
421 sc->opregs.usbcmd &= ~XHCI_CMD_RS;
422 sc->opregs.usbsts |= XHCI_STS_HCH;
423 sc->opregs.usbsts &= ~XHCI_STS_PCD;
424 }
425
426 /* start execution of schedule; stop when set to 0 */
427 cmd |= sc->opregs.usbcmd & XHCI_CMD_RS;
428
429 if (cmd & XHCI_CMD_HCRST) {
430 /* reset controller */
431 pci_xhci_reset(sc);
432 cmd &= ~XHCI_CMD_HCRST;
433 }
434
435 cmd &= ~(XHCI_CMD_CSS | XHCI_CMD_CRS);
436
437 if (do_intr)
438 pci_xhci_assert_interrupt(sc);
439
440 return (cmd);
441 }
442
443 static void
444 pci_xhci_portregs_write(struct pci_xhci_softc *sc, uint64_t offset,
445 uint64_t value)
446 {
447 struct xhci_trb evtrb;
448 struct pci_xhci_portregs *p;
449 int port;
450 uint32_t oldpls, newpls;
451
452 if (sc->portregs == NULL)
453 return;
454
455 port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ;
456 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ;
457
458 DPRINTF(("pci_xhci: portregs wr offset 0x%lx, port %u: 0x%lx",
459 offset, port, value));
460
461 assert(port >= 0);
462
463 if (port > XHCI_MAX_DEVS) {
464 DPRINTF(("pci_xhci: portregs_write port %d > ndevices",
465 port));
466 return;
467 }
468
469 if (XHCI_DEVINST_PTR(sc, port) == NULL) {
470 DPRINTF(("pci_xhci: portregs_write to unattached port %d",
471 port));
472 }
473
474 p = XHCI_PORTREG_PTR(sc, port);
475 switch (offset) {
476 case 0:
477 /* port reset or warm reset */
478 if (value & (XHCI_PS_PR | XHCI_PS_WPR)) {
479 pci_xhci_reset_port(sc, port, value & XHCI_PS_WPR);
480 break;
481 }
482
483 if ((p->portsc & XHCI_PS_PP) == 0) {
484 WPRINTF(("pci_xhci: portregs_write to unpowered "
485 "port %d", port));
486 break;
487 }
488
489 /* Port status and control register */
490 oldpls = XHCI_PS_PLS_GET(p->portsc);
491 newpls = XHCI_PS_PLS_GET(value);
492
493 #ifndef __FreeBSD__
494 p->portsc &= XHCI_PS_PED | XHCI_PS_PP | XHCI_PS_PLS_MASK |
495 XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK;
496 #else
497 p->portsc &= XHCI_PS_PED | XHCI_PS_PLS_MASK |
498 XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK;
499 #endif
500
501 if (XHCI_DEVINST_PTR(sc, port))
502 p->portsc |= XHCI_PS_CCS;
503
504 p->portsc |= (value &
505 ~(XHCI_PS_OCA |
506 XHCI_PS_PR |
507 XHCI_PS_PED |
508 XHCI_PS_PLS_MASK | /* link state */
509 XHCI_PS_SPEED_MASK |
510 XHCI_PS_PIC_MASK | /* port indicator */
511 XHCI_PS_LWS | XHCI_PS_DR | XHCI_PS_WPR));
512
513 /* clear control bits */
514 p->portsc &= ~(value &
515 (XHCI_PS_CSC |
516 XHCI_PS_PEC |
517 XHCI_PS_WRC |
518 XHCI_PS_OCC |
519 XHCI_PS_PRC |
520 XHCI_PS_PLC |
521 XHCI_PS_CEC |
522 XHCI_PS_CAS));
523
524 /* port disable request; for USB3, don't care */
525 if (value & XHCI_PS_PED)
526 DPRINTF(("Disable port %d request", port));
527
528 if (!(value & XHCI_PS_LWS))
529 break;
530
531 DPRINTF(("Port new PLS: %d", newpls));
532 switch (newpls) {
533 case 0: /* U0 */
534 case 3: /* U3 */
535 if (oldpls != newpls) {
536 p->portsc &= ~XHCI_PS_PLS_MASK;
537 p->portsc |= XHCI_PS_PLS_SET(newpls) |
538 XHCI_PS_PLC;
539
540 if (oldpls != 0 && newpls == 0) {
541 pci_xhci_set_evtrb(&evtrb, port,
542 XHCI_TRB_ERROR_SUCCESS,
543 XHCI_TRB_EVENT_PORT_STS_CHANGE);
544
545 pci_xhci_insert_event(sc, &evtrb, 1);
546 }
547 }
548 break;
549
550 default:
551 DPRINTF(("Unhandled change port %d PLS %u",
552 port, newpls));
553 break;
554 }
555 break;
556 case 4:
557 /* Port power management status and control register */
558 p->portpmsc = value;
559 break;
560 case 8:
561 /* Port link information register */
562 DPRINTF(("pci_xhci attempted write to PORTLI, port %d",
563 port));
564 break;
565 case 12:
566 /*
567 * Port hardware LPM control register.
568 * For USB3, this register is reserved.
569 */
570 p->porthlpmc = value;
571 break;
572 default:
573 DPRINTF(("pci_xhci: unaligned portreg write offset %#lx",
574 offset));
575 break;
576 }
577 }
578
579 static struct xhci_dev_ctx *
580 pci_xhci_get_dev_ctx(struct pci_xhci_softc *sc, uint32_t slot)
581 {
582 uint64_t devctx_addr;
583 struct xhci_dev_ctx *devctx;
584
585 assert(slot > 0 && slot <= XHCI_MAX_DEVS);
586 assert(XHCI_SLOTDEV_PTR(sc, slot) != NULL);
587 assert(sc->opregs.dcbaa_p != NULL);
588
589 devctx_addr = sc->opregs.dcbaa_p->dcba[slot];
590
591 if (devctx_addr == 0) {
592 DPRINTF(("get_dev_ctx devctx_addr == 0"));
593 return (NULL);
594 }
595
596 DPRINTF(("pci_xhci: get dev ctx, slot %u devctx addr %016lx",
597 slot, devctx_addr));
598 devctx = XHCI_GADDR(sc, devctx_addr & ~0x3FUL);
599
600 return (devctx);
601 }
602
603 static struct xhci_trb *
604 pci_xhci_trb_next(struct pci_xhci_softc *sc, struct xhci_trb *curtrb,
605 uint64_t *guestaddr)
606 {
607 struct xhci_trb *next;
608
609 assert(curtrb != NULL);
610
611 if (XHCI_TRB_3_TYPE_GET(curtrb->dwTrb3) == XHCI_TRB_TYPE_LINK) {
612 if (guestaddr)
613 *guestaddr = curtrb->qwTrb0 & ~0xFUL;
614
615 next = XHCI_GADDR(sc, curtrb->qwTrb0 & ~0xFUL);
616 } else {
617 if (guestaddr)
618 *guestaddr += sizeof(struct xhci_trb) & ~0xFUL;
619
620 next = curtrb + 1;
621 }
622
623 return (next);
624 }
625
626 static void
627 pci_xhci_assert_interrupt(struct pci_xhci_softc *sc)
628 {
629
630 sc->rtsregs.intrreg.erdp |= XHCI_ERDP_LO_BUSY;
631 sc->rtsregs.intrreg.iman |= XHCI_IMAN_INTR_PEND;
632 sc->opregs.usbsts |= XHCI_STS_EINT;
633
634 /* only trigger interrupt if permitted */
635 if ((sc->opregs.usbcmd & XHCI_CMD_INTE) &&
636 (sc->rtsregs.intrreg.iman & XHCI_IMAN_INTR_ENA)) {
637 if (pci_msi_enabled(sc->xsc_pi))
638 pci_generate_msi(sc->xsc_pi, 0);
639 else
640 pci_lintr_assert(sc->xsc_pi);
641 }
642 }
643
644 static void
645 pci_xhci_deassert_interrupt(struct pci_xhci_softc *sc)
646 {
647
648 if (!pci_msi_enabled(sc->xsc_pi))
649 pci_lintr_assert(sc->xsc_pi);
650 }
651
652 static void
653 pci_xhci_init_ep(struct pci_xhci_dev_emu *dev, int epid)
654 {
655 struct xhci_dev_ctx *dev_ctx;
656 struct pci_xhci_dev_ep *devep;
657 struct xhci_endp_ctx *ep_ctx;
658 uint32_t i, pstreams;
659
660 dev_ctx = dev->dev_ctx;
661 ep_ctx = &dev_ctx->ctx_ep[epid];
662 devep = &dev->eps[epid];
663 pstreams = XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0);
664 if (pstreams > 0) {
665 DPRINTF(("init_ep %d with pstreams %d", epid, pstreams));
666 assert(devep->ep_sctx_trbs == NULL);
667
668 devep->ep_sctx = XHCI_GADDR(dev->xsc, ep_ctx->qwEpCtx2 &
669 XHCI_EPCTX_2_TR_DQ_PTR_MASK);
670 devep->ep_sctx_trbs = calloc(pstreams,
671 sizeof(struct pci_xhci_trb_ring));
672 for (i = 0; i < pstreams; i++) {
673 devep->ep_sctx_trbs[i].ringaddr =
674 devep->ep_sctx[i].qwSctx0 &
675 XHCI_SCTX_0_TR_DQ_PTR_MASK;
676 devep->ep_sctx_trbs[i].ccs =
677 XHCI_SCTX_0_DCS_GET(devep->ep_sctx[i].qwSctx0);
678 }
679 } else {
680 DPRINTF(("init_ep %d with no pstreams", epid));
681 devep->ep_ringaddr = ep_ctx->qwEpCtx2 &
682 XHCI_EPCTX_2_TR_DQ_PTR_MASK;
683 devep->ep_ccs = XHCI_EPCTX_2_DCS_GET(ep_ctx->qwEpCtx2);
684 devep->ep_tr = XHCI_GADDR(dev->xsc, devep->ep_ringaddr);
685 DPRINTF(("init_ep tr DCS %x", devep->ep_ccs));
686 }
687 devep->ep_MaxPStreams = pstreams;
688
689 if (devep->ep_xfer == NULL) {
690 devep->ep_xfer = malloc(sizeof(struct usb_data_xfer));
691 USB_DATA_XFER_INIT(devep->ep_xfer);
692 }
693 }
694
695 static void
696 pci_xhci_disable_ep(struct pci_xhci_dev_emu *dev, int epid)
697 {
698 struct xhci_dev_ctx *dev_ctx;
699 struct pci_xhci_dev_ep *devep;
700 struct xhci_endp_ctx *ep_ctx;
701
702 DPRINTF(("pci_xhci disable_ep %d", epid));
703
704 dev_ctx = dev->dev_ctx;
705 ep_ctx = &dev_ctx->ctx_ep[epid];
706 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_DISABLED;
707
708 devep = &dev->eps[epid];
709 if (devep->ep_MaxPStreams > 0)
710 free(devep->ep_sctx_trbs);
711
712 if (devep->ep_xfer != NULL) {
713 free(devep->ep_xfer);
714 devep->ep_xfer = NULL;
715 }
716
717 memset(devep, 0, sizeof(struct pci_xhci_dev_ep));
718 }
719
720
721 /* reset device at slot and data structures related to it */
722 static void
723 pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot)
724 {
725 struct pci_xhci_dev_emu *dev;
726
727 dev = XHCI_SLOTDEV_PTR(sc, slot);
728
729 if (!dev) {
730 DPRINTF(("xhci reset unassigned slot (%d)?", slot));
731 } else {
732 dev->dev_slotstate = XHCI_ST_DISABLED;
733 }
734
735 /* TODO: reset ring buffer pointers */
736 }
737
738 static int
739 pci_xhci_insert_event(struct pci_xhci_softc *sc, struct xhci_trb *evtrb,
740 int do_intr)
741 {
742 struct pci_xhci_rtsregs *rts;
743 uint64_t erdp;
744 int erdp_idx;
745 int err;
746 struct xhci_trb *evtrbptr;
747
748 err = XHCI_TRB_ERROR_SUCCESS;
749
750 rts = &sc->rtsregs;
751
752 erdp = rts->intrreg.erdp & ~0xF;
753 erdp_idx = (erdp - rts->erstba_p[rts->er_deq_seg].qwEvrsTablePtr) /
754 sizeof(struct xhci_trb);
755
756 DPRINTF(("pci_xhci: insert event 0[%lx] 2[%x] 3[%x]",
757 evtrb->qwTrb0, evtrb->dwTrb2, evtrb->dwTrb3));
758 DPRINTF(("\terdp idx %d/seg %d, enq idx %d/seg %d, pcs %u",
759 erdp_idx, rts->er_deq_seg, rts->er_enq_idx,
760 rts->er_enq_seg, rts->event_pcs));
761 DPRINTF(("\t(erdp=0x%lx, erst=0x%lx, tblsz=%u, do_intr %d)",
762 erdp, rts->erstba_p->qwEvrsTablePtr,
763 rts->erstba_p->dwEvrsTableSize, do_intr));
764
765 evtrbptr = &rts->erst_p[rts->er_enq_idx];
766
767 /* TODO: multi-segment table */
768 if (rts->er_events_cnt >= rts->erstba_p->dwEvrsTableSize) {
769 DPRINTF(("pci_xhci[%d] cannot insert event; ring full",
770 __LINE__));
771 err = XHCI_TRB_ERROR_EV_RING_FULL;
772 goto done;
773 }
774
775 if (rts->er_events_cnt == rts->erstba_p->dwEvrsTableSize - 1) {
776 struct xhci_trb errev;
777
778 if ((evtrbptr->dwTrb3 & 0x1) == (rts->event_pcs & 0x1)) {
779
780 DPRINTF(("pci_xhci[%d] insert evt err: ring full",
781 __LINE__));
782
783 errev.qwTrb0 = 0;
784 errev.dwTrb2 = XHCI_TRB_2_ERROR_SET(
785 XHCI_TRB_ERROR_EV_RING_FULL);
786 errev.dwTrb3 = XHCI_TRB_3_TYPE_SET(
787 XHCI_TRB_EVENT_HOST_CTRL) |
788 rts->event_pcs;
789 rts->er_events_cnt++;
790 memcpy(&rts->erst_p[rts->er_enq_idx], &errev,
791 sizeof(struct xhci_trb));
792 rts->er_enq_idx = (rts->er_enq_idx + 1) %
793 rts->erstba_p->dwEvrsTableSize;
794 err = XHCI_TRB_ERROR_EV_RING_FULL;
795 do_intr = 1;
796
797 goto done;
798 }
799 } else {
800 rts->er_events_cnt++;
801 }
802
803 evtrb->dwTrb3 &= ~XHCI_TRB_3_CYCLE_BIT;
804 evtrb->dwTrb3 |= rts->event_pcs;
805
806 memcpy(&rts->erst_p[rts->er_enq_idx], evtrb, sizeof(struct xhci_trb));
807 rts->er_enq_idx = (rts->er_enq_idx + 1) %
808 rts->erstba_p->dwEvrsTableSize;
809
810 if (rts->er_enq_idx == 0)
811 rts->event_pcs ^= 1;
812
813 done:
814 if (do_intr)
815 pci_xhci_assert_interrupt(sc);
816
817 return (err);
818 }
819
820 static uint32_t
821 pci_xhci_cmd_enable_slot(struct pci_xhci_softc *sc, uint32_t *slot)
822 {
823 struct pci_xhci_dev_emu *dev;
824 uint32_t cmderr;
825 int i;
826
827 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
828 if (sc->portregs != NULL)
829 for (i = 1; i <= XHCI_MAX_SLOTS; i++) {
830 dev = XHCI_SLOTDEV_PTR(sc, i);
831 if (dev && dev->dev_slotstate == XHCI_ST_DISABLED) {
832 *slot = i;
833 dev->dev_slotstate = XHCI_ST_ENABLED;
834 cmderr = XHCI_TRB_ERROR_SUCCESS;
835 dev->hci.hci_address = i;
836 break;
837 }
838 }
839
840 DPRINTF(("pci_xhci enable slot (error=%d) slot %u",
841 cmderr != XHCI_TRB_ERROR_SUCCESS, *slot));
842
843 return (cmderr);
844 }
845
846 static uint32_t
847 pci_xhci_cmd_disable_slot(struct pci_xhci_softc *sc, uint32_t slot)
848 {
849 struct pci_xhci_dev_emu *dev;
850 uint32_t cmderr;
851
852 DPRINTF(("pci_xhci disable slot %u", slot));
853
854 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
855 if (sc->portregs == NULL)
856 goto done;
857
858 if (slot > XHCI_MAX_SLOTS) {
859 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
860 goto done;
861 }
862
863 dev = XHCI_SLOTDEV_PTR(sc, slot);
864 if (dev) {
865 if (dev->dev_slotstate == XHCI_ST_DISABLED) {
866 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
867 } else {
868 dev->dev_slotstate = XHCI_ST_DISABLED;
869 cmderr = XHCI_TRB_ERROR_SUCCESS;
870 /* TODO: reset events and endpoints */
871 }
872 } else
873 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
874
875 done:
876 return (cmderr);
877 }
878
879 static uint32_t
880 pci_xhci_cmd_reset_device(struct pci_xhci_softc *sc, uint32_t slot)
881 {
882 struct pci_xhci_dev_emu *dev;
883 struct xhci_dev_ctx *dev_ctx;
884 struct xhci_endp_ctx *ep_ctx;
885 uint32_t cmderr;
886 int i;
887
888 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
889 if (sc->portregs == NULL)
890 goto done;
891
892 DPRINTF(("pci_xhci reset device slot %u", slot));
893
894 dev = XHCI_SLOTDEV_PTR(sc, slot);
895 if (!dev || dev->dev_slotstate == XHCI_ST_DISABLED)
896 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
897 else {
898 dev->dev_slotstate = XHCI_ST_DEFAULT;
899
900 dev->hci.hci_address = 0;
901 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
902
903 /* slot state */
904 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
905 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_DEFAULT,
906 0x1F, 27);
907
908 /* number of contexts */
909 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE(
910 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27);
911
912 /* reset all eps other than ep-0 */
913 for (i = 2; i <= 31; i++) {
914 ep_ctx = &dev_ctx->ctx_ep[i];
915 ep_ctx->dwEpCtx0 = FIELD_REPLACE( ep_ctx->dwEpCtx0,
916 XHCI_ST_EPCTX_DISABLED, 0x7, 0);
917 }
918
919 cmderr = XHCI_TRB_ERROR_SUCCESS;
920 }
921
922 pci_xhci_reset_slot(sc, slot);
923
924 done:
925 return (cmderr);
926 }
927
928 static uint32_t
929 pci_xhci_cmd_address_device(struct pci_xhci_softc *sc, uint32_t slot,
930 struct xhci_trb *trb)
931 {
932 struct pci_xhci_dev_emu *dev;
933 struct xhci_input_dev_ctx *input_ctx;
934 struct xhci_slot_ctx *islot_ctx;
935 struct xhci_dev_ctx *dev_ctx;
936 struct xhci_endp_ctx *ep0_ctx;
937 uint32_t cmderr;
938
939 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
940 islot_ctx = &input_ctx->ctx_slot;
941 ep0_ctx = &input_ctx->ctx_ep[1];
942
943 cmderr = XHCI_TRB_ERROR_SUCCESS;
944
945 DPRINTF(("pci_xhci: address device, input ctl: D 0x%08x A 0x%08x,",
946 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1));
947 DPRINTF((" slot %08x %08x %08x %08x",
948 islot_ctx->dwSctx0, islot_ctx->dwSctx1,
949 islot_ctx->dwSctx2, islot_ctx->dwSctx3));
950 DPRINTF((" ep0 %08x %08x %016lx %08x",
951 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
952 ep0_ctx->dwEpCtx4));
953
954 /* when setting address: drop-ctx=0, add-ctx=slot+ep0 */
955 if ((input_ctx->ctx_input.dwInCtx0 != 0) ||
956 (input_ctx->ctx_input.dwInCtx1 & 0x03) != 0x03) {
957 DPRINTF(("pci_xhci: address device, input ctl invalid"));
958 cmderr = XHCI_TRB_ERROR_TRB;
959 goto done;
960 }
961
962 /* assign address to slot */
963 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
964
965 DPRINTF(("pci_xhci: address device, dev ctx"));
966 DPRINTF((" slot %08x %08x %08x %08x",
967 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
968 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
969
970 dev = XHCI_SLOTDEV_PTR(sc, slot);
971 assert(dev != NULL);
972
973 dev->hci.hci_address = slot;
974 dev->dev_ctx = dev_ctx;
975
976 if (dev->dev_ue->ue_reset == NULL ||
977 dev->dev_ue->ue_reset(dev->dev_sc) < 0) {
978 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;
979 goto done;
980 }
981
982 memcpy(&dev_ctx->ctx_slot, islot_ctx, sizeof(struct xhci_slot_ctx));
983
984 dev_ctx->ctx_slot.dwSctx3 =
985 XHCI_SCTX_3_SLOT_STATE_SET(XHCI_ST_SLCTX_ADDRESSED) |
986 XHCI_SCTX_3_DEV_ADDR_SET(slot);
987
988 memcpy(&dev_ctx->ctx_ep[1], ep0_ctx, sizeof(struct xhci_endp_ctx));
989 ep0_ctx = &dev_ctx->ctx_ep[1];
990 ep0_ctx->dwEpCtx0 = (ep0_ctx->dwEpCtx0 & ~0x7) |
991 XHCI_EPCTX_0_EPSTATE_SET(XHCI_ST_EPCTX_RUNNING);
992
993 pci_xhci_init_ep(dev, 1);
994
995 dev->dev_slotstate = XHCI_ST_ADDRESSED;
996
997 DPRINTF(("pci_xhci: address device, output ctx"));
998 DPRINTF((" slot %08x %08x %08x %08x",
999 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1000 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1001 DPRINTF((" ep0 %08x %08x %016lx %08x",
1002 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
1003 ep0_ctx->dwEpCtx4));
1004
1005 done:
1006 return (cmderr);
1007 }
1008
1009 static uint32_t
1010 pci_xhci_cmd_config_ep(struct pci_xhci_softc *sc, uint32_t slot,
1011 struct xhci_trb *trb)
1012 {
1013 struct xhci_input_dev_ctx *input_ctx;
1014 struct pci_xhci_dev_emu *dev;
1015 struct xhci_dev_ctx *dev_ctx;
1016 struct xhci_endp_ctx *ep_ctx, *iep_ctx;
1017 uint32_t cmderr;
1018 int i;
1019
1020 cmderr = XHCI_TRB_ERROR_SUCCESS;
1021
1022 DPRINTF(("pci_xhci config_ep slot %u", slot));
1023
1024 dev = XHCI_SLOTDEV_PTR(sc, slot);
1025 assert(dev != NULL);
1026
1027 if ((trb->dwTrb3 & XHCI_TRB_3_DCEP_BIT) != 0) {
1028 DPRINTF(("pci_xhci config_ep - deconfigure ep slot %u",
1029 slot));
1030 if (dev->dev_ue->ue_stop != NULL)
1031 dev->dev_ue->ue_stop(dev->dev_sc);
1032
1033 dev->dev_slotstate = XHCI_ST_ADDRESSED;
1034
1035 dev->hci.hci_address = 0;
1036 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1037
1038 /* number of contexts */
1039 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE(
1040 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27);
1041
1042 /* slot state */
1043 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
1044 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_ADDRESSED,
1045 0x1F, 27);
1046
1047 /* disable endpoints */
1048 for (i = 2; i < 32; i++)
1049 pci_xhci_disable_ep(dev, i);
1050
1051 cmderr = XHCI_TRB_ERROR_SUCCESS;
1052
1053 goto done;
1054 }
1055
1056 if (dev->dev_slotstate < XHCI_ST_ADDRESSED) {
1057 DPRINTF(("pci_xhci: config_ep slotstate x%x != addressed",
1058 dev->dev_slotstate));
1059 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
1060 goto done;
1061 }
1062
1063 /* In addressed/configured state;
1064 * for each drop endpoint ctx flag:
1065 * ep->state = DISABLED
1066 * for each add endpoint ctx flag:
1067 * cp(ep-in, ep-out)
1068 * ep->state = RUNNING
1069 * for each drop+add endpoint flag:
1070 * reset ep resources
1071 * cp(ep-in, ep-out)
1072 * ep->state = RUNNING
1073 * if input->DisabledCtx[2-31] < 30: (at least 1 ep not disabled)
1074 * slot->state = configured
1075 */
1076
1077 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
1078 dev_ctx = dev->dev_ctx;
1079 DPRINTF(("pci_xhci: config_ep inputctx: D:x%08x A:x%08x 7:x%08x",
1080 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1,
1081 input_ctx->ctx_input.dwInCtx7));
1082
1083 for (i = 2; i <= 31; i++) {
1084 ep_ctx = &dev_ctx->ctx_ep[i];
1085
1086 if (input_ctx->ctx_input.dwInCtx0 &
1087 XHCI_INCTX_0_DROP_MASK(i)) {
1088 DPRINTF((" config ep - dropping ep %d", i));
1089 pci_xhci_disable_ep(dev, i);
1090 }
1091
1092 if (input_ctx->ctx_input.dwInCtx1 &
1093 XHCI_INCTX_1_ADD_MASK(i)) {
1094 iep_ctx = &input_ctx->ctx_ep[i];
1095
1096 DPRINTF((" enable ep[%d] %08x %08x %016lx %08x",
1097 i, iep_ctx->dwEpCtx0, iep_ctx->dwEpCtx1,
1098 iep_ctx->qwEpCtx2, iep_ctx->dwEpCtx4));
1099
1100 memcpy(ep_ctx, iep_ctx, sizeof(struct xhci_endp_ctx));
1101
1102 pci_xhci_init_ep(dev, i);
1103
1104 /* ep state */
1105 ep_ctx->dwEpCtx0 = FIELD_REPLACE(
1106 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1107 }
1108 }
1109
1110 /* slot state to configured */
1111 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
1112 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_CONFIGURED, 0x1F, 27);
1113 dev_ctx->ctx_slot.dwSctx0 = FIELD_COPY(
1114 dev_ctx->ctx_slot.dwSctx0, input_ctx->ctx_slot.dwSctx0, 0x1F, 27);
1115 dev->dev_slotstate = XHCI_ST_CONFIGURED;
1116
1117 DPRINTF(("EP configured; slot %u [0]=0x%08x [1]=0x%08x [2]=0x%08x "
1118 "[3]=0x%08x",
1119 slot, dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1120 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1121
1122 done:
1123 return (cmderr);
1124 }
1125
1126 static uint32_t
1127 pci_xhci_cmd_reset_ep(struct pci_xhci_softc *sc, uint32_t slot,
1128 struct xhci_trb *trb)
1129 {
1130 struct pci_xhci_dev_emu *dev;
1131 struct pci_xhci_dev_ep *devep;
1132 struct xhci_dev_ctx *dev_ctx;
1133 struct xhci_endp_ctx *ep_ctx;
1134 uint32_t cmderr, epid;
1135 uint32_t type;
1136
1137 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3);
1138
1139 DPRINTF(("pci_xhci: reset ep %u: slot %u", epid, slot));
1140
1141 cmderr = XHCI_TRB_ERROR_SUCCESS;
1142
1143 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1144
1145 dev = XHCI_SLOTDEV_PTR(sc, slot);
1146 assert(dev != NULL);
1147
1148 if (type == XHCI_TRB_TYPE_STOP_EP &&
1149 (trb->dwTrb3 & XHCI_TRB_3_SUSP_EP_BIT) != 0) {
1150 /* XXX suspend endpoint for 10ms */
1151 }
1152
1153 if (epid < 1 || epid > 31) {
1154 DPRINTF(("pci_xhci: reset ep: invalid epid %u", epid));
1155 cmderr = XHCI_TRB_ERROR_TRB;
1156 goto done;
1157 }
1158
1159 devep = &dev->eps[epid];
1160 if (devep->ep_xfer != NULL)
1161 USB_DATA_XFER_RESET(devep->ep_xfer);
1162
1163 dev_ctx = dev->dev_ctx;
1164 assert(dev_ctx != NULL);
1165
1166 ep_ctx = &dev_ctx->ctx_ep[epid];
1167
1168 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED;
1169
1170 if (devep->ep_MaxPStreams == 0)
1171 ep_ctx->qwEpCtx2 = devep->ep_ringaddr | devep->ep_ccs;
1172
1173 DPRINTF(("pci_xhci: reset ep[%u] %08x %08x %016lx %08x",
1174 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2,
1175 ep_ctx->dwEpCtx4));
1176
1177 if (type == XHCI_TRB_TYPE_RESET_EP &&
1178 (dev->dev_ue->ue_reset == NULL ||
1179 dev->dev_ue->ue_reset(dev->dev_sc) < 0)) {
1180 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;
1181 goto done;
1182 }
1183
1184 done:
1185 return (cmderr);
1186 }
1187
1188
1189 static uint32_t
1190 pci_xhci_find_stream(struct pci_xhci_softc *sc, struct xhci_endp_ctx *ep,
1191 struct pci_xhci_dev_ep *devep, uint32_t streamid)
1192 {
1193 struct xhci_stream_ctx *sctx;
1194
1195 if (devep->ep_MaxPStreams == 0)
1196 return (XHCI_TRB_ERROR_TRB);
1197
1198 if (devep->ep_MaxPStreams > XHCI_STREAMS_MAX)
1199 return (XHCI_TRB_ERROR_INVALID_SID);
1200
1201 if (XHCI_EPCTX_0_LSA_GET(ep->dwEpCtx0) == 0) {
1202 DPRINTF(("pci_xhci: find_stream; LSA bit not set"));
1203 return (XHCI_TRB_ERROR_INVALID_SID);
1204 }
1205
1206 /* only support primary stream */
1207 if (streamid > devep->ep_MaxPStreams)
1208 return (XHCI_TRB_ERROR_STREAM_TYPE);
1209
1210 sctx = (struct xhci_stream_ctx *)XHCI_GADDR(sc, ep->qwEpCtx2 & ~0xFUL) +
1211 streamid;
1212 if (!XHCI_SCTX_0_SCT_GET(sctx->qwSctx0))
1213 return (XHCI_TRB_ERROR_STREAM_TYPE);
1214
1215 return (XHCI_TRB_ERROR_SUCCESS);
1216 }
1217
1218
1219 static uint32_t
1220 pci_xhci_cmd_set_tr(struct pci_xhci_softc *sc, uint32_t slot,
1221 struct xhci_trb *trb)
1222 {
1223 struct pci_xhci_dev_emu *dev;
1224 struct pci_xhci_dev_ep *devep;
1225 struct xhci_dev_ctx *dev_ctx;
1226 struct xhci_endp_ctx *ep_ctx;
1227 uint32_t cmderr, epid;
1228 uint32_t streamid;
1229
1230 cmderr = XHCI_TRB_ERROR_SUCCESS;
1231
1232 dev = XHCI_SLOTDEV_PTR(sc, slot);
1233 assert(dev != NULL);
1234
1235 DPRINTF(("pci_xhci set_tr: new-tr x%016lx, SCT %u DCS %u",
1236 (trb->qwTrb0 & ~0xF), (uint32_t)((trb->qwTrb0 >> 1) & 0x7),
1237 (uint32_t)(trb->qwTrb0 & 0x1)));
1238 DPRINTF((" stream-id %u, slot %u, epid %u, C %u",
1239 (trb->dwTrb2 >> 16) & 0xFFFF,
1240 XHCI_TRB_3_SLOT_GET(trb->dwTrb3),
1241 XHCI_TRB_3_EP_GET(trb->dwTrb3), trb->dwTrb3 & 0x1));
1242
1243 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3);
1244 if (epid < 1 || epid > 31) {
1245 DPRINTF(("pci_xhci: set_tr_deq: invalid epid %u", epid));
1246 cmderr = XHCI_TRB_ERROR_TRB;
1247 goto done;
1248 }
1249
1250 dev_ctx = dev->dev_ctx;
1251 assert(dev_ctx != NULL);
1252
1253 ep_ctx = &dev_ctx->ctx_ep[epid];
1254 devep = &dev->eps[epid];
1255
1256 switch (XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)) {
1257 case XHCI_ST_EPCTX_STOPPED:
1258 case XHCI_ST_EPCTX_ERROR:
1259 break;
1260 default:
1261 DPRINTF(("pci_xhci cmd set_tr invalid state %x",
1262 XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)));
1263 cmderr = XHCI_TRB_ERROR_CONTEXT_STATE;
1264 goto done;
1265 }
1266
1267 streamid = XHCI_TRB_2_STREAM_GET(trb->dwTrb2);
1268 if (devep->ep_MaxPStreams > 0) {
1269 cmderr = pci_xhci_find_stream(sc, ep_ctx, devep, streamid);
1270 if (cmderr == XHCI_TRB_ERROR_SUCCESS) {
1271 assert(devep->ep_sctx != NULL);
1272
1273 devep->ep_sctx[streamid].qwSctx0 = trb->qwTrb0;
1274 devep->ep_sctx_trbs[streamid].ringaddr =
1275 trb->qwTrb0 & ~0xF;
1276 devep->ep_sctx_trbs[streamid].ccs =
1277 XHCI_EPCTX_2_DCS_GET(trb->qwTrb0);
1278 }
1279 } else {
1280 if (streamid != 0) {
1281 DPRINTF(("pci_xhci cmd set_tr streamid %x != 0",
1282 streamid));
1283 }
1284 ep_ctx->qwEpCtx2 = trb->qwTrb0 & ~0xFUL;
1285 devep->ep_ringaddr = ep_ctx->qwEpCtx2 & ~0xFUL;
1286 devep->ep_ccs = trb->qwTrb0 & 0x1;
1287 devep->ep_tr = XHCI_GADDR(sc, devep->ep_ringaddr);
1288
1289 DPRINTF(("pci_xhci set_tr first TRB:"));
1290 pci_xhci_dump_trb(devep->ep_tr);
1291 }
1292 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED;
1293
1294 done:
1295 return (cmderr);
1296 }
1297
1298 static uint32_t
1299 pci_xhci_cmd_eval_ctx(struct pci_xhci_softc *sc, uint32_t slot,
1300 struct xhci_trb *trb)
1301 {
1302 struct xhci_input_dev_ctx *input_ctx;
1303 struct xhci_slot_ctx *islot_ctx;
1304 struct xhci_dev_ctx *dev_ctx;
1305 struct xhci_endp_ctx *ep0_ctx;
1306 uint32_t cmderr;
1307
1308 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
1309 islot_ctx = &input_ctx->ctx_slot;
1310 ep0_ctx = &input_ctx->ctx_ep[1];
1311
1312 cmderr = XHCI_TRB_ERROR_SUCCESS;
1313 DPRINTF(("pci_xhci: eval ctx, input ctl: D 0x%08x A 0x%08x,",
1314 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1));
1315 DPRINTF((" slot %08x %08x %08x %08x",
1316 islot_ctx->dwSctx0, islot_ctx->dwSctx1,
1317 islot_ctx->dwSctx2, islot_ctx->dwSctx3));
1318 DPRINTF((" ep0 %08x %08x %016lx %08x",
1319 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
1320 ep0_ctx->dwEpCtx4));
1321
1322 /* this command expects drop-ctx=0 & add-ctx=slot+ep0 */
1323 if ((input_ctx->ctx_input.dwInCtx0 != 0) ||
1324 (input_ctx->ctx_input.dwInCtx1 & 0x03) == 0) {
1325 DPRINTF(("pci_xhci: eval ctx, input ctl invalid"));
1326 cmderr = XHCI_TRB_ERROR_TRB;
1327 goto done;
1328 }
1329
1330 /* assign address to slot; in this emulation, slot_id = address */
1331 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1332
1333 DPRINTF(("pci_xhci: eval ctx, dev ctx"));
1334 DPRINTF((" slot %08x %08x %08x %08x",
1335 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1336 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1337
1338 if (input_ctx->ctx_input.dwInCtx1 & 0x01) { /* slot ctx */
1339 /* set max exit latency */
1340 dev_ctx->ctx_slot.dwSctx1 = FIELD_COPY(
1341 dev_ctx->ctx_slot.dwSctx1, input_ctx->ctx_slot.dwSctx1,
1342 0xFFFF, 0);
1343
1344 /* set interrupter target */
1345 dev_ctx->ctx_slot.dwSctx2 = FIELD_COPY(
1346 dev_ctx->ctx_slot.dwSctx2, input_ctx->ctx_slot.dwSctx2,
1347 0x3FF, 22);
1348 }
1349 if (input_ctx->ctx_input.dwInCtx1 & 0x02) { /* control ctx */
1350 /* set max packet size */
1351 dev_ctx->ctx_ep[1].dwEpCtx1 = FIELD_COPY(
1352 dev_ctx->ctx_ep[1].dwEpCtx1, ep0_ctx->dwEpCtx1,
1353 0xFFFF, 16);
1354
1355 ep0_ctx = &dev_ctx->ctx_ep[1];
1356 }
1357
1358 DPRINTF(("pci_xhci: eval ctx, output ctx"));
1359 DPRINTF((" slot %08x %08x %08x %08x",
1360 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1361 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1362 DPRINTF((" ep0 %08x %08x %016lx %08x",
1363 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
1364 ep0_ctx->dwEpCtx4));
1365
1366 done:
1367 return (cmderr);
1368 }
1369
1370 static int
1371 pci_xhci_complete_commands(struct pci_xhci_softc *sc)
1372 {
1373 struct xhci_trb evtrb;
1374 struct xhci_trb *trb;
1375 uint64_t crcr;
1376 uint32_t ccs; /* cycle state (XHCI 4.9.2) */
1377 uint32_t type;
1378 uint32_t slot;
1379 uint32_t cmderr;
1380 int error;
1381
1382 error = 0;
1383 sc->opregs.crcr |= XHCI_CRCR_LO_CRR;
1384
1385 trb = sc->opregs.cr_p;
1386 ccs = sc->opregs.crcr & XHCI_CRCR_LO_RCS;
1387 crcr = sc->opregs.crcr & ~0xF;
1388
1389 while (1) {
1390 sc->opregs.cr_p = trb;
1391
1392 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1393
1394 if ((trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT) !=
1395 (ccs & XHCI_TRB_3_CYCLE_BIT))
1396 break;
1397
1398 DPRINTF(("pci_xhci: cmd type 0x%x, Trb0 x%016lx dwTrb2 x%08x"
1399 " dwTrb3 x%08x, TRB_CYCLE %u/ccs %u",
1400 type, trb->qwTrb0, trb->dwTrb2, trb->dwTrb3,
1401 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT, ccs));
1402
1403 cmderr = XHCI_TRB_ERROR_SUCCESS;
1404 evtrb.dwTrb2 = 0;
1405 evtrb.dwTrb3 = (ccs & XHCI_TRB_3_CYCLE_BIT) |
1406 XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_CMD_COMPLETE);
1407 slot = 0;
1408
1409 switch (type) {
1410 case XHCI_TRB_TYPE_LINK: /* 0x06 */
1411 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT)
1412 ccs ^= XHCI_CRCR_LO_RCS;
1413 break;
1414
1415 case XHCI_TRB_TYPE_ENABLE_SLOT: /* 0x09 */
1416 cmderr = pci_xhci_cmd_enable_slot(sc, &slot);
1417 break;
1418
1419 case XHCI_TRB_TYPE_DISABLE_SLOT: /* 0x0A */
1420 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1421 cmderr = pci_xhci_cmd_disable_slot(sc, slot);
1422 break;
1423
1424 case XHCI_TRB_TYPE_ADDRESS_DEVICE: /* 0x0B */
1425 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1426 cmderr = pci_xhci_cmd_address_device(sc, slot, trb);
1427 break;
1428
1429 case XHCI_TRB_TYPE_CONFIGURE_EP: /* 0x0C */
1430 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1431 cmderr = pci_xhci_cmd_config_ep(sc, slot, trb);
1432 break;
1433
1434 case XHCI_TRB_TYPE_EVALUATE_CTX: /* 0x0D */
1435 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1436 cmderr = pci_xhci_cmd_eval_ctx(sc, slot, trb);
1437 break;
1438
1439 case XHCI_TRB_TYPE_RESET_EP: /* 0x0E */
1440 DPRINTF(("Reset Endpoint on slot %d", slot));
1441 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1442 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb);
1443 break;
1444
1445 case XHCI_TRB_TYPE_STOP_EP: /* 0x0F */
1446 DPRINTF(("Stop Endpoint on slot %d", slot));
1447 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1448 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb);
1449 break;
1450
1451 case XHCI_TRB_TYPE_SET_TR_DEQUEUE: /* 0x10 */
1452 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1453 cmderr = pci_xhci_cmd_set_tr(sc, slot, trb);
1454 break;
1455
1456 case XHCI_TRB_TYPE_RESET_DEVICE: /* 0x11 */
1457 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1458 cmderr = pci_xhci_cmd_reset_device(sc, slot);
1459 break;
1460
1461 case XHCI_TRB_TYPE_FORCE_EVENT: /* 0x12 */
1462 /* TODO: */
1463 break;
1464
1465 case XHCI_TRB_TYPE_NEGOTIATE_BW: /* 0x13 */
1466 break;
1467
1468 case XHCI_TRB_TYPE_SET_LATENCY_TOL: /* 0x14 */
1469 break;
1470
1471 case XHCI_TRB_TYPE_GET_PORT_BW: /* 0x15 */
1472 break;
1473
1474 case XHCI_TRB_TYPE_FORCE_HEADER: /* 0x16 */
1475 break;
1476
1477 case XHCI_TRB_TYPE_NOOP_CMD: /* 0x17 */
1478 break;
1479
1480 default:
1481 DPRINTF(("pci_xhci: unsupported cmd %x", type));
1482 break;
1483 }
1484
1485 if (type != XHCI_TRB_TYPE_LINK) {
1486 /*
1487 * insert command completion event and assert intr
1488 */
1489 evtrb.qwTrb0 = crcr;
1490 evtrb.dwTrb2 |= XHCI_TRB_2_ERROR_SET(cmderr);
1491 evtrb.dwTrb3 |= XHCI_TRB_3_SLOT_SET(slot);
1492 DPRINTF(("pci_xhci: command 0x%x result: 0x%x",
1493 type, cmderr));
1494 pci_xhci_insert_event(sc, &evtrb, 1);
1495 }
1496
1497 trb = pci_xhci_trb_next(sc, trb, &crcr);
1498 }
1499
1500 sc->opregs.crcr = crcr | (sc->opregs.crcr & XHCI_CRCR_LO_CA) | ccs;
1501 sc->opregs.crcr &= ~XHCI_CRCR_LO_CRR;
1502 return (error);
1503 }
1504
1505 static void
1506 pci_xhci_dump_trb(struct xhci_trb *trb)
1507 {
1508 static const char *trbtypes[] = {
1509 "RESERVED",
1510 "NORMAL",
1511 "SETUP_STAGE",
1512 "DATA_STAGE",
1513 "STATUS_STAGE",
1514 "ISOCH",
1515 "LINK",
1516 "EVENT_DATA",
1517 "NOOP",
1518 "ENABLE_SLOT",
1519 "DISABLE_SLOT",
1520 "ADDRESS_DEVICE",
1521 "CONFIGURE_EP",
1522 "EVALUATE_CTX",
1523 "RESET_EP",
1524 "STOP_EP",
1525 "SET_TR_DEQUEUE",
1526 "RESET_DEVICE",
1527 "FORCE_EVENT",
1528 "NEGOTIATE_BW",
1529 "SET_LATENCY_TOL",
1530 "GET_PORT_BW",
1531 "FORCE_HEADER",
1532 "NOOP_CMD"
1533 };
1534 uint32_t type;
1535
1536 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1537 DPRINTF(("pci_xhci: trb[@%p] type x%02x %s 0:x%016lx 2:x%08x 3:x%08x",
1538 trb, type,
1539 type <= XHCI_TRB_TYPE_NOOP_CMD ? trbtypes[type] : "INVALID",
1540 trb->qwTrb0, trb->dwTrb2, trb->dwTrb3));
1541 }
1542
1543 static int
1544 pci_xhci_xfer_complete(struct pci_xhci_softc *sc, struct usb_data_xfer *xfer,
1545 uint32_t slot, uint32_t epid, int *do_intr)
1546 {
1547 struct pci_xhci_dev_emu *dev;
1548 struct pci_xhci_dev_ep *devep;
1549 struct xhci_dev_ctx *dev_ctx;
1550 struct xhci_endp_ctx *ep_ctx;
1551 struct xhci_trb *trb;
1552 struct xhci_trb evtrb;
1553 uint32_t trbflags;
1554 uint32_t edtla;
1555 int i, err;
1556
1557 dev = XHCI_SLOTDEV_PTR(sc, slot);
1558 devep = &dev->eps[epid];
1559 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1560
1561 assert(dev_ctx != NULL);
1562
1563 ep_ctx = &dev_ctx->ctx_ep[epid];
1564
1565 err = XHCI_TRB_ERROR_SUCCESS;
1566 *do_intr = 0;
1567 edtla = 0;
1568
1569 /* go through list of TRBs and insert event(s) */
1570 for (i = xfer->head; xfer->ndata > 0; ) {
1571 evtrb.qwTrb0 = (uint64_t)xfer->data[i].hci_data;
1572 trb = XHCI_GADDR(sc, evtrb.qwTrb0);
1573 trbflags = trb->dwTrb3;
1574
1575 DPRINTF(("pci_xhci: xfer[%d] done?%u:%d trb %x %016lx %x "
1576 "(err %d) IOC?%d",
1577 i, xfer->data[i].processed, xfer->data[i].blen,
1578 XHCI_TRB_3_TYPE_GET(trbflags), evtrb.qwTrb0,
1579 trbflags, err,
1580 trb->dwTrb3 & XHCI_TRB_3_IOC_BIT ? 1 : 0));
1581
1582 if (!xfer->data[i].processed) {
1583 xfer->head = i;
1584 break;
1585 }
1586
1587 xfer->ndata--;
1588 edtla += xfer->data[i].bdone;
1589
1590 trb->dwTrb3 = (trb->dwTrb3 & ~0x1) | (xfer->data[i].ccs);
1591
1592 pci_xhci_update_ep_ring(sc, dev, devep, ep_ctx,
1593 xfer->data[i].streamid, xfer->data[i].trbnext,
1594 xfer->data[i].ccs);
1595
1596 /* Only interrupt if IOC or short packet */
1597 if (!(trb->dwTrb3 & XHCI_TRB_3_IOC_BIT) &&
1598 !((err == XHCI_TRB_ERROR_SHORT_PKT) &&
1599 (trb->dwTrb3 & XHCI_TRB_3_ISP_BIT))) {
1600
1601 i = (i + 1) % USB_MAX_XFER_BLOCKS;
1602 continue;
1603 }
1604
1605 evtrb.dwTrb2 = XHCI_TRB_2_ERROR_SET(err) |
1606 XHCI_TRB_2_REM_SET(xfer->data[i].blen);
1607
1608 evtrb.dwTrb3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_TRANSFER) |
1609 XHCI_TRB_3_SLOT_SET(slot) | XHCI_TRB_3_EP_SET(epid);
1610
1611 if (XHCI_TRB_3_TYPE_GET(trbflags) == XHCI_TRB_TYPE_EVENT_DATA) {
1612 DPRINTF(("pci_xhci EVENT_DATA edtla %u", edtla));
1613 evtrb.qwTrb0 = trb->qwTrb0;
1614 evtrb.dwTrb2 = (edtla & 0xFFFFF) |
1615 XHCI_TRB_2_ERROR_SET(err);
1616 evtrb.dwTrb3 |= XHCI_TRB_3_ED_BIT;
1617 edtla = 0;
1618 }
1619
1620 *do_intr = 1;
1621
1622 err = pci_xhci_insert_event(sc, &evtrb, 0);
1623 if (err != XHCI_TRB_ERROR_SUCCESS) {
1624 break;
1625 }
1626
1627 i = (i + 1) % USB_MAX_XFER_BLOCKS;
1628 }
1629
1630 return (err);
1631 }
1632
1633 static void
1634 pci_xhci_update_ep_ring(struct pci_xhci_softc *sc,
1635 struct pci_xhci_dev_emu *dev __unused, struct pci_xhci_dev_ep *devep,
1636 struct xhci_endp_ctx *ep_ctx, uint32_t streamid, uint64_t ringaddr, int ccs)
1637 {
1638
1639 if (devep->ep_MaxPStreams != 0) {
1640 devep->ep_sctx[streamid].qwSctx0 = (ringaddr & ~0xFUL) |
1641 (ccs & 0x1);
1642
1643 devep->ep_sctx_trbs[streamid].ringaddr = ringaddr & ~0xFUL;
1644 devep->ep_sctx_trbs[streamid].ccs = ccs & 0x1;
1645 ep_ctx->qwEpCtx2 = (ep_ctx->qwEpCtx2 & ~0x1) | (ccs & 0x1);
1646
1647 DPRINTF(("xhci update ep-ring stream %d, addr %lx",
1648 streamid, devep->ep_sctx[streamid].qwSctx0));
1649 } else {
1650 devep->ep_ringaddr = ringaddr & ~0xFUL;
1651 devep->ep_ccs = ccs & 0x1;
1652 devep->ep_tr = XHCI_GADDR(sc, ringaddr & ~0xFUL);
1653 ep_ctx->qwEpCtx2 = (ringaddr & ~0xFUL) | (ccs & 0x1);
1654
1655 DPRINTF(("xhci update ep-ring, addr %lx",
1656 (devep->ep_ringaddr | devep->ep_ccs)));
1657 }
1658 }
1659
1660 /*
1661 * Outstanding transfer still in progress (device NAK'd earlier) so retry
1662 * the transfer again to see if it succeeds.
1663 */
1664 static int
1665 pci_xhci_try_usb_xfer(struct pci_xhci_softc *sc,
1666 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
1667 struct xhci_endp_ctx *ep_ctx, uint32_t slot, uint32_t epid)
1668 {
1669 struct usb_data_xfer *xfer;
1670 int err;
1671 int do_intr;
1672
1673 ep_ctx->dwEpCtx0 = FIELD_REPLACE(
1674 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1675
1676 err = 0;
1677 do_intr = 0;
1678
1679 xfer = devep->ep_xfer;
1680 #ifdef __FreeBSD__
1681 USB_DATA_XFER_LOCK(xfer);
1682 #else
1683 /*
1684 * At least one caller needs to hold this lock across the call to this
1685 * function and other code. To avoid deadlock from a recursive mutex
1686 * enter, we ensure that all callers hold this lock.
1687 */
1688 assert(USB_DATA_XFER_LOCK_HELD(xfer));
1689 #endif
1690
1691 /* outstanding requests queued up */
1692 if (dev->dev_ue->ue_data != NULL) {
1693 err = dev->dev_ue->ue_data(dev->dev_sc, xfer,
1694 epid & 0x1 ? USB_XFER_IN : USB_XFER_OUT, epid/2);
1695 if (err == USB_ERR_CANCELLED) {
1696 if (USB_DATA_GET_ERRCODE(&xfer->data[xfer->head]) ==
1697 USB_NAK)
1698 err = XHCI_TRB_ERROR_SUCCESS;
1699 } else {
1700 err = pci_xhci_xfer_complete(sc, xfer, slot, epid,
1701 &do_intr);
1702 if (err == XHCI_TRB_ERROR_SUCCESS && do_intr) {
1703 pci_xhci_assert_interrupt(sc);
1704 }
1705
1706
1707 /* XXX should not do it if error? */
1708 USB_DATA_XFER_RESET(xfer);
1709 }
1710 }
1711
1712 #ifdef __FreeBSD__
1713 USB_DATA_XFER_UNLOCK(xfer);
1714 #endif
1715
1716 return (err);
1717 }
1718
1719
1720 static int
1721 pci_xhci_handle_transfer(struct pci_xhci_softc *sc,
1722 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
1723 struct xhci_endp_ctx *ep_ctx, struct xhci_trb *trb, uint32_t slot,
1724 uint32_t epid, uint64_t addr, uint32_t ccs, uint32_t streamid)
1725 {
1726 struct xhci_trb *setup_trb;
1727 struct usb_data_xfer *xfer;
1728 struct usb_data_xfer_block *xfer_block;
1729 uint64_t val;
1730 uint32_t trbflags;
1731 int do_intr, err;
1732 int do_retry;
1733
1734 ep_ctx->dwEpCtx0 = FIELD_REPLACE(ep_ctx->dwEpCtx0,
1735 XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1736
1737 xfer = devep->ep_xfer;
1738 USB_DATA_XFER_LOCK(xfer);
1739
1740 DPRINTF(("pci_xhci handle_transfer slot %u", slot));
1741
1742 retry:
1743 err = XHCI_TRB_ERROR_INVALID;
1744 do_retry = 0;
1745 do_intr = 0;
1746 setup_trb = NULL;
1747
1748 while (1) {
1749 pci_xhci_dump_trb(trb);
1750
1751 trbflags = trb->dwTrb3;
1752
1753 if (XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK &&
1754 (trbflags & XHCI_TRB_3_CYCLE_BIT) !=
1755 (ccs & XHCI_TRB_3_CYCLE_BIT)) {
1756 DPRINTF(("Cycle-bit changed trbflags %x, ccs %x",
1757 trbflags & XHCI_TRB_3_CYCLE_BIT, ccs));
1758 break;
1759 }
1760
1761 xfer_block = NULL;
1762
1763 switch (XHCI_TRB_3_TYPE_GET(trbflags)) {
1764 case XHCI_TRB_TYPE_LINK:
1765 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT)
1766 ccs ^= 0x1;
1767
1768 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1769 (void *)addr, ccs);
1770 xfer_block->processed = 1;
1771 break;
1772
1773 case XHCI_TRB_TYPE_SETUP_STAGE:
1774 if ((trbflags & XHCI_TRB_3_IDT_BIT) == 0 ||
1775 XHCI_TRB_2_BYTES_GET(trb->dwTrb2) != 8) {
1776 DPRINTF(("pci_xhci: invalid setup trb"));
1777 err = XHCI_TRB_ERROR_TRB;
1778 goto errout;
1779 }
1780 setup_trb = trb;
1781
1782 val = trb->qwTrb0;
1783 if (!xfer->ureq)
1784 xfer->ureq = malloc(
1785 sizeof(struct usb_device_request));
1786 memcpy(xfer->ureq, &val,
1787 sizeof(struct usb_device_request));
1788
1789 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1790 (void *)addr, ccs);
1791 xfer_block->processed = 1;
1792 break;
1793
1794 case XHCI_TRB_TYPE_NORMAL:
1795 case XHCI_TRB_TYPE_ISOCH:
1796 if (setup_trb != NULL) {
1797 DPRINTF(("pci_xhci: trb not supposed to be in "
1798 "ctl scope"));
1799 err = XHCI_TRB_ERROR_TRB;
1800 goto errout;
1801 }
1802 /* fall through */
1803
1804 case XHCI_TRB_TYPE_DATA_STAGE:
1805 xfer_block = usb_data_xfer_append(xfer,
1806 (void *)(trbflags & XHCI_TRB_3_IDT_BIT ?
1807 &trb->qwTrb0 : XHCI_GADDR(sc, trb->qwTrb0)),
1808 trb->dwTrb2 & 0x1FFFF, (void *)addr, ccs);
1809 break;
1810
1811 case XHCI_TRB_TYPE_STATUS_STAGE:
1812 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1813 (void *)addr, ccs);
1814 break;
1815
1816 case XHCI_TRB_TYPE_NOOP:
1817 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1818 (void *)addr, ccs);
1819 xfer_block->processed = 1;
1820 break;
1821
1822 case XHCI_TRB_TYPE_EVENT_DATA:
1823 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1824 (void *)addr, ccs);
1825 if ((epid > 1) && (trbflags & XHCI_TRB_3_IOC_BIT)) {
1826 xfer_block->processed = 1;
1827 }
1828 break;
1829
1830 default:
1831 DPRINTF(("pci_xhci: handle xfer unexpected trb type "
1832 "0x%x",
1833 XHCI_TRB_3_TYPE_GET(trbflags)));
1834 err = XHCI_TRB_ERROR_TRB;
1835 goto errout;
1836 }
1837
1838 trb = pci_xhci_trb_next(sc, trb, &addr);
1839
1840 DPRINTF(("pci_xhci: next trb: 0x%lx", (uint64_t)trb));
1841
1842 if (xfer_block) {
1843 xfer_block->trbnext = addr;
1844 xfer_block->streamid = streamid;
1845 }
1846
1847 if (!setup_trb && !(trbflags & XHCI_TRB_3_CHAIN_BIT) &&
1848 XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK) {
1849 break;
1850 }
1851
1852 /* handle current batch that requires interrupt on complete */
1853 if (trbflags & XHCI_TRB_3_IOC_BIT) {
1854 DPRINTF(("pci_xhci: trb IOC bit set"));
1855 if (epid == 1)
1856 do_retry = 1;
1857 break;
1858 }
1859 }
1860
1861 DPRINTF(("pci_xhci[%d]: xfer->ndata %u", __LINE__, xfer->ndata));
1862
1863 if (xfer->ndata <= 0)
1864 goto errout;
1865
1866 if (epid == 1) {
1867 int usberr;
1868
1869 if (dev->dev_ue->ue_request != NULL)
1870 usberr = dev->dev_ue->ue_request(dev->dev_sc, xfer);
1871 else
1872 usberr = USB_ERR_NOT_STARTED;
1873 err = USB_TO_XHCI_ERR(usberr);
1874 if (err == XHCI_TRB_ERROR_SUCCESS ||
1875 err == XHCI_TRB_ERROR_STALL ||
1876 err == XHCI_TRB_ERROR_SHORT_PKT) {
1877 err = pci_xhci_xfer_complete(sc, xfer, slot, epid,
1878 &do_intr);
1879 if (err != XHCI_TRB_ERROR_SUCCESS)
1880 do_retry = 0;
1881 }
1882
1883 } else {
1884 /* handle data transfer */
1885 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid);
1886 err = XHCI_TRB_ERROR_SUCCESS;
1887 }
1888
1889 errout:
1890 if (err == XHCI_TRB_ERROR_EV_RING_FULL)
1891 DPRINTF(("pci_xhci[%d]: event ring full", __LINE__));
1892
1893 if (!do_retry)
1894 USB_DATA_XFER_UNLOCK(xfer);
1895
1896 if (do_intr)
1897 pci_xhci_assert_interrupt(sc);
1898
1899 if (do_retry) {
1900 USB_DATA_XFER_RESET(xfer);
1901 DPRINTF(("pci_xhci[%d]: retry:continuing with next TRBs",
1902 __LINE__));
1903 goto retry;
1904 }
1905
1906 if (epid == 1)
1907 USB_DATA_XFER_RESET(xfer);
1908
1909 return (err);
1910 }
1911
1912 static void
1913 pci_xhci_device_doorbell(struct pci_xhci_softc *sc, uint32_t slot,
1914 uint32_t epid, uint32_t streamid)
1915 {
1916 struct pci_xhci_dev_emu *dev;
1917 struct pci_xhci_dev_ep *devep;
1918 struct xhci_dev_ctx *dev_ctx;
1919 struct xhci_endp_ctx *ep_ctx;
1920 struct pci_xhci_trb_ring *sctx_tr;
1921 struct xhci_trb *trb;
1922 uint64_t ringaddr;
1923 uint32_t ccs;
1924 int error;
1925
1926 DPRINTF(("pci_xhci doorbell slot %u epid %u stream %u",
1927 slot, epid, streamid));
1928
1929 if (slot == 0 || slot > XHCI_MAX_SLOTS) {
1930 DPRINTF(("pci_xhci: invalid doorbell slot %u", slot));
1931 return;
1932 }
1933
1934 if (epid == 0 || epid >= XHCI_MAX_ENDPOINTS) {
1935 DPRINTF(("pci_xhci: invalid endpoint %u", epid));
1936 return;
1937 }
1938
1939 dev = XHCI_SLOTDEV_PTR(sc, slot);
1940 devep = &dev->eps[epid];
1941 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1942 if (!dev_ctx) {
1943 return;
1944 }
1945 ep_ctx = &dev_ctx->ctx_ep[epid];
1946
1947 sctx_tr = NULL;
1948
1949 DPRINTF(("pci_xhci: device doorbell ep[%u] %08x %08x %016lx %08x",
1950 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2,
1951 ep_ctx->dwEpCtx4));
1952
1953 if (ep_ctx->qwEpCtx2 == 0)
1954 return;
1955
1956 /* handle pending transfers */
1957 if (devep->ep_xfer->ndata > 0) {
1958 #ifndef __FreeBSD__
1959 USB_DATA_XFER_LOCK(devep->ep_xfer);
1960 #endif
1961 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid);
1962 #ifndef __FreeBSD__
1963 USB_DATA_XFER_UNLOCK(devep->ep_xfer);
1964 #endif
1965 return;
1966 }
1967
1968 /* get next trb work item */
1969 if (devep->ep_MaxPStreams != 0) {
1970 /*
1971 * Stream IDs of 0, 65535 (any stream), and 65534
1972 * (prime) are invalid.
1973 */
1974 if (streamid == 0 || streamid == 65534 || streamid == 65535) {
1975 DPRINTF(("pci_xhci: invalid stream %u", streamid));
1976 return;
1977 }
1978
1979 error = pci_xhci_find_stream(sc, ep_ctx, devep, streamid);
1980 if (error != XHCI_TRB_ERROR_SUCCESS) {
1981 DPRINTF(("pci_xhci: invalid stream %u: %d",
1982 streamid, error));
1983 return;
1984 }
1985 sctx_tr = &devep->ep_sctx_trbs[streamid];
1986 ringaddr = sctx_tr->ringaddr;
1987 ccs = sctx_tr->ccs;
1988 trb = XHCI_GADDR(sc, sctx_tr->ringaddr & ~0xFUL);
1989 DPRINTF(("doorbell, stream %u, ccs %lx, trb ccs %x",
1990 streamid, ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT,
1991 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT));
1992 } else {
1993 if (streamid != 0) {
1994 DPRINTF(("pci_xhci: invalid stream %u", streamid));
1995 return;
1996 }
1997 ringaddr = devep->ep_ringaddr;
1998 ccs = devep->ep_ccs;
1999 trb = devep->ep_tr;
2000 DPRINTF(("doorbell, ccs %lx, trb ccs %x",
2001 ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT,
2002 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT));
2003 }
2004
2005 if (XHCI_TRB_3_TYPE_GET(trb->dwTrb3) == 0) {
2006 DPRINTF(("pci_xhci: ring %lx trb[%lx] EP %u is RESERVED?",
2007 ep_ctx->qwEpCtx2, devep->ep_ringaddr, epid));
2008 return;
2009 }
2010
2011 pci_xhci_handle_transfer(sc, dev, devep, ep_ctx, trb, slot, epid,
2012 ringaddr, ccs, streamid);
2013 }
2014
2015 static void
2016 pci_xhci_dbregs_write(struct pci_xhci_softc *sc, uint64_t offset,
2017 uint64_t value)
2018 {
2019
2020 offset = (offset - sc->dboff) / sizeof(uint32_t);
2021
2022 DPRINTF(("pci_xhci: doorbell write offset 0x%lx: 0x%lx",
2023 offset, value));
2024
2025 if (XHCI_HALTED(sc)) {
2026 DPRINTF(("pci_xhci: controller halted"));
2027 return;
2028 }
2029
2030 if (offset == 0)
2031 pci_xhci_complete_commands(sc);
2032 else if (sc->portregs != NULL)
2033 pci_xhci_device_doorbell(sc, offset,
2034 XHCI_DB_TARGET_GET(value), XHCI_DB_SID_GET(value));
2035 }
2036
2037 static void
2038 pci_xhci_rtsregs_write(struct pci_xhci_softc *sc, uint64_t offset,
2039 uint64_t value)
2040 {
2041 struct pci_xhci_rtsregs *rts;
2042
2043 offset -= sc->rtsoff;
2044
2045 if (offset == 0) {
2046 DPRINTF(("pci_xhci attempted write to MFINDEX"));
2047 return;
2048 }
2049
2050 DPRINTF(("pci_xhci: runtime regs write offset 0x%lx: 0x%lx",
2051 offset, value));
2052
2053 offset -= 0x20; /* start of intrreg */
2054
2055 rts = &sc->rtsregs;
2056
2057 switch (offset) {
2058 case 0x00:
2059 if (value & XHCI_IMAN_INTR_PEND)
2060 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND;
2061 rts->intrreg.iman = (value & XHCI_IMAN_INTR_ENA) |
2062 (rts->intrreg.iman & XHCI_IMAN_INTR_PEND);
2063
2064 if (!(value & XHCI_IMAN_INTR_ENA))
2065 pci_xhci_deassert_interrupt(sc);
2066
2067 break;
2068
2069 case 0x04:
2070 rts->intrreg.imod = value;
2071 break;
2072
2073 case 0x08:
2074 rts->intrreg.erstsz = value & 0xFFFF;
2075 break;
2076
2077 case 0x10:
2078 /* ERSTBA low bits */
2079 rts->intrreg.erstba = MASK_64_HI(sc->rtsregs.intrreg.erstba) |
2080 (value & ~0x3F);
2081 break;
2082
2083 case 0x14:
2084 /* ERSTBA high bits */
2085 rts->intrreg.erstba = (value << 32) |
2086 MASK_64_LO(sc->rtsregs.intrreg.erstba);
2087
2088 rts->erstba_p = XHCI_GADDR(sc,
2089 sc->rtsregs.intrreg.erstba & ~0x3FUL);
2090
2091 rts->erst_p = XHCI_GADDR(sc,
2092 sc->rtsregs.erstba_p->qwEvrsTablePtr & ~0x3FUL);
2093
2094 rts->er_enq_idx = 0;
2095 rts->er_events_cnt = 0;
2096
2097 DPRINTF(("pci_xhci: wr erstba erst (%p) ptr 0x%lx, sz %u",
2098 rts->erstba_p,
2099 rts->erstba_p->qwEvrsTablePtr,
2100 rts->erstba_p->dwEvrsTableSize));
2101 break;
2102
2103 case 0x18:
2104 /* ERDP low bits */
2105 rts->intrreg.erdp =
2106 MASK_64_HI(sc->rtsregs.intrreg.erdp) |
2107 (rts->intrreg.erdp & XHCI_ERDP_LO_BUSY) |
2108 (value & ~0xF);
2109 if (value & XHCI_ERDP_LO_BUSY) {
2110 rts->intrreg.erdp &= ~XHCI_ERDP_LO_BUSY;
2111 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND;
2112 }
2113
2114 rts->er_deq_seg = XHCI_ERDP_LO_SINDEX(value);
2115
2116 break;
2117
2118 case 0x1C:
2119 /* ERDP high bits */
2120 rts->intrreg.erdp = (value << 32) |
2121 MASK_64_LO(sc->rtsregs.intrreg.erdp);
2122
2123 if (rts->er_events_cnt > 0) {
2124 uint64_t erdp;
2125 int erdp_i;
2126
2127 erdp = rts->intrreg.erdp & ~0xF;
2128 erdp_i = (erdp - rts->erstba_p->qwEvrsTablePtr) /
2129 sizeof(struct xhci_trb);
2130
2131 if (erdp_i <= rts->er_enq_idx)
2132 rts->er_events_cnt = rts->er_enq_idx - erdp_i;
2133 else
2134 rts->er_events_cnt =
2135 rts->erstba_p->dwEvrsTableSize -
2136 (erdp_i - rts->er_enq_idx);
2137
2138 DPRINTF(("pci_xhci: erdp 0x%lx, events cnt %u",
2139 erdp, rts->er_events_cnt));
2140 }
2141
2142 break;
2143
2144 default:
2145 DPRINTF(("pci_xhci attempted write to RTS offset 0x%lx",
2146 offset));
2147 break;
2148 }
2149 }
2150
2151 static uint64_t
2152 pci_xhci_portregs_read(struct pci_xhci_softc *sc, uint64_t offset)
2153 {
2154 struct pci_xhci_portregs *portregs;
2155 int port;
2156 uint32_t reg;
2157
2158 if (sc->portregs == NULL)
2159 return (0);
2160
2161 port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ;
2162 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ;
2163
2164 if (port > XHCI_MAX_DEVS) {
2165 DPRINTF(("pci_xhci: portregs_read port %d >= XHCI_MAX_DEVS",
2166 port));
2167
2168 /* return default value for unused port */
2169 return (XHCI_PS_SPEED_SET(3));
2170 }
2171
2172 portregs = XHCI_PORTREG_PTR(sc, port);
2173 switch (offset) {
2174 case 0:
2175 reg = portregs->portsc;
2176 break;
2177 case 4:
2178 reg = portregs->portpmsc;
2179 break;
2180 case 8:
2181 reg = portregs->portli;
2182 break;
2183 case 12:
2184 reg = portregs->porthlpmc;
2185 break;
2186 default:
2187 DPRINTF(("pci_xhci: unaligned portregs read offset %#lx",
2188 offset));
2189 reg = 0xffffffff;
2190 break;
2191 }
2192
2193 DPRINTF(("pci_xhci: portregs read offset 0x%lx port %u -> 0x%x",
2194 offset, port, reg));
2195
2196 return (reg);
2197 }
2198
2199 static void
2200 pci_xhci_hostop_write(struct pci_xhci_softc *sc, uint64_t offset,
2201 uint64_t value)
2202 {
2203 offset -= XHCI_CAPLEN;
2204
2205 if (offset < 0x400)
2206 DPRINTF(("pci_xhci: hostop write offset 0x%lx: 0x%lx",
2207 offset, value));
2208
2209 switch (offset) {
2210 case XHCI_USBCMD:
2211 sc->opregs.usbcmd = pci_xhci_usbcmd_write(sc, value & 0x3F0F);
2212 break;
2213
2214 case XHCI_USBSTS:
2215 /* clear bits on write */
2216 sc->opregs.usbsts &= ~(value &
2217 (XHCI_STS_HSE|XHCI_STS_EINT|XHCI_STS_PCD|XHCI_STS_SSS|
2218 XHCI_STS_RSS|XHCI_STS_SRE|XHCI_STS_CNR));
2219 break;
2220
2221 case XHCI_PAGESIZE:
2222 /* read only */
2223 break;
2224
2225 case XHCI_DNCTRL:
2226 sc->opregs.dnctrl = value & 0xFFFF;
2227 break;
2228
2229 case XHCI_CRCR_LO:
2230 if (sc->opregs.crcr & XHCI_CRCR_LO_CRR) {
2231 sc->opregs.crcr &= ~(XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA);
2232 sc->opregs.crcr |= value &
2233 (XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA);
2234 } else {
2235 sc->opregs.crcr = MASK_64_HI(sc->opregs.crcr) |
2236 (value & (0xFFFFFFC0 | XHCI_CRCR_LO_RCS));
2237 }
2238 break;
2239
2240 case XHCI_CRCR_HI:
2241 if (!(sc->opregs.crcr & XHCI_CRCR_LO_CRR)) {
2242 sc->opregs.crcr = MASK_64_LO(sc->opregs.crcr) |
2243 (value << 32);
2244
2245 sc->opregs.cr_p = XHCI_GADDR(sc,
2246 sc->opregs.crcr & ~0xF);
2247 }
2248
2249 if (sc->opregs.crcr & XHCI_CRCR_LO_CS) {
2250 /* Stop operation of Command Ring */
2251 }
2252
2253 if (sc->opregs.crcr & XHCI_CRCR_LO_CA) {
2254 /* Abort command */
2255 }
2256
2257 break;
2258
2259 case XHCI_DCBAAP_LO:
2260 sc->opregs.dcbaap = MASK_64_HI(sc->opregs.dcbaap) |
2261 (value & 0xFFFFFFC0);
2262 break;
2263
2264 case XHCI_DCBAAP_HI:
2265 sc->opregs.dcbaap = MASK_64_LO(sc->opregs.dcbaap) |
2266 (value << 32);
2267 sc->opregs.dcbaa_p = XHCI_GADDR(sc, sc->opregs.dcbaap & ~0x3FUL);
2268
2269 DPRINTF(("pci_xhci: opregs dcbaap = 0x%lx (vaddr 0x%lx)",
2270 sc->opregs.dcbaap, (uint64_t)sc->opregs.dcbaa_p));
2271 break;
2272
2273 case XHCI_CONFIG:
2274 sc->opregs.config = value & 0x03FF;
2275 break;
2276
2277 default:
2278 if (offset >= 0x400)
2279 pci_xhci_portregs_write(sc, offset, value);
2280
2281 break;
2282 }
2283 }
2284
2285
2286 static void
2287 pci_xhci_write(struct vmctx *ctx __unused,
2288 struct pci_devinst *pi, int baridx, uint64_t offset, int size __unused,
2289 uint64_t value)
2290 {
2291 struct pci_xhci_softc *sc;
2292
2293 sc = pi->pi_arg;
2294
2295 assert(baridx == 0);
2296
2297
2298 pthread_mutex_lock(&sc->mtx);
2299 if (offset < XHCI_CAPLEN) /* read only registers */
2300 WPRINTF(("pci_xhci: write RO-CAPs offset %ld", offset));
2301 else if (offset < sc->dboff)
2302 pci_xhci_hostop_write(sc, offset, value);
2303 else if (offset < sc->rtsoff)
2304 pci_xhci_dbregs_write(sc, offset, value);
2305 else if (offset < sc->regsend)
2306 pci_xhci_rtsregs_write(sc, offset, value);
2307 else
2308 WPRINTF(("pci_xhci: write invalid offset %ld", offset));
2309
2310 pthread_mutex_unlock(&sc->mtx);
2311 }
2312
2313 static uint64_t
2314 pci_xhci_hostcap_read(struct pci_xhci_softc *sc, uint64_t offset)
2315 {
2316 uint64_t value;
2317
2318 switch (offset) {
2319 case XHCI_CAPLENGTH: /* 0x00 */
2320 value = sc->caplength;
2321 break;
2322
2323 case XHCI_HCSPARAMS1: /* 0x04 */
2324 value = sc->hcsparams1;
2325 break;
2326
2327 case XHCI_HCSPARAMS2: /* 0x08 */
2328 value = sc->hcsparams2;
2329 break;
2330
2331 case XHCI_HCSPARAMS3: /* 0x0C */
2332 value = sc->hcsparams3;
2333 break;
2334
2335 case XHCI_HCSPARAMS0: /* 0x10 */
2336 value = sc->hccparams1;
2337 break;
2338
2339 case XHCI_DBOFF: /* 0x14 */
2340 value = sc->dboff;
2341 break;
2342
2343 case XHCI_RTSOFF: /* 0x18 */
2344 value = sc->rtsoff;
2345 break;
2346
2347 case XHCI_HCCPRAMS2: /* 0x1C */
2348 value = sc->hccparams2;
2349 break;
2350
2351 default:
2352 value = 0;
2353 break;
2354 }
2355
2356 DPRINTF(("pci_xhci: hostcap read offset 0x%lx -> 0x%lx",
2357 offset, value));
2358
2359 return (value);
2360 }
2361
2362 static uint64_t
2363 pci_xhci_hostop_read(struct pci_xhci_softc *sc, uint64_t offset)
2364 {
2365 uint64_t value;
2366
2367 offset = (offset - XHCI_CAPLEN);
2368
2369 switch (offset) {
2370 case XHCI_USBCMD: /* 0x00 */
2371 value = sc->opregs.usbcmd;
2372 break;
2373
2374 case XHCI_USBSTS: /* 0x04 */
2375 value = sc->opregs.usbsts;
2376 break;
2377
2378 case XHCI_PAGESIZE: /* 0x08 */
2379 value = sc->opregs.pgsz;
2380 break;
2381
2382 case XHCI_DNCTRL: /* 0x14 */
2383 value = sc->opregs.dnctrl;
2384 break;
2385
2386 case XHCI_CRCR_LO: /* 0x18 */
2387 value = sc->opregs.crcr & XHCI_CRCR_LO_CRR;
2388 break;
2389
2390 case XHCI_CRCR_HI: /* 0x1C */
2391 value = 0;
2392 break;
2393
2394 case XHCI_DCBAAP_LO: /* 0x30 */
2395 value = sc->opregs.dcbaap & 0xFFFFFFFF;
2396 break;
2397
2398 case XHCI_DCBAAP_HI: /* 0x34 */
2399 value = (sc->opregs.dcbaap >> 32) & 0xFFFFFFFF;
2400 break;
2401
2402 case XHCI_CONFIG: /* 0x38 */
2403 value = sc->opregs.config;
2404 break;
2405
2406 default:
2407 if (offset >= 0x400)
2408 value = pci_xhci_portregs_read(sc, offset);
2409 else
2410 value = 0;
2411
2412 break;
2413 }
2414
2415 if (offset < 0x400)
2416 DPRINTF(("pci_xhci: hostop read offset 0x%lx -> 0x%lx",
2417 offset, value));
2418
2419 return (value);
2420 }
2421
2422 static uint64_t
2423 pci_xhci_dbregs_read(struct pci_xhci_softc *sc __unused,
2424 uint64_t offset __unused)
2425 {
2426 /* read doorbell always returns 0 */
2427 return (0);
2428 }
2429
2430 static uint64_t
2431 pci_xhci_rtsregs_read(struct pci_xhci_softc *sc, uint64_t offset)
2432 {
2433 uint32_t value;
2434
2435 offset -= sc->rtsoff;
2436 value = 0;
2437
2438 if (offset == XHCI_MFINDEX) {
2439 value = sc->rtsregs.mfindex;
2440 } else if (offset >= 0x20) {
2441 int item;
2442 uint32_t *p;
2443
2444 offset -= 0x20;
2445 item = offset % 32;
2446
2447 assert(offset < sizeof(sc->rtsregs.intrreg));
2448
2449 p = &sc->rtsregs.intrreg.iman;
2450 p += item / sizeof(uint32_t);
2451 value = *p;
2452 }
2453
2454 DPRINTF(("pci_xhci: rtsregs read offset 0x%lx -> 0x%x",
2455 offset, value));
2456
2457 return (value);
2458 }
2459
2460 static uint64_t
2461 pci_xhci_xecp_read(struct pci_xhci_softc *sc, uint64_t offset)
2462 {
2463 uint32_t value;
2464
2465 offset -= sc->regsend;
2466 value = 0;
2467
2468 switch (offset) {
2469 case 0:
2470 /* rev major | rev minor | next-cap | cap-id */
2471 value = (0x02 << 24) | (4 << 8) | XHCI_ID_PROTOCOLS;
2472 break;
2473 case 4:
2474 /* name string = "USB" */
2475 value = 0x20425355;
2476 break;
2477 case 8:
2478 /* psic | proto-defined | compat # | compat offset */
2479 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb2_port_start;
2480 break;
2481 case 12:
2482 break;
2483 case 16:
2484 /* rev major | rev minor | next-cap | cap-id */
2485 value = (0x03 << 24) | XHCI_ID_PROTOCOLS;
2486 break;
2487 case 20:
2488 /* name string = "USB" */
2489 value = 0x20425355;
2490 break;
2491 case 24:
2492 /* psic | proto-defined | compat # | compat offset */
2493 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb3_port_start;
2494 break;
2495 case 28:
2496 break;
2497 default:
2498 DPRINTF(("pci_xhci: xecp invalid offset 0x%lx", offset));
2499 break;
2500 }
2501
2502 DPRINTF(("pci_xhci: xecp read offset 0x%lx -> 0x%x",
2503 offset, value));
2504
2505 return (value);
2506 }
2507
2508
2509 static uint64_t
2510 pci_xhci_read(struct vmctx *ctx __unused,
2511 struct pci_devinst *pi, int baridx, uint64_t offset, int size)
2512 {
2513 struct pci_xhci_softc *sc;
2514 uint32_t value;
2515
2516 sc = pi->pi_arg;
2517
2518 assert(baridx == 0);
2519
2520 pthread_mutex_lock(&sc->mtx);
2521 if (offset < XHCI_CAPLEN)
2522 value = pci_xhci_hostcap_read(sc, offset);
2523 else if (offset < sc->dboff)
2524 value = pci_xhci_hostop_read(sc, offset);
2525 else if (offset < sc->rtsoff)
2526 value = pci_xhci_dbregs_read(sc, offset);
2527 else if (offset < sc->regsend)
2528 value = pci_xhci_rtsregs_read(sc, offset);
2529 else if (offset < (sc->regsend + 4*32))
2530 value = pci_xhci_xecp_read(sc, offset);
2531 else {
2532 value = 0;
2533 WPRINTF(("pci_xhci: read invalid offset %ld", offset));
2534 }
2535
2536 pthread_mutex_unlock(&sc->mtx);
2537
2538 switch (size) {
2539 case 1:
2540 value &= 0xFF;
2541 break;
2542 case 2:
2543 value &= 0xFFFF;
2544 break;
2545 case 4:
2546 value &= 0xFFFFFFFF;
2547 break;
2548 }
2549
2550 return (value);
2551 }
2552
2553 static void
2554 pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm)
2555 {
2556 struct pci_xhci_portregs *port;
2557 struct pci_xhci_dev_emu *dev;
2558 struct xhci_trb evtrb;
2559 int error;
2560
2561 assert(portn <= XHCI_MAX_DEVS);
2562
2563 DPRINTF(("xhci reset port %d", portn));
2564
2565 port = XHCI_PORTREG_PTR(sc, portn);
2566 dev = XHCI_DEVINST_PTR(sc, portn);
2567 if (dev) {
2568 port->portsc &= ~(XHCI_PS_PLS_MASK | XHCI_PS_PR | XHCI_PS_PRC);
2569 port->portsc |= XHCI_PS_PED |
2570 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2571
2572 if (warm && dev->dev_ue->ue_usbver == 3) {
2573 port->portsc |= XHCI_PS_WRC;
2574 }
2575
2576 if ((port->portsc & XHCI_PS_PRC) == 0) {
2577 port->portsc |= XHCI_PS_PRC;
2578
2579 pci_xhci_set_evtrb(&evtrb, portn,
2580 XHCI_TRB_ERROR_SUCCESS,
2581 XHCI_TRB_EVENT_PORT_STS_CHANGE);
2582 error = pci_xhci_insert_event(sc, &evtrb, 1);
2583 if (error != XHCI_TRB_ERROR_SUCCESS)
2584 DPRINTF(("xhci reset port insert event "
2585 "failed"));
2586 }
2587 }
2588 }
2589
2590 static void
2591 pci_xhci_init_port(struct pci_xhci_softc *sc, int portn)
2592 {
2593 struct pci_xhci_portregs *port;
2594 struct pci_xhci_dev_emu *dev;
2595
2596 port = XHCI_PORTREG_PTR(sc, portn);
2597 dev = XHCI_DEVINST_PTR(sc, portn);
2598 if (dev) {
2599 port->portsc = XHCI_PS_CCS | /* connected */
2600 XHCI_PS_PP; /* port power */
2601
2602 if (dev->dev_ue->ue_usbver == 2) {
2603 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_POLL) |
2604 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2605 } else {
2606 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_U0) |
2607 XHCI_PS_PED | /* enabled */
2608 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2609 }
2610
2611 DPRINTF(("Init port %d 0x%x", portn, port->portsc));
2612 } else {
2613 port->portsc = XHCI_PS_PLS_SET(UPS_PORT_LS_RX_DET) | XHCI_PS_PP;
2614 DPRINTF(("Init empty port %d 0x%x", portn, port->portsc));
2615 }
2616 }
2617
2618 static int
2619 pci_xhci_dev_intr(struct usb_hci *hci, int epctx)
2620 {
2621 struct pci_xhci_dev_emu *dev;
2622 struct xhci_dev_ctx *dev_ctx;
2623 struct xhci_trb evtrb;
2624 struct pci_xhci_softc *sc;
2625 struct pci_xhci_portregs *p;
2626 struct xhci_endp_ctx *ep_ctx;
2627 int error = 0;
2628 int dir_in;
2629 int epid;
2630
2631 dir_in = epctx & 0x80;
2632 epid = epctx & ~0x80;
2633
2634 /* HW endpoint contexts are 0-15; convert to epid based on dir */
2635 epid = (epid * 2) + (dir_in ? 1 : 0);
2636
2637 assert(epid >= 1 && epid <= 31);
2638
2639 dev = hci->hci_sc;
2640 sc = dev->xsc;
2641
2642 /* check if device is ready; OS has to initialise it */
2643 if (sc->rtsregs.erstba_p == NULL ||
2644 (sc->opregs.usbcmd & XHCI_CMD_RS) == 0 ||
2645 dev->dev_ctx == NULL)
2646 return (0);
2647
2648 p = XHCI_PORTREG_PTR(sc, hci->hci_port);
2649
2650 /* raise event if link U3 (suspended) state */
2651 if (XHCI_PS_PLS_GET(p->portsc) == 3) {
2652 p->portsc &= ~XHCI_PS_PLS_MASK;
2653 p->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_RESUME);
2654 if ((p->portsc & XHCI_PS_PLC) != 0)
2655 return (0);
2656
2657 p->portsc |= XHCI_PS_PLC;
2658
2659 pci_xhci_set_evtrb(&evtrb, hci->hci_port,
2660 XHCI_TRB_ERROR_SUCCESS, XHCI_TRB_EVENT_PORT_STS_CHANGE);
2661 error = pci_xhci_insert_event(sc, &evtrb, 0);
2662 if (error != XHCI_TRB_ERROR_SUCCESS)
2663 goto done;
2664 }
2665
2666 dev_ctx = dev->dev_ctx;
2667 ep_ctx = &dev_ctx->ctx_ep[epid];
2668 if ((ep_ctx->dwEpCtx0 & 0x7) == XHCI_ST_EPCTX_DISABLED) {
2669 DPRINTF(("xhci device interrupt on disabled endpoint %d",
2670 epid));
2671 return (0);
2672 }
2673
2674 DPRINTF(("xhci device interrupt on endpoint %d", epid));
2675
2676 pci_xhci_device_doorbell(sc, hci->hci_port, epid, 0);
2677
2678 done:
2679 return (error);
2680 }
2681
2682 static int
2683 pci_xhci_dev_event(struct usb_hci *hci, enum hci_usbev evid __unused,
2684 void *param __unused)
2685 {
2686 DPRINTF(("xhci device event port %d", hci->hci_port));
2687 return (0);
2688 }
2689
2690 /*
2691 * Each controller contains a "slot" node which contains a list of
2692 * child nodes each of which is a device. Each slot node's name
2693 * corresponds to a specific controller slot. These nodes
2694 * contain a "device" variable identifying the device model of the
2695 * USB device. For example:
2696 *
2697 * pci.0.1.0
2698 * .device="xhci"
2699 * .slot
2700 * .1
2701 * .device="tablet"
2702 */
2703 static int
2704 pci_xhci_legacy_config(nvlist_t *nvl, const char *opts)
2705 {
2706 char node_name[16];
2707 nvlist_t *slots_nvl, *slot_nvl;
2708 char *cp, *opt, *str, *tofree;
2709 int slot;
2710
2711 if (opts == NULL)
2712 return (0);
2713
2714 slots_nvl = create_relative_config_node(nvl, "slot");
2715 slot = 1;
2716 tofree = str = strdup(opts);
2717 while ((opt = strsep(&str, ",")) != NULL) {
2718 /* device[=<config>] */
2719 cp = strchr(opt, '=');
2720 if (cp != NULL) {
2721 *cp = '\0';
2722 cp++;
2723 }
2724
2725 snprintf(node_name, sizeof(node_name), "%d", slot);
2726 slot++;
2727 slot_nvl = create_relative_config_node(slots_nvl, node_name);
2728 set_config_value_node(slot_nvl, "device", opt);
2729
2730 /*
2731 * NB: Given that we split on commas above, the legacy
2732 * format only supports a single option.
2733 */
2734 if (cp != NULL && *cp != '\0')
2735 pci_parse_legacy_config(slot_nvl, cp);
2736 }
2737 free(tofree);
2738 return (0);
2739 }
2740
2741 static int
2742 pci_xhci_parse_devices(struct pci_xhci_softc *sc, nvlist_t *nvl)
2743 {
2744 struct pci_xhci_dev_emu *dev;
2745 struct usb_devemu *ue;
2746 const nvlist_t *slots_nvl, *slot_nvl;
2747 const char *name, *device;
2748 char *cp;
2749 void *devsc, *cookie;
2750 long slot;
2751 int type, usb3_port, usb2_port, i, ndevices;
2752
2753 usb3_port = sc->usb3_port_start;
2754 usb2_port = sc->usb2_port_start;
2755
2756 sc->devices = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_dev_emu *));
2757 sc->slots = calloc(XHCI_MAX_SLOTS, sizeof(struct pci_xhci_dev_emu *));
2758
2759 /* port and slot numbering start from 1 */
2760 sc->devices--;
2761 sc->slots--;
2762
2763 ndevices = 0;
2764
2765 slots_nvl = find_relative_config_node(nvl, "slot");
2766 if (slots_nvl == NULL)
2767 goto portsfinal;
2768
2769 cookie = NULL;
2770 while ((name = nvlist_next(slots_nvl, &type, &cookie)) != NULL) {
2771 if (usb2_port == ((sc->usb2_port_start) + XHCI_MAX_DEVS/2) ||
2772 usb3_port == ((sc->usb3_port_start) + XHCI_MAX_DEVS/2)) {
2773 WPRINTF(("pci_xhci max number of USB 2 or 3 "
2774 "devices reached, max %d", XHCI_MAX_DEVS/2));
2775 goto bad;
2776 }
2777
2778 if (type != NV_TYPE_NVLIST) {
2779 EPRINTLN(
2780 "pci_xhci: config variable '%s' under slot node",
2781 name);
2782 goto bad;
2783 }
2784
2785 slot = strtol(name, &cp, 0);
2786 if (*cp != '\0' || slot <= 0 || slot > XHCI_MAX_SLOTS) {
2787 EPRINTLN("pci_xhci: invalid slot '%s'", name);
2788 goto bad;
2789 }
2790
2791 if (XHCI_SLOTDEV_PTR(sc, slot) != NULL) {
2792 EPRINTLN("pci_xhci: duplicate slot '%s'", name);
2793 goto bad;
2794 }
2795
2796 slot_nvl = nvlist_get_nvlist(slots_nvl, name);
2797 device = get_config_value_node(slot_nvl, "device");
2798 if (device == NULL) {
2799 EPRINTLN(
2800 "pci_xhci: missing \"device\" value for slot '%s'",
2801 name);
2802 goto bad;
2803 }
2804
2805 ue = usb_emu_finddev(device);
2806 if (ue == NULL) {
2807 EPRINTLN("pci_xhci: unknown device model \"%s\"",
2808 device);
2809 goto bad;
2810 }
2811
2812 DPRINTF(("pci_xhci adding device %s", device));
2813
2814 dev = calloc(1, sizeof(struct pci_xhci_dev_emu));
2815 dev->xsc = sc;
2816 dev->hci.hci_sc = dev;
2817 dev->hci.hci_intr = pci_xhci_dev_intr;
2818 dev->hci.hci_event = pci_xhci_dev_event;
2819
2820 if (ue->ue_usbver == 2) {
2821 if (usb2_port == sc->usb2_port_start +
2822 XHCI_MAX_DEVS / 2) {
2823 WPRINTF(("pci_xhci max number of USB 2 devices "
2824 "reached, max %d", XHCI_MAX_DEVS / 2));
2825 goto bad;
2826 }
2827 dev->hci.hci_port = usb2_port;
2828 usb2_port++;
2829 } else {
2830 if (usb3_port == sc->usb3_port_start +
2831 XHCI_MAX_DEVS / 2) {
2832 WPRINTF(("pci_xhci max number of USB 3 devices "
2833 "reached, max %d", XHCI_MAX_DEVS / 2));
2834 goto bad;
2835 }
2836 dev->hci.hci_port = usb3_port;
2837 usb3_port++;
2838 }
2839 XHCI_DEVINST_PTR(sc, dev->hci.hci_port) = dev;
2840
2841 dev->hci.hci_address = 0;
2842 devsc = ue->ue_init(&dev->hci, nvl);
2843 if (devsc == NULL) {
2844 goto bad;
2845 }
2846
2847 dev->dev_ue = ue;
2848 dev->dev_sc = devsc;
2849
2850 XHCI_SLOTDEV_PTR(sc, slot) = dev;
2851 ndevices++;
2852 }
2853
2854 portsfinal:
2855 sc->portregs = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_portregs));
2856 sc->portregs--;
2857
2858 if (ndevices > 0) {
2859 for (i = 1; i <= XHCI_MAX_DEVS; i++) {
2860 pci_xhci_init_port(sc, i);
2861 }
2862 } else {
2863 WPRINTF(("pci_xhci no USB devices configured"));
2864 }
2865 return (0);
2866
2867 bad:
2868 for (i = 1; i <= XHCI_MAX_DEVS; i++) {
2869 free(XHCI_DEVINST_PTR(sc, i));
2870 }
2871
2872 free(sc->devices + 1);
2873 free(sc->slots + 1);
2874
2875 return (-1);
2876 }
2877
2878 static int
2879 pci_xhci_init(struct vmctx *ctx __unused, struct pci_devinst *pi, nvlist_t *nvl)
2880 {
2881 struct pci_xhci_softc *sc;
2882 int error;
2883
2884 #ifndef __FreeBSD__
2885 if (get_config_bool_default("xhci.debug", false))
2886 xhci_debug = 1;
2887 #endif
2888
2889 if (xhci_in_use) {
2890 WPRINTF(("pci_xhci controller already defined"));
2891 return (-1);
2892 }
2893 xhci_in_use = 1;
2894
2895 sc = calloc(1, sizeof(struct pci_xhci_softc));
2896 pi->pi_arg = sc;
2897 sc->xsc_pi = pi;
2898
2899 sc->usb2_port_start = (XHCI_MAX_DEVS/2) + 1;
2900 sc->usb3_port_start = 1;
2901
2902 /* discover devices */
2903 error = pci_xhci_parse_devices(sc, nvl);
2904 if (error < 0)
2905 goto done;
2906 else
2907 error = 0;
2908
2909 sc->caplength = XHCI_SET_CAPLEN(XHCI_CAPLEN) |
2910 XHCI_SET_HCIVERSION(0x0100);
2911 sc->hcsparams1 = XHCI_SET_HCSP1_MAXPORTS(XHCI_MAX_DEVS) |
2912 XHCI_SET_HCSP1_MAXINTR(1) | /* interrupters */
2913 XHCI_SET_HCSP1_MAXSLOTS(XHCI_MAX_SLOTS);
2914 sc->hcsparams2 = XHCI_SET_HCSP2_ERSTMAX(XHCI_ERST_MAX) |
2915 XHCI_SET_HCSP2_IST(0x04);
2916 sc->hcsparams3 = 0; /* no latency */
2917 sc->hccparams1 = XHCI_SET_HCCP1_AC64(1) | /* 64-bit addrs */
2918 XHCI_SET_HCCP1_NSS(1) | /* no 2nd-streams */
2919 XHCI_SET_HCCP1_SPC(1) | /* short packet */
2920 XHCI_SET_HCCP1_MAXPSA(XHCI_STREAMS_MAX);
2921 sc->hccparams2 = XHCI_SET_HCCP2_LEC(1) |
2922 XHCI_SET_HCCP2_U3C(1);
2923 sc->dboff = XHCI_SET_DOORBELL(XHCI_CAPLEN + XHCI_PORTREGS_START +
2924 XHCI_MAX_DEVS * sizeof(struct pci_xhci_portregs));
2925
2926 /* dboff must be 32-bit aligned */
2927 if (sc->dboff & 0x3)
2928 sc->dboff = (sc->dboff + 0x3) & ~0x3;
2929
2930 /* rtsoff must be 32-bytes aligned */
2931 sc->rtsoff = XHCI_SET_RTSOFFSET(sc->dboff + (XHCI_MAX_SLOTS+1) * 32);
2932 if (sc->rtsoff & 0x1F)
2933 sc->rtsoff = (sc->rtsoff + 0x1F) & ~0x1F;
2934
2935 DPRINTF(("pci_xhci dboff: 0x%x, rtsoff: 0x%x", sc->dboff,
2936 sc->rtsoff));
2937
2938 sc->opregs.usbsts = XHCI_STS_HCH;
2939 sc->opregs.pgsz = XHCI_PAGESIZE_4K;
2940
2941 pci_xhci_reset(sc);
2942
2943 sc->regsend = sc->rtsoff + 0x20 + 32; /* only 1 intrpter */
2944
2945 /*
2946 * Set extended capabilities pointer to be after regsend;
2947 * value of xecp field is 32-bit offset.
2948 */
2949 sc->hccparams1 |= XHCI_SET_HCCP1_XECP(sc->regsend/4);
2950
2951 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x1E31);
2952 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2953 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SERIALBUS);
2954 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_SERIALBUS_USB);
2955 pci_set_cfgdata8(pi, PCIR_PROGIF,PCIP_SERIALBUS_USB_XHCI);
2956 pci_set_cfgdata8(pi, PCI_USBREV, PCI_USB_REV_3_0);
2957
2958 pci_emul_add_msicap(pi, 1);
2959
2960 /* regsend + xecp registers */
2961 pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, sc->regsend + 4*32);
2962 DPRINTF(("pci_xhci pci_emu_alloc: %d", sc->regsend + 4*32));
2963
2964
2965 pci_lintr_request(pi);
2966
2967 pthread_mutex_init(&sc->mtx, NULL);
2968
2969 done:
2970 if (error) {
2971 free(sc);
2972 }
2973
2974 return (error);
2975 }
2976
2977 static const struct pci_devemu pci_de_xhci = {
2978 .pe_emu = "xhci",
2979 .pe_init = pci_xhci_init,
2980 .pe_legacy_config = pci_xhci_legacy_config,
2981 .pe_barwrite = pci_xhci_write,
2982 .pe_barread = pci_xhci_read
2983 };
2984 PCI_EMUL_SET(pci_de_xhci);
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