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15325 bhyve upstream sync 2023 January
[illumos-gate.git] / usr / src / cmd / bhyve / pci_ahci.c
blobe66945655aefe08ee7e51ac5c11e9354bf246529
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 #include <sys/param.h>
36 #include <sys/linker_set.h>
37 #include <sys/stat.h>
38 #include <sys/uio.h>
39 #include <sys/ioctl.h>
40 #include <sys/disk.h>
41 #include <sys/ata.h>
42 #include <sys/endian.h>
43
44 #include <errno.h>
45 #include <fcntl.h>
46 #include <stdio.h>
47 #include <stdlib.h>
48 #include <stdint.h>
49 #include <string.h>
50 #include <strings.h>
51 #include <unistd.h>
52 #include <assert.h>
53 #include <pthread.h>
54 #include <pthread_np.h>
55 #include <inttypes.h>
56 #include <md5.h>
57
58 #include "bhyverun.h"
59 #include "config.h"
60 #include "debug.h"
61 #include "pci_emul.h"
62 #include "ahci.h"
63 #include "block_if.h"
64
65 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
66 #define MAX_PORTS 32 /* AHCI supports 32 ports */
67
68 #define PxSIG_ATA 0x00000101 /* ATA drive */
69 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
70
71 enum sata_fis_type {
72 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
73 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
74 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
75 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
76 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
77 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
78 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
79 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
80 };
81
82 /*
83 * SCSI opcodes
84 */
85 #define TEST_UNIT_READY 0x00
86 #define REQUEST_SENSE 0x03
87 #define INQUIRY 0x12
88 #define START_STOP_UNIT 0x1B
89 #define PREVENT_ALLOW 0x1E
90 #define READ_CAPACITY 0x25
91 #define READ_10 0x28
92 #define POSITION_TO_ELEMENT 0x2B
93 #define READ_TOC 0x43
94 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
95 #define MODE_SENSE_10 0x5A
96 #define REPORT_LUNS 0xA0
97 #define READ_12 0xA8
98 #define READ_CD 0xBE
99
100 /*
101 * SCSI mode page codes
102 */
103 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
104 #define MODEPAGE_CD_CAPABILITIES 0x2A
105
106 /*
107 * ATA commands
108 */
109 #define ATA_SF_ENAB_SATA_SF 0x10
110 #define ATA_SATA_SF_AN 0x05
111 #define ATA_SF_DIS_SATA_SF 0x90
112
113 /*
114 * Debug printf
115 */
116 #ifdef AHCI_DEBUG
117 static FILE *dbg;
118 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
119 #else
120 #define DPRINTF(format, arg...)
121 #endif
122 #define WPRINTF(format, arg...) printf(format, ##arg)
123
124 #define AHCI_PORT_IDENT 20 + 1
125
126 struct ahci_ioreq {
127 struct blockif_req io_req;
128 struct ahci_port *io_pr;
129 STAILQ_ENTRY(ahci_ioreq) io_flist;
130 TAILQ_ENTRY(ahci_ioreq) io_blist;
131 uint8_t *cfis;
132 uint32_t len;
133 uint32_t done;
134 int slot;
135 int more;
136 };
137
138 struct ahci_port {
139 struct blockif_ctxt *bctx;
140 struct pci_ahci_softc *pr_sc;
141 struct ata_params ata_ident;
142 uint8_t *cmd_lst;
143 uint8_t *rfis;
144 int port;
145 int atapi;
146 int reset;
147 int waitforclear;
148 int mult_sectors;
149 uint8_t xfermode;
150 uint8_t err_cfis[20];
151 uint8_t sense_key;
152 uint8_t asc;
153 u_int ccs;
154 uint32_t pending;
155
156 uint32_t clb;
157 uint32_t clbu;
158 uint32_t fb;
159 uint32_t fbu;
160 uint32_t is;
161 uint32_t ie;
162 uint32_t cmd;
163 uint32_t unused0;
164 uint32_t tfd;
165 uint32_t sig;
166 uint32_t ssts;
167 uint32_t sctl;
168 uint32_t serr;
169 uint32_t sact;
170 uint32_t ci;
171 uint32_t sntf;
172 uint32_t fbs;
173
174 /*
175 * i/o request info
176 */
177 struct ahci_ioreq *ioreq;
178 int ioqsz;
179 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
180 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
181 };
182
183 struct ahci_cmd_hdr {
184 uint16_t flags;
185 uint16_t prdtl;
186 uint32_t prdbc;
187 uint64_t ctba;
188 uint32_t reserved[4];
189 };
190
191 struct ahci_prdt_entry {
192 uint64_t dba;
193 uint32_t reserved;
194 #define DBCMASK 0x3fffff
195 uint32_t dbc;
196 };
197
198 struct pci_ahci_softc {
199 struct pci_devinst *asc_pi;
200 pthread_mutex_t mtx;
201 int ports;
202 uint32_t cap;
203 uint32_t ghc;
204 uint32_t is;
205 uint32_t pi;
206 uint32_t vs;
207 uint32_t ccc_ctl;
208 uint32_t ccc_pts;
209 uint32_t em_loc;
210 uint32_t em_ctl;
211 uint32_t cap2;
212 uint32_t bohc;
213 uint32_t lintr;
214 struct ahci_port port[MAX_PORTS];
215 };
216 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
217
218 static void ahci_handle_port(struct ahci_port *p);
219
220 static inline void lba_to_msf(uint8_t *buf, int lba)
221 {
222 lba += 150;
223 buf[0] = (lba / 75) / 60;
224 buf[1] = (lba / 75) % 60;
225 buf[2] = lba % 75;
226 }
227
228 /*
229 * Generate HBA interrupts on global IS register write.
230 */
231 static void
232 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask)
233 {
234 struct pci_devinst *pi = sc->asc_pi;
235 struct ahci_port *p;
236 int i, nmsg;
237 uint32_t mmask;
238
239 /* Update global IS from PxIS/PxIE. */
240 for (i = 0; i < sc->ports; i++) {
241 p = &sc->port[i];
242 if (p->is & p->ie)
243 sc->is |= (1 << i);
244 }
245 DPRINTF("%s(%08x) %08x", __func__, mask, sc->is);
246
247 /* If there is nothing enabled -- clear legacy interrupt and exit. */
248 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) {
249 if (sc->lintr) {
250 pci_lintr_deassert(pi);
251 sc->lintr = 0;
252 }
253 return;
254 }
255
256 /* If there is anything and no MSI -- assert legacy interrupt. */
257 nmsg = pci_msi_maxmsgnum(pi);
258 if (nmsg == 0) {
259 if (!sc->lintr) {
260 sc->lintr = 1;
261 pci_lintr_assert(pi);
262 }
263 return;
264 }
265
266 /* Assert respective MSIs for ports that were touched. */
267 for (i = 0; i < nmsg; i++) {
268 if (sc->ports <= nmsg || i < nmsg - 1)
269 mmask = 1 << i;
270 else
271 mmask = 0xffffffff << i;
272 if (sc->is & mask && mmask & mask)
273 pci_generate_msi(pi, i);
274 }
275 }
276
277 /*
278 * Generate HBA interrupt on specific port event.
279 */
280 static void
281 ahci_port_intr(struct ahci_port *p)
282 {
283 struct pci_ahci_softc *sc = p->pr_sc;
284 struct pci_devinst *pi = sc->asc_pi;
285 int nmsg;
286
287 DPRINTF("%s(%d) %08x/%08x %08x", __func__,
288 p->port, p->is, p->ie, sc->is);
289
290 /* If there is nothing enabled -- we are done. */
291 if ((p->is & p->ie) == 0)
292 return;
293
294 /* In case of non-shared MSI always generate interrupt. */
295 nmsg = pci_msi_maxmsgnum(pi);
296 if (sc->ports <= nmsg || p->port < nmsg - 1) {
297 sc->is |= (1 << p->port);
298 if ((sc->ghc & AHCI_GHC_IE) == 0)
299 return;
300 pci_generate_msi(pi, p->port);
301 return;
302 }
303
304 /* If IS for this port is already set -- do nothing. */
305 if (sc->is & (1 << p->port))
306 return;
307
308 sc->is |= (1 << p->port);
309
310 /* If interrupts are enabled -- generate one. */
311 if ((sc->ghc & AHCI_GHC_IE) == 0)
312 return;
313 if (nmsg > 0) {
314 pci_generate_msi(pi, nmsg - 1);
315 } else if (!sc->lintr) {
316 sc->lintr = 1;
317 pci_lintr_assert(pi);
318 }
319 }
320
321 static void
322 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
323 {
324 int offset, len, irq;
325
326 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
327 return;
328
329 switch (ft) {
330 case FIS_TYPE_REGD2H:
331 offset = 0x40;
332 len = 20;
333 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0;
334 break;
335 case FIS_TYPE_SETDEVBITS:
336 offset = 0x58;
337 len = 8;
338 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0;
339 break;
340 case FIS_TYPE_PIOSETUP:
341 offset = 0x20;
342 len = 20;
343 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
344 break;
345 default:
346 WPRINTF("unsupported fis type %d", ft);
347 return;
348 }
349 if (fis[2] & ATA_S_ERROR) {
350 p->waitforclear = 1;
351 irq |= AHCI_P_IX_TFE;
352 }
353 memcpy(p->rfis + offset, fis, len);
354 if (irq) {
355 if (~p->is & irq) {
356 p->is |= irq;
357 ahci_port_intr(p);
358 }
359 }
360 }
361
362 static void
363 ahci_write_fis_piosetup(struct ahci_port *p)
364 {
365 uint8_t fis[20];
366
367 memset(fis, 0, sizeof(fis));
368 fis[0] = FIS_TYPE_PIOSETUP;
369 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
370 }
371
372 static void
373 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
374 {
375 uint8_t fis[8];
376 uint8_t error;
377
378 error = (tfd >> 8) & 0xff;
379 tfd &= 0x77;
380 memset(fis, 0, sizeof(fis));
381 fis[0] = FIS_TYPE_SETDEVBITS;
382 fis[1] = (1 << 6);
383 fis[2] = tfd;
384 fis[3] = error;
385 if (fis[2] & ATA_S_ERROR) {
386 p->err_cfis[0] = slot;
387 p->err_cfis[2] = tfd;
388 p->err_cfis[3] = error;
389 memcpy(&p->err_cfis[4], cfis + 4, 16);
390 } else {
391 *(uint32_t *)(fis + 4) = (1 << slot);
392 p->sact &= ~(1 << slot);
393 }
394 p->tfd &= ~0x77;
395 p->tfd |= tfd;
396 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
397 }
398
399 static void
400 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
401 {
402 uint8_t fis[20];
403 uint8_t error;
404
405 error = (tfd >> 8) & 0xff;
406 memset(fis, 0, sizeof(fis));
407 fis[0] = FIS_TYPE_REGD2H;
408 fis[1] = (1 << 6);
409 fis[2] = tfd & 0xff;
410 fis[3] = error;
411 fis[4] = cfis[4];
412 fis[5] = cfis[5];
413 fis[6] = cfis[6];
414 fis[7] = cfis[7];
415 fis[8] = cfis[8];
416 fis[9] = cfis[9];
417 fis[10] = cfis[10];
418 fis[11] = cfis[11];
419 fis[12] = cfis[12];
420 fis[13] = cfis[13];
421 if (fis[2] & ATA_S_ERROR) {
422 p->err_cfis[0] = 0x80;
423 p->err_cfis[2] = tfd & 0xff;
424 p->err_cfis[3] = error;
425 memcpy(&p->err_cfis[4], cfis + 4, 16);
426 } else
427 p->ci &= ~(1 << slot);
428 p->tfd = tfd;
429 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
430 }
431
432 static void
433 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot)
434 {
435 uint8_t fis[20];
436
437 p->tfd = ATA_S_READY | ATA_S_DSC;
438 memset(fis, 0, sizeof(fis));
439 fis[0] = FIS_TYPE_REGD2H;
440 fis[1] = 0; /* No interrupt */
441 fis[2] = p->tfd; /* Status */
442 fis[3] = 0; /* No error */
443 p->ci &= ~(1 << slot);
444 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
445 }
446
447 static void
448 ahci_write_reset_fis_d2h(struct ahci_port *p)
449 {
450 uint8_t fis[20];
451
452 memset(fis, 0, sizeof(fis));
453 fis[0] = FIS_TYPE_REGD2H;
454 fis[3] = 1;
455 fis[4] = 1;
456 if (p->atapi) {
457 fis[5] = 0x14;
458 fis[6] = 0xeb;
459 }
460 fis[12] = 1;
461 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
462 }
463
464 static void
465 ahci_check_stopped(struct ahci_port *p)
466 {
467 /*
468 * If we are no longer processing the command list and nothing
469 * is in-flight, clear the running bit, the current command
470 * slot, the command issue and active bits.
471 */
472 if (!(p->cmd & AHCI_P_CMD_ST)) {
473 if (p->pending == 0) {
474 p->ccs = 0;
475 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
476 p->ci = 0;
477 p->sact = 0;
478 p->waitforclear = 0;
479 }
480 }
481 }
482
483 static void
484 ahci_port_stop(struct ahci_port *p)
485 {
486 struct ahci_ioreq *aior;
487 uint8_t *cfis;
488 int slot;
489 int error;
490
491 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
492
493 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
494 /*
495 * Try to cancel the outstanding blockif request.
496 */
497 error = blockif_cancel(p->bctx, &aior->io_req);
498 if (error != 0)
499 continue;
500
501 slot = aior->slot;
502 cfis = aior->cfis;
503 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
504 cfis[2] == ATA_READ_FPDMA_QUEUED ||
505 cfis[2] == ATA_SEND_FPDMA_QUEUED)
506 p->sact &= ~(1 << slot); /* NCQ */
507 else
508 p->ci &= ~(1 << slot);
509
510 /*
511 * This command is now done.
512 */
513 p->pending &= ~(1 << slot);
514
515 /*
516 * Delete the blockif request from the busy list
517 */
518 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
519
520 /*
521 * Move the blockif request back to the free list
522 */
523 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
524 }
525
526 ahci_check_stopped(p);
527 }
528
529 static void
530 ahci_port_reset(struct ahci_port *pr)
531 {
532 pr->serr = 0;
533 pr->sact = 0;
534 pr->xfermode = ATA_UDMA6;
535 pr->mult_sectors = 128;
536
537 if (!pr->bctx) {
538 pr->ssts = ATA_SS_DET_NO_DEVICE;
539 pr->sig = 0xFFFFFFFF;
540 pr->tfd = 0x7F;
541 return;
542 }
543 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
544 if (pr->sctl & ATA_SC_SPD_MASK)
545 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
546 else
547 pr->ssts |= ATA_SS_SPD_GEN3;
548 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
549 if (!pr->atapi) {
550 pr->sig = PxSIG_ATA;
551 pr->tfd |= ATA_S_READY;
552 } else
553 pr->sig = PxSIG_ATAPI;
554 ahci_write_reset_fis_d2h(pr);
555 }
556
557 static void
558 ahci_reset(struct pci_ahci_softc *sc)
559 {
560 int i;
561
562 sc->ghc = AHCI_GHC_AE;
563 sc->is = 0;
564
565 if (sc->lintr) {
566 pci_lintr_deassert(sc->asc_pi);
567 sc->lintr = 0;
568 }
569
570 for (i = 0; i < sc->ports; i++) {
571 sc->port[i].ie = 0;
572 sc->port[i].is = 0;
573 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD);
574 if (sc->port[i].bctx)
575 sc->port[i].cmd |= AHCI_P_CMD_CPS;
576 sc->port[i].sctl = 0;
577 ahci_port_reset(&sc->port[i]);
578 }
579 }
580
581 static void
582 ata_string(uint8_t *dest, const char *src, int len)
583 {
584 int i;
585
586 for (i = 0; i < len; i++) {
587 if (*src)
588 dest[i ^ 1] = *src++;
589 else
590 dest[i ^ 1] = ' ';
591 }
592 }
593
594 static void
595 atapi_string(uint8_t *dest, const char *src, int len)
596 {
597 int i;
598
599 for (i = 0; i < len; i++) {
600 if (*src)
601 dest[i] = *src++;
602 else
603 dest[i] = ' ';
604 }
605 }
606
607 /*
608 * Build up the iovec based on the PRDT, 'done' and 'len'.
609 */
610 static void
611 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior,
612 struct ahci_prdt_entry *prdt, uint16_t prdtl)
613 {
614 struct blockif_req *breq = &aior->io_req;
615 uint32_t dbcsz, extra, left, skip, todo;
616 int i, j;
617
618 assert(aior->len >= aior->done);
619
620 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */
621 skip = aior->done;
622 left = aior->len - aior->done;
623 todo = 0;
624 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0;
625 i++, prdt++) {
626 dbcsz = (prdt->dbc & DBCMASK) + 1;
627 /* Skip already done part of the PRDT */
628 if (dbcsz <= skip) {
629 skip -= dbcsz;
630 continue;
631 }
632 dbcsz -= skip;
633 if (dbcsz > left)
634 dbcsz = left;
635 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc),
636 prdt->dba + skip, dbcsz);
637 breq->br_iov[j].iov_len = dbcsz;
638 todo += dbcsz;
639 left -= dbcsz;
640 skip = 0;
641 j++;
642 }
643
644 /* If we got limited by IOV length, round I/O down to sector size. */
645 if (j == BLOCKIF_IOV_MAX) {
646 extra = todo % blockif_sectsz(p->bctx);
647 todo -= extra;
648 assert(todo > 0);
649 while (extra > 0) {
650 if (breq->br_iov[j - 1].iov_len > extra) {
651 breq->br_iov[j - 1].iov_len -= extra;
652 break;
653 }
654 extra -= breq->br_iov[j - 1].iov_len;
655 j--;
656 }
657 }
658
659 breq->br_iovcnt = j;
660 breq->br_resid = todo;
661 aior->done += todo;
662 aior->more = (aior->done < aior->len && i < prdtl);
663 }
664
665 static void
666 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
667 {
668 struct ahci_ioreq *aior;
669 struct blockif_req *breq;
670 struct ahci_prdt_entry *prdt;
671 struct ahci_cmd_hdr *hdr;
672 uint64_t lba;
673 uint32_t len;
674 int err, first, ncq, readop;
675
676 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
677 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
678 ncq = 0;
679 readop = 1;
680 first = (done == 0);
681
682 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
683 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
684 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
685 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
686 readop = 0;
687
688 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
689 cfis[2] == ATA_READ_FPDMA_QUEUED) {
690 lba = ((uint64_t)cfis[10] << 40) |
691 ((uint64_t)cfis[9] << 32) |
692 ((uint64_t)cfis[8] << 24) |
693 ((uint64_t)cfis[6] << 16) |
694 ((uint64_t)cfis[5] << 8) |
695 cfis[4];
696 len = cfis[11] << 8 | cfis[3];
697 if (!len)
698 len = 65536;
699 ncq = 1;
700 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
701 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
702 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
703 lba = ((uint64_t)cfis[10] << 40) |
704 ((uint64_t)cfis[9] << 32) |
705 ((uint64_t)cfis[8] << 24) |
706 ((uint64_t)cfis[6] << 16) |
707 ((uint64_t)cfis[5] << 8) |
708 cfis[4];
709 len = cfis[13] << 8 | cfis[12];
710 if (!len)
711 len = 65536;
712 } else {
713 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
714 (cfis[5] << 8) | cfis[4];
715 len = cfis[12];
716 if (!len)
717 len = 256;
718 }
719 lba *= blockif_sectsz(p->bctx);
720 len *= blockif_sectsz(p->bctx);
721
722 /* Pull request off free list */
723 aior = STAILQ_FIRST(&p->iofhd);
724 assert(aior != NULL);
725 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
726
727 aior->cfis = cfis;
728 aior->slot = slot;
729 aior->len = len;
730 aior->done = done;
731 breq = &aior->io_req;
732 breq->br_offset = lba + done;
733 ahci_build_iov(p, aior, prdt, hdr->prdtl);
734
735 /* Mark this command in-flight. */
736 p->pending |= 1 << slot;
737
738 /* Stuff request onto busy list. */
739 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
740
741 if (ncq && first)
742 ahci_write_fis_d2h_ncq(p, slot);
743
744 if (readop)
745 err = blockif_read(p->bctx, breq);
746 else
747 err = blockif_write(p->bctx, breq);
748 assert(err == 0);
749 }
750
751 static void
752 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
753 {
754 struct ahci_ioreq *aior;
755 struct blockif_req *breq;
756 int err;
757
758 /*
759 * Pull request off free list
760 */
761 aior = STAILQ_FIRST(&p->iofhd);
762 assert(aior != NULL);
763 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
764 aior->cfis = cfis;
765 aior->slot = slot;
766 aior->len = 0;
767 aior->done = 0;
768 aior->more = 0;
769 breq = &aior->io_req;
770
771 /*
772 * Mark this command in-flight.
773 */
774 p->pending |= 1 << slot;
775
776 /*
777 * Stuff request onto busy list
778 */
779 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
780
781 err = blockif_flush(p->bctx, breq);
782 assert(err == 0);
783 }
784
785 static inline void
786 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf,
787 unsigned int size)
788 {
789 struct ahci_cmd_hdr *hdr;
790 struct ahci_prdt_entry *prdt;
791 uint8_t *to;
792 unsigned int len;
793 int i;
794
795 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
796 len = size;
797 to = buf;
798 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
799 for (i = 0; i < hdr->prdtl && len; i++) {
800 uint8_t *ptr;
801 uint32_t dbcsz;
802 unsigned int sublen;
803
804 dbcsz = (prdt->dbc & DBCMASK) + 1;
805 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
806 sublen = MIN(len, dbcsz);
807 memcpy(to, ptr, sublen);
808 len -= sublen;
809 to += sublen;
810 prdt++;
811 }
812 }
813
814 static void
815 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
816 {
817 struct ahci_ioreq *aior;
818 struct blockif_req *breq;
819 uint8_t *entry;
820 uint64_t elba;
821 uint32_t len, elen;
822 int err, first, ncq;
823 uint8_t buf[512];
824
825 first = (done == 0);
826 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
827 len = (uint16_t)cfis[13] << 8 | cfis[12];
828 len *= 512;
829 ncq = 0;
830 } else { /* ATA_SEND_FPDMA_QUEUED */
831 len = (uint16_t)cfis[11] << 8 | cfis[3];
832 len *= 512;
833 ncq = 1;
834 }
835 read_prdt(p, slot, cfis, buf, sizeof(buf));
836
837 next:
838 entry = &buf[done];
839 elba = ((uint64_t)entry[5] << 40) |
840 ((uint64_t)entry[4] << 32) |
841 ((uint64_t)entry[3] << 24) |
842 ((uint64_t)entry[2] << 16) |
843 ((uint64_t)entry[1] << 8) |
844 entry[0];
845 elen = (uint16_t)entry[7] << 8 | entry[6];
846 done += 8;
847 if (elen == 0) {
848 if (done >= len) {
849 if (ncq) {
850 if (first)
851 ahci_write_fis_d2h_ncq(p, slot);
852 ahci_write_fis_sdb(p, slot, cfis,
853 ATA_S_READY | ATA_S_DSC);
854 } else {
855 ahci_write_fis_d2h(p, slot, cfis,
856 ATA_S_READY | ATA_S_DSC);
857 }
858 p->pending &= ~(1 << slot);
859 ahci_check_stopped(p);
860 if (!first)
861 ahci_handle_port(p);
862 return;
863 }
864 goto next;
865 }
866
867 /*
868 * Pull request off free list
869 */
870 aior = STAILQ_FIRST(&p->iofhd);
871 assert(aior != NULL);
872 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
873 aior->cfis = cfis;
874 aior->slot = slot;
875 aior->len = len;
876 aior->done = done;
877 aior->more = (len != done);
878
879 breq = &aior->io_req;
880 breq->br_offset = elba * blockif_sectsz(p->bctx);
881 breq->br_resid = elen * blockif_sectsz(p->bctx);
882
883 /*
884 * Mark this command in-flight.
885 */
886 p->pending |= 1 << slot;
887
888 /*
889 * Stuff request onto busy list
890 */
891 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
892
893 if (ncq && first)
894 ahci_write_fis_d2h_ncq(p, slot);
895
896 err = blockif_delete(p->bctx, breq);
897 assert(err == 0);
898 }
899
900 static inline void
901 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf,
902 unsigned int size)
903 {
904 struct ahci_cmd_hdr *hdr;
905 struct ahci_prdt_entry *prdt;
906 uint8_t *from;
907 unsigned int len;
908 int i;
909
910 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
911 len = size;
912 from = buf;
913 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
914 for (i = 0; i < hdr->prdtl && len; i++) {
915 uint8_t *ptr;
916 uint32_t dbcsz;
917 int sublen;
918
919 dbcsz = (prdt->dbc & DBCMASK) + 1;
920 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
921 sublen = MIN(len, dbcsz);
922 memcpy(ptr, from, sublen);
923 len -= sublen;
924 from += sublen;
925 prdt++;
926 }
927 hdr->prdbc = size - len;
928 }
929
930 static void
931 ahci_checksum(uint8_t *buf, int size)
932 {
933 int i;
934 uint8_t sum = 0;
935
936 for (i = 0; i < size - 1; i++)
937 sum += buf[i];
938 buf[size - 1] = 0x100 - sum;
939 }
940
941 static void
942 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
943 {
944 struct ahci_cmd_hdr *hdr;
945 uint32_t buf[128];
946 uint8_t *buf8 = (uint8_t *)buf;
947 uint16_t *buf16 = (uint16_t *)buf;
948
949 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
950 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 ||
951 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
952 ahci_write_fis_d2h(p, slot, cfis,
953 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
954 return;
955 }
956
957 memset(buf, 0, sizeof(buf));
958 if (cfis[4] == 0x00) { /* Log directory */
959 buf16[0x00] = 1; /* Version -- 1 */
960 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */
961 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */
962 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */
963 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis));
964 ahci_checksum(buf8, sizeof(buf));
965 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */
966 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) {
967 buf[0x00] = 1; /* SFQ DSM supported */
968 buf[0x01] = 1; /* SFQ DSM TRIM supported */
969 }
970 } else {
971 ahci_write_fis_d2h(p, slot, cfis,
972 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
973 return;
974 }
975
976 if (cfis[2] == ATA_READ_LOG_EXT)
977 ahci_write_fis_piosetup(p);
978 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
979 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
980 }
981
982 static void
983 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
984 {
985 struct ahci_cmd_hdr *hdr;
986
987 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
988 if (p->atapi || hdr->prdtl == 0) {
989 ahci_write_fis_d2h(p, slot, cfis,
990 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
991 } else {
992 ahci_write_fis_piosetup(p);
993 write_prdt(p, slot, cfis, (void*)&p->ata_ident, sizeof(struct ata_params));
994 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
995 }
996 }
997
998 static void
999 ata_identify_init(struct ahci_port* p, int atapi)
1000 {
1001 struct ata_params* ata_ident = &p->ata_ident;
1002
1003 if (atapi) {
1004 ata_ident->config = ATA_PROTO_ATAPI | ATA_ATAPI_TYPE_CDROM |
1005 ATA_ATAPI_REMOVABLE | ATA_DRQ_FAST;
1006 ata_ident->capabilities1 = ATA_SUPPORT_LBA |
1007 ATA_SUPPORT_DMA;
1008 ata_ident->capabilities2 = (1 << 14 | 1);
1009 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1010 ata_ident->obsolete62 = 0x3f;
1011 ata_ident->mwdmamodes = 7;
1012 if (p->xfermode & ATA_WDMA0)
1013 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1014 ata_ident->apiomodes = 3;
1015 ata_ident->mwdmamin = 0x0078;
1016 ata_ident->mwdmarec = 0x0078;
1017 ata_ident->pioblind = 0x0078;
1018 ata_ident->pioiordy = 0x0078;
1019 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
1020 ata_ident->satacapabilities2 = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
1021 ata_ident->satasupport = ATA_SUPPORT_NCQ_STREAM;
1022 ata_ident->version_major = 0x3f0;
1023 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1024 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1025 ata_ident->support.command2 = (1 << 14);
1026 ata_ident->support.extension = (1 << 14);
1027 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1028 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1029 ata_ident->enabled.extension = (1 << 14);
1030 ata_ident->udmamodes = 0x7f;
1031 if (p->xfermode & ATA_UDMA0)
1032 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1033 ata_ident->transport_major = 0x1020;
1034 ata_ident->integrity = 0x00a5;
1035 } else {
1036 uint64_t sectors;
1037 int sectsz, psectsz, psectoff, candelete, ro;
1038 uint16_t cyl;
1039 uint8_t sech, heads;
1040
1041 ro = blockif_is_ro(p->bctx);
1042 candelete = blockif_candelete(p->bctx);
1043 sectsz = blockif_sectsz(p->bctx);
1044 sectors = blockif_size(p->bctx) / sectsz;
1045 blockif_chs(p->bctx, &cyl, &heads, &sech);
1046 blockif_psectsz(p->bctx, &psectsz, &psectoff);
1047 ata_ident->config = ATA_DRQ_FAST;
1048 ata_ident->cylinders = cyl;
1049 ata_ident->heads = heads;
1050 ata_ident->sectors = sech;
1051
1052 ata_ident->sectors_intr = (0x8000 | 128);
1053 ata_ident->tcg = 0;
1054
1055 ata_ident->capabilities1 = ATA_SUPPORT_DMA |
1056 ATA_SUPPORT_LBA | ATA_SUPPORT_IORDY;
1057 ata_ident->capabilities2 = (1 << 14);
1058 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1059 if (p->mult_sectors)
1060 ata_ident->multi = (ATA_MULTI_VALID | p->mult_sectors);
1061 if (sectors <= 0x0fffffff) {
1062 ata_ident->lba_size_1 = sectors;
1063 ata_ident->lba_size_2 = (sectors >> 16);
1064 } else {
1065 ata_ident->lba_size_1 = 0xffff;
1066 ata_ident->lba_size_2 = 0x0fff;
1067 }
1068 ata_ident->mwdmamodes = 0x7;
1069 if (p->xfermode & ATA_WDMA0)
1070 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1071 ata_ident->apiomodes = 0x3;
1072 ata_ident->mwdmamin = 0x0078;
1073 ata_ident->mwdmarec = 0x0078;
1074 ata_ident->pioblind = 0x0078;
1075 ata_ident->pioiordy = 0x0078;
1076 ata_ident->support3 = 0;
1077 ata_ident->queue = 31;
1078 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
1079 ATA_SUPPORT_NCQ);
1080 ata_ident->satacapabilities2 = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
1081 (p->ssts & ATA_SS_SPD_MASK) >> 3);
1082 ata_ident->version_major = 0x3f0;
1083 ata_ident->version_minor = 0x28;
1084 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1085 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1086 ata_ident->support.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1087 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
1088 ata_ident->support.extension = (1 << 14);
1089 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1090 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1091 ata_ident->enabled.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1092 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
1093 ata_ident->enabled.extension = (1 << 14);
1094 ata_ident->udmamodes = 0x7f;
1095 if (p->xfermode & ATA_UDMA0)
1096 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1097 ata_ident->lba_size48_1 = sectors;
1098 ata_ident->lba_size48_2 = (sectors >> 16);
1099 ata_ident->lba_size48_3 = (sectors >> 32);
1100 ata_ident->lba_size48_4 = (sectors >> 48);
1101
1102 if (candelete && !ro) {
1103 ata_ident->support3 |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
1104 ata_ident->max_dsm_blocks = 1;
1105 ata_ident->support_dsm = ATA_SUPPORT_DSM_TRIM;
1106 }
1107 ata_ident->pss = ATA_PSS_VALID_VALUE;
1108 ata_ident->lsalign = 0x4000;
1109 if (psectsz > sectsz) {
1110 ata_ident->pss |= ATA_PSS_MULTLS;
1111 ata_ident->pss |= ffsl(psectsz / sectsz) - 1;
1112 ata_ident->lsalign |= (psectoff / sectsz);
1113 }
1114 if (sectsz > 512) {
1115 ata_ident->pss |= ATA_PSS_LSSABOVE512;
1116 ata_ident->lss_1 = sectsz / 2;
1117 ata_ident->lss_2 = ((sectsz / 2) >> 16);
1118 }
1119 ata_ident->support2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1120 ata_ident->enabled2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1121 ata_ident->transport_major = 0x1020;
1122 ata_ident->integrity = 0x00a5;
1123 }
1124 ahci_checksum((uint8_t*)ata_ident, sizeof(struct ata_params));
1125 }
1126
1127 static void
1128 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1129 {
1130 if (!p->atapi) {
1131 ahci_write_fis_d2h(p, slot, cfis,
1132 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1133 } else {
1134 ahci_write_fis_piosetup(p);
1135 write_prdt(p, slot, cfis, (void *)&p->ata_ident, sizeof(struct ata_params));
1136 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1137 }
1138 }
1139
1140 static void
1141 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
1142 {
1143 uint8_t buf[36];
1144 uint8_t *acmd;
1145 unsigned int len;
1146 uint32_t tfd;
1147
1148 acmd = cfis + 0x40;
1149
1150 if (acmd[1] & 1) { /* VPD */
1151 if (acmd[2] == 0) { /* Supported VPD pages */
1152 buf[0] = 0x05;
1153 buf[1] = 0;
1154 buf[2] = 0;
1155 buf[3] = 1;
1156 buf[4] = 0;
1157 len = 4 + buf[3];
1158 } else {
1159 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1160 p->asc = 0x24;
1161 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1162 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1163 ahci_write_fis_d2h(p, slot, cfis, tfd);
1164 return;
1165 }
1166 } else {
1167 buf[0] = 0x05;
1168 buf[1] = 0x80;
1169 buf[2] = 0x00;
1170 buf[3] = 0x21;
1171 buf[4] = 31;
1172 buf[5] = 0;
1173 buf[6] = 0;
1174 buf[7] = 0;
1175 atapi_string(buf + 8, "BHYVE", 8);
1176 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1177 atapi_string(buf + 32, "001", 4);
1178 len = sizeof(buf);
1179 }
1180
1181 if (len > acmd[4])
1182 len = acmd[4];
1183 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1184 write_prdt(p, slot, cfis, buf, len);
1185 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1186 }
1187
1188 static void
1189 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1190 {
1191 uint8_t buf[8];
1192 uint64_t sectors;
1193
1194 sectors = blockif_size(p->bctx) / 2048;
1195 be32enc(buf, sectors - 1);
1196 be32enc(buf + 4, 2048);
1197 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1198 write_prdt(p, slot, cfis, buf, sizeof(buf));
1199 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1200 }
1201
1202 static void
1203 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1204 {
1205 uint8_t *acmd;
1206 uint8_t format;
1207 unsigned int len;
1208
1209 acmd = cfis + 0x40;
1210
1211 len = be16dec(acmd + 7);
1212 format = acmd[9] >> 6;
1213 switch (format) {
1214 case 0:
1215 {
1216 size_t size;
1217 int msf;
1218 uint64_t sectors;
1219 uint8_t start_track, buf[20], *bp;
1220
1221 msf = (acmd[1] >> 1) & 1;
1222 start_track = acmd[6];
1223 if (start_track > 1 && start_track != 0xaa) {
1224 uint32_t tfd;
1225 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1226 p->asc = 0x24;
1227 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1228 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1229 ahci_write_fis_d2h(p, slot, cfis, tfd);
1230 return;
1231 }
1232 bp = buf + 2;
1233 *bp++ = 1;
1234 *bp++ = 1;
1235 if (start_track <= 1) {
1236 *bp++ = 0;
1237 *bp++ = 0x14;
1238 *bp++ = 1;
1239 *bp++ = 0;
1240 if (msf) {
1241 *bp++ = 0;
1242 lba_to_msf(bp, 0);
1243 bp += 3;
1244 } else {
1245 *bp++ = 0;
1246 *bp++ = 0;
1247 *bp++ = 0;
1248 *bp++ = 0;
1249 }
1250 }
1251 *bp++ = 0;
1252 *bp++ = 0x14;
1253 *bp++ = 0xaa;
1254 *bp++ = 0;
1255 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1256 sectors >>= 2;
1257 if (msf) {
1258 *bp++ = 0;
1259 lba_to_msf(bp, sectors);
1260 bp += 3;
1261 } else {
1262 be32enc(bp, sectors);
1263 bp += 4;
1264 }
1265 size = bp - buf;
1266 be16enc(buf, size - 2);
1267 if (len > size)
1268 len = size;
1269 write_prdt(p, slot, cfis, buf, len);
1270 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1271 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1272 break;
1273 }
1274 case 1:
1275 {
1276 uint8_t buf[12];
1277
1278 memset(buf, 0, sizeof(buf));
1279 buf[1] = 0xa;
1280 buf[2] = 0x1;
1281 buf[3] = 0x1;
1282 if (len > sizeof(buf))
1283 len = sizeof(buf);
1284 write_prdt(p, slot, cfis, buf, len);
1285 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1286 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1287 break;
1288 }
1289 case 2:
1290 {
1291 size_t size;
1292 int msf;
1293 uint64_t sectors;
1294 uint8_t *bp, buf[50];
1295
1296 msf = (acmd[1] >> 1) & 1;
1297 bp = buf + 2;
1298 *bp++ = 1;
1299 *bp++ = 1;
1300
1301 *bp++ = 1;
1302 *bp++ = 0x14;
1303 *bp++ = 0;
1304 *bp++ = 0xa0;
1305 *bp++ = 0;
1306 *bp++ = 0;
1307 *bp++ = 0;
1308 *bp++ = 0;
1309 *bp++ = 1;
1310 *bp++ = 0;
1311 *bp++ = 0;
1312
1313 *bp++ = 1;
1314 *bp++ = 0x14;
1315 *bp++ = 0;
1316 *bp++ = 0xa1;
1317 *bp++ = 0;
1318 *bp++ = 0;
1319 *bp++ = 0;
1320 *bp++ = 0;
1321 *bp++ = 1;
1322 *bp++ = 0;
1323 *bp++ = 0;
1324
1325 *bp++ = 1;
1326 *bp++ = 0x14;
1327 *bp++ = 0;
1328 *bp++ = 0xa2;
1329 *bp++ = 0;
1330 *bp++ = 0;
1331 *bp++ = 0;
1332 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1333 sectors >>= 2;
1334 if (msf) {
1335 *bp++ = 0;
1336 lba_to_msf(bp, sectors);
1337 bp += 3;
1338 } else {
1339 be32enc(bp, sectors);
1340 bp += 4;
1341 }
1342
1343 *bp++ = 1;
1344 *bp++ = 0x14;
1345 *bp++ = 0;
1346 *bp++ = 1;
1347 *bp++ = 0;
1348 *bp++ = 0;
1349 *bp++ = 0;
1350 if (msf) {
1351 *bp++ = 0;
1352 lba_to_msf(bp, 0);
1353 bp += 3;
1354 } else {
1355 *bp++ = 0;
1356 *bp++ = 0;
1357 *bp++ = 0;
1358 *bp++ = 0;
1359 }
1360
1361 size = bp - buf;
1362 be16enc(buf, size - 2);
1363 if (len > size)
1364 len = size;
1365 write_prdt(p, slot, cfis, buf, len);
1366 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1367 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1368 break;
1369 }
1370 default:
1371 {
1372 uint32_t tfd;
1373
1374 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1375 p->asc = 0x24;
1376 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1377 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1378 ahci_write_fis_d2h(p, slot, cfis, tfd);
1379 break;
1380 }
1381 }
1382 }
1383
1384 static void
1385 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1386 {
1387 uint8_t buf[16];
1388
1389 memset(buf, 0, sizeof(buf));
1390 buf[3] = 8;
1391
1392 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1393 write_prdt(p, slot, cfis, buf, sizeof(buf));
1394 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1395 }
1396
1397 static void
1398 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
1399 {
1400 struct ahci_ioreq *aior;
1401 struct ahci_cmd_hdr *hdr;
1402 struct ahci_prdt_entry *prdt;
1403 struct blockif_req *breq;
1404 uint8_t *acmd;
1405 uint64_t lba;
1406 uint32_t len;
1407 int err;
1408
1409 acmd = cfis + 0x40;
1410 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1411 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1412
1413 lba = be32dec(acmd + 2);
1414 if (acmd[0] == READ_10)
1415 len = be16dec(acmd + 7);
1416 else
1417 len = be32dec(acmd + 6);
1418 if (len == 0) {
1419 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1420 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1421 }
1422 lba *= 2048;
1423 len *= 2048;
1424
1425 /*
1426 * Pull request off free list
1427 */
1428 aior = STAILQ_FIRST(&p->iofhd);
1429 assert(aior != NULL);
1430 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1431 aior->cfis = cfis;
1432 aior->slot = slot;
1433 aior->len = len;
1434 aior->done = done;
1435 breq = &aior->io_req;
1436 breq->br_offset = lba + done;
1437 ahci_build_iov(p, aior, prdt, hdr->prdtl);
1438
1439 /* Mark this command in-flight. */
1440 p->pending |= 1 << slot;
1441
1442 /* Stuff request onto busy list. */
1443 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1444
1445 err = blockif_read(p->bctx, breq);
1446 assert(err == 0);
1447 }
1448
1449 static void
1450 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1451 {
1452 uint8_t buf[64];
1453 uint8_t *acmd;
1454 unsigned int len;
1455
1456 acmd = cfis + 0x40;
1457 len = acmd[4];
1458 if (len > sizeof(buf))
1459 len = sizeof(buf);
1460 memset(buf, 0, len);
1461 buf[0] = 0x70 | (1 << 7);
1462 buf[2] = p->sense_key;
1463 buf[7] = 10;
1464 buf[12] = p->asc;
1465 write_prdt(p, slot, cfis, buf, len);
1466 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1467 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1468 }
1469
1470 static void
1471 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1472 {
1473 uint8_t *acmd = cfis + 0x40;
1474 uint32_t tfd;
1475
1476 switch (acmd[4] & 3) {
1477 case 0:
1478 case 1:
1479 case 3:
1480 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1481 tfd = ATA_S_READY | ATA_S_DSC;
1482 break;
1483 case 2:
1484 /* TODO eject media */
1485 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1486 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1487 p->asc = 0x53;
1488 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1489 break;
1490 }
1491 ahci_write_fis_d2h(p, slot, cfis, tfd);
1492 }
1493
1494 static void
1495 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1496 {
1497 uint8_t *acmd;
1498 uint32_t tfd = 0;
1499 uint8_t pc, code;
1500 unsigned int len;
1501
1502 acmd = cfis + 0x40;
1503 len = be16dec(acmd + 7);
1504 pc = acmd[2] >> 6;
1505 code = acmd[2] & 0x3f;
1506
1507 switch (pc) {
1508 case 0:
1509 switch (code) {
1510 case MODEPAGE_RW_ERROR_RECOVERY:
1511 {
1512 uint8_t buf[16];
1513
1514 if (len > sizeof(buf))
1515 len = sizeof(buf);
1516
1517 memset(buf, 0, sizeof(buf));
1518 be16enc(buf, 16 - 2);
1519 buf[2] = 0x70;
1520 buf[8] = 0x01;
1521 buf[9] = 16 - 10;
1522 buf[11] = 0x05;
1523 write_prdt(p, slot, cfis, buf, len);
1524 tfd = ATA_S_READY | ATA_S_DSC;
1525 break;
1526 }
1527 case MODEPAGE_CD_CAPABILITIES:
1528 {
1529 uint8_t buf[30];
1530
1531 if (len > sizeof(buf))
1532 len = sizeof(buf);
1533
1534 memset(buf, 0, sizeof(buf));
1535 be16enc(buf, 30 - 2);
1536 buf[2] = 0x70;
1537 buf[8] = 0x2A;
1538 buf[9] = 30 - 10;
1539 buf[10] = 0x08;
1540 buf[12] = 0x71;
1541 be16enc(&buf[18], 2);
1542 be16enc(&buf[20], 512);
1543 write_prdt(p, slot, cfis, buf, len);
1544 tfd = ATA_S_READY | ATA_S_DSC;
1545 break;
1546 }
1547 default:
1548 goto error;
1549 break;
1550 }
1551 break;
1552 case 3:
1553 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1554 p->asc = 0x39;
1555 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1556 break;
1557 error:
1558 case 1:
1559 case 2:
1560 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1561 p->asc = 0x24;
1562 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1563 break;
1564 }
1565 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1566 ahci_write_fis_d2h(p, slot, cfis, tfd);
1567 }
1568
1569 static void
1570 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1571 uint8_t *cfis)
1572 {
1573 uint8_t *acmd;
1574 uint32_t tfd;
1575
1576 acmd = cfis + 0x40;
1577
1578 /* we don't support asynchronous operation */
1579 if (!(acmd[1] & 1)) {
1580 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1581 p->asc = 0x24;
1582 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1583 } else {
1584 uint8_t buf[8];
1585 unsigned int len;
1586
1587 len = be16dec(acmd + 7);
1588 if (len > sizeof(buf))
1589 len = sizeof(buf);
1590
1591 memset(buf, 0, sizeof(buf));
1592 be16enc(buf, 8 - 2);
1593 buf[2] = 0x04;
1594 buf[3] = 0x10;
1595 buf[5] = 0x02;
1596 write_prdt(p, slot, cfis, buf, len);
1597 tfd = ATA_S_READY | ATA_S_DSC;
1598 }
1599 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1600 ahci_write_fis_d2h(p, slot, cfis, tfd);
1601 }
1602
1603 static void
1604 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1605 {
1606 uint8_t *acmd;
1607
1608 acmd = cfis + 0x40;
1609
1610 #ifdef AHCI_DEBUG
1611 {
1612 int i;
1613 DPRINTF("ACMD:");
1614 for (i = 0; i < 16; i++)
1615 DPRINTF("%02x ", acmd[i]);
1616 DPRINTF("");
1617 }
1618 #endif
1619
1620 switch (acmd[0]) {
1621 case TEST_UNIT_READY:
1622 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1623 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1624 break;
1625 case INQUIRY:
1626 atapi_inquiry(p, slot, cfis);
1627 break;
1628 case READ_CAPACITY:
1629 atapi_read_capacity(p, slot, cfis);
1630 break;
1631 case PREVENT_ALLOW:
1632 /* TODO */
1633 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1634 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1635 break;
1636 case READ_TOC:
1637 atapi_read_toc(p, slot, cfis);
1638 break;
1639 case REPORT_LUNS:
1640 atapi_report_luns(p, slot, cfis);
1641 break;
1642 case READ_10:
1643 case READ_12:
1644 atapi_read(p, slot, cfis, 0);
1645 break;
1646 case REQUEST_SENSE:
1647 atapi_request_sense(p, slot, cfis);
1648 break;
1649 case START_STOP_UNIT:
1650 atapi_start_stop_unit(p, slot, cfis);
1651 break;
1652 case MODE_SENSE_10:
1653 atapi_mode_sense(p, slot, cfis);
1654 break;
1655 case GET_EVENT_STATUS_NOTIFICATION:
1656 atapi_get_event_status_notification(p, slot, cfis);
1657 break;
1658 default:
1659 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1660 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1661 p->asc = 0x20;
1662 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1663 ATA_S_READY | ATA_S_ERROR);
1664 break;
1665 }
1666 }
1667
1668 static void
1669 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1670 {
1671
1672 p->tfd |= ATA_S_BUSY;
1673 switch (cfis[2]) {
1674 case ATA_ATA_IDENTIFY:
1675 handle_identify(p, slot, cfis);
1676 break;
1677 case ATA_SETFEATURES:
1678 {
1679 switch (cfis[3]) {
1680 case ATA_SF_ENAB_SATA_SF:
1681 switch (cfis[12]) {
1682 case ATA_SATA_SF_AN:
1683 p->tfd = ATA_S_DSC | ATA_S_READY;
1684 break;
1685 default:
1686 p->tfd = ATA_S_ERROR | ATA_S_READY;
1687 p->tfd |= (ATA_ERROR_ABORT << 8);
1688 break;
1689 }
1690 break;
1691 case ATA_SF_ENAB_WCACHE:
1692 case ATA_SF_DIS_WCACHE:
1693 case ATA_SF_ENAB_RCACHE:
1694 case ATA_SF_DIS_RCACHE:
1695 p->tfd = ATA_S_DSC | ATA_S_READY;
1696 break;
1697 case ATA_SF_SETXFER:
1698 {
1699 switch (cfis[12] & 0xf8) {
1700 case ATA_PIO:
1701 case ATA_PIO0:
1702 break;
1703 case ATA_WDMA0:
1704 case ATA_UDMA0:
1705 p->xfermode = (cfis[12] & 0x7);
1706 break;
1707 }
1708 p->tfd = ATA_S_DSC | ATA_S_READY;
1709 break;
1710 }
1711 default:
1712 p->tfd = ATA_S_ERROR | ATA_S_READY;
1713 p->tfd |= (ATA_ERROR_ABORT << 8);
1714 break;
1715 }
1716 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1717 break;
1718 }
1719 case ATA_SET_MULTI:
1720 if (cfis[12] != 0 &&
1721 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1722 p->tfd = ATA_S_ERROR | ATA_S_READY;
1723 p->tfd |= (ATA_ERROR_ABORT << 8);
1724 } else {
1725 p->mult_sectors = cfis[12];
1726 p->tfd = ATA_S_DSC | ATA_S_READY;
1727 }
1728 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1729 break;
1730 case ATA_READ:
1731 case ATA_WRITE:
1732 case ATA_READ48:
1733 case ATA_WRITE48:
1734 case ATA_READ_MUL:
1735 case ATA_WRITE_MUL:
1736 case ATA_READ_MUL48:
1737 case ATA_WRITE_MUL48:
1738 case ATA_READ_DMA:
1739 case ATA_WRITE_DMA:
1740 case ATA_READ_DMA48:
1741 case ATA_WRITE_DMA48:
1742 case ATA_READ_FPDMA_QUEUED:
1743 case ATA_WRITE_FPDMA_QUEUED:
1744 ahci_handle_rw(p, slot, cfis, 0);
1745 break;
1746 case ATA_FLUSHCACHE:
1747 case ATA_FLUSHCACHE48:
1748 ahci_handle_flush(p, slot, cfis);
1749 break;
1750 case ATA_DATA_SET_MANAGEMENT:
1751 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1752 cfis[13] == 0 && cfis[12] == 1) {
1753 ahci_handle_dsm_trim(p, slot, cfis, 0);
1754 break;
1755 }
1756 ahci_write_fis_d2h(p, slot, cfis,
1757 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1758 break;
1759 case ATA_SEND_FPDMA_QUEUED:
1760 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1761 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1762 cfis[11] == 0 && cfis[3] == 1) {
1763 ahci_handle_dsm_trim(p, slot, cfis, 0);
1764 break;
1765 }
1766 ahci_write_fis_d2h(p, slot, cfis,
1767 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1768 break;
1769 case ATA_READ_LOG_EXT:
1770 case ATA_READ_LOG_DMA_EXT:
1771 ahci_handle_read_log(p, slot, cfis);
1772 break;
1773 case ATA_SECURITY_FREEZE_LOCK:
1774 case ATA_SMART_CMD:
1775 case ATA_NOP:
1776 ahci_write_fis_d2h(p, slot, cfis,
1777 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1778 break;
1779 case ATA_CHECK_POWER_MODE:
1780 cfis[12] = 0xff; /* always on */
1781 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1782 break;
1783 case ATA_STANDBY_CMD:
1784 case ATA_STANDBY_IMMEDIATE:
1785 case ATA_IDLE_CMD:
1786 case ATA_IDLE_IMMEDIATE:
1787 case ATA_SLEEP:
1788 case ATA_READ_VERIFY:
1789 case ATA_READ_VERIFY48:
1790 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1791 break;
1792 case ATA_ATAPI_IDENTIFY:
1793 handle_atapi_identify(p, slot, cfis);
1794 break;
1795 case ATA_PACKET_CMD:
1796 if (!p->atapi) {
1797 ahci_write_fis_d2h(p, slot, cfis,
1798 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1799 } else
1800 handle_packet_cmd(p, slot, cfis);
1801 break;
1802 default:
1803 WPRINTF("Unsupported cmd:%02x", cfis[2]);
1804 ahci_write_fis_d2h(p, slot, cfis,
1805 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1806 break;
1807 }
1808 }
1809
1810 static void
1811 ahci_handle_slot(struct ahci_port *p, int slot)
1812 {
1813 struct ahci_cmd_hdr *hdr;
1814 #ifdef AHCI_DEBUG
1815 struct ahci_prdt_entry *prdt;
1816 #endif
1817 struct pci_ahci_softc *sc;
1818 uint8_t *cfis;
1819 #ifdef AHCI_DEBUG
1820 int cfl, i;
1821 #endif
1822
1823 sc = p->pr_sc;
1824 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1825 #ifdef AHCI_DEBUG
1826 cfl = (hdr->flags & 0x1f) * 4;
1827 #endif
1828 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1829 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1830 #ifdef AHCI_DEBUG
1831 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1832
1833 DPRINTF("cfis:");
1834 for (i = 0; i < cfl; i++) {
1835 if (i % 10 == 0)
1836 DPRINTF("");
1837 DPRINTF("%02x ", cfis[i]);
1838 }
1839 DPRINTF("");
1840
1841 for (i = 0; i < hdr->prdtl; i++) {
1842 DPRINTF("%d@%08"PRIx64"", prdt->dbc & 0x3fffff, prdt->dba);
1843 prdt++;
1844 }
1845 #endif
1846
1847 if (cfis[0] != FIS_TYPE_REGH2D) {
1848 WPRINTF("Not a H2D FIS:%02x", cfis[0]);
1849 return;
1850 }
1851
1852 if (cfis[1] & 0x80) {
1853 ahci_handle_cmd(p, slot, cfis);
1854 } else {
1855 if (cfis[15] & (1 << 2))
1856 p->reset = 1;
1857 else if (p->reset) {
1858 p->reset = 0;
1859 ahci_port_reset(p);
1860 }
1861 p->ci &= ~(1 << slot);
1862 }
1863 }
1864
1865 static void
1866 ahci_handle_port(struct ahci_port *p)
1867 {
1868
1869 if (!(p->cmd & AHCI_P_CMD_ST))
1870 return;
1871
1872 /*
1873 * Search for any new commands to issue ignoring those that
1874 * are already in-flight. Stop if device is busy or in error.
1875 */
1876 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) {
1877 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0)
1878 break;
1879 if (p->waitforclear)
1880 break;
1881 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) {
1882 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1883 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT;
1884 ahci_handle_slot(p, p->ccs);
1885 }
1886 }
1887 }
1888
1889 /*
1890 * blockif callback routine - this runs in the context of the blockif
1891 * i/o thread, so the mutex needs to be acquired.
1892 */
1893 static void
1894 ata_ioreq_cb(struct blockif_req *br, int err)
1895 {
1896 struct ahci_cmd_hdr *hdr;
1897 struct ahci_ioreq *aior;
1898 struct ahci_port *p;
1899 struct pci_ahci_softc *sc;
1900 uint32_t tfd;
1901 uint8_t *cfis;
1902 int slot, ncq, dsm;
1903
1904 DPRINTF("%s %d", __func__, err);
1905
1906 ncq = dsm = 0;
1907 aior = br->br_param;
1908 p = aior->io_pr;
1909 cfis = aior->cfis;
1910 slot = aior->slot;
1911 sc = p->pr_sc;
1912 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1913
1914 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1915 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1916 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1917 ncq = 1;
1918 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1919 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1920 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1921 dsm = 1;
1922
1923 pthread_mutex_lock(&sc->mtx);
1924
1925 /*
1926 * Delete the blockif request from the busy list
1927 */
1928 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1929
1930 /*
1931 * Move the blockif request back to the free list
1932 */
1933 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1934
1935 if (!err)
1936 hdr->prdbc = aior->done;
1937
1938 if (!err && aior->more) {
1939 if (dsm)
1940 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1941 else
1942 ahci_handle_rw(p, slot, cfis, aior->done);
1943 goto out;
1944 }
1945
1946 if (!err)
1947 tfd = ATA_S_READY | ATA_S_DSC;
1948 else
1949 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1950 if (ncq)
1951 ahci_write_fis_sdb(p, slot, cfis, tfd);
1952 else
1953 ahci_write_fis_d2h(p, slot, cfis, tfd);
1954
1955 /*
1956 * This command is now complete.
1957 */
1958 p->pending &= ~(1 << slot);
1959
1960 ahci_check_stopped(p);
1961 ahci_handle_port(p);
1962 out:
1963 pthread_mutex_unlock(&sc->mtx);
1964 DPRINTF("%s exit", __func__);
1965 }
1966
1967 static void
1968 atapi_ioreq_cb(struct blockif_req *br, int err)
1969 {
1970 struct ahci_cmd_hdr *hdr;
1971 struct ahci_ioreq *aior;
1972 struct ahci_port *p;
1973 struct pci_ahci_softc *sc;
1974 uint8_t *cfis;
1975 uint32_t tfd;
1976 int slot;
1977
1978 DPRINTF("%s %d", __func__, err);
1979
1980 aior = br->br_param;
1981 p = aior->io_pr;
1982 cfis = aior->cfis;
1983 slot = aior->slot;
1984 sc = p->pr_sc;
1985 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1986
1987 pthread_mutex_lock(&sc->mtx);
1988
1989 /*
1990 * Delete the blockif request from the busy list
1991 */
1992 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1993
1994 /*
1995 * Move the blockif request back to the free list
1996 */
1997 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1998
1999 if (!err)
2000 hdr->prdbc = aior->done;
2001
2002 if (!err && aior->more) {
2003 atapi_read(p, slot, cfis, aior->done);
2004 goto out;
2005 }
2006
2007 if (!err) {
2008 tfd = ATA_S_READY | ATA_S_DSC;
2009 } else {
2010 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
2011 p->asc = 0x21;
2012 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
2013 }
2014 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
2015 ahci_write_fis_d2h(p, slot, cfis, tfd);
2016
2017 /*
2018 * This command is now complete.
2019 */
2020 p->pending &= ~(1 << slot);
2021
2022 ahci_check_stopped(p);
2023 ahci_handle_port(p);
2024 out:
2025 pthread_mutex_unlock(&sc->mtx);
2026 DPRINTF("%s exit", __func__);
2027 }
2028
2029 static void
2030 pci_ahci_ioreq_init(struct ahci_port *pr)
2031 {
2032 struct ahci_ioreq *vr;
2033 int i;
2034
2035 pr->ioqsz = blockif_queuesz(pr->bctx);
2036 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
2037 STAILQ_INIT(&pr->iofhd);
2038
2039 /*
2040 * Add all i/o request entries to the free queue
2041 */
2042 for (i = 0; i < pr->ioqsz; i++) {
2043 vr = &pr->ioreq[i];
2044 vr->io_pr = pr;
2045 if (!pr->atapi)
2046 vr->io_req.br_callback = ata_ioreq_cb;
2047 else
2048 vr->io_req.br_callback = atapi_ioreq_cb;
2049 vr->io_req.br_param = vr;
2050 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
2051 }
2052
2053 TAILQ_INIT(&pr->iobhd);
2054 }
2055
2056 static void
2057 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2058 {
2059 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2060 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2061 struct ahci_port *p = &sc->port[port];
2062
2063 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2064 port, offset, value);
2065
2066 switch (offset) {
2067 case AHCI_P_CLB:
2068 p->clb = value;
2069 break;
2070 case AHCI_P_CLBU:
2071 p->clbu = value;
2072 break;
2073 case AHCI_P_FB:
2074 p->fb = value;
2075 break;
2076 case AHCI_P_FBU:
2077 p->fbu = value;
2078 break;
2079 case AHCI_P_IS:
2080 p->is &= ~value;
2081 ahci_port_intr(p);
2082 break;
2083 case AHCI_P_IE:
2084 p->ie = value & 0xFDC000FF;
2085 ahci_port_intr(p);
2086 break;
2087 case AHCI_P_CMD:
2088 {
2089 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2090 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2091 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2092 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK);
2093 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2094 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2095 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2096 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value;
2097
2098 if (!(value & AHCI_P_CMD_ST)) {
2099 ahci_port_stop(p);
2100 } else {
2101 uint64_t clb;
2102
2103 p->cmd |= AHCI_P_CMD_CR;
2104 clb = (uint64_t)p->clbu << 32 | p->clb;
2105 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
2106 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
2107 }
2108
2109 if (value & AHCI_P_CMD_FRE) {
2110 uint64_t fb;
2111
2112 p->cmd |= AHCI_P_CMD_FR;
2113 fb = (uint64_t)p->fbu << 32 | p->fb;
2114 /* we don't support FBSCP, so rfis size is 256Bytes */
2115 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
2116 } else {
2117 p->cmd &= ~AHCI_P_CMD_FR;
2118 }
2119
2120 if (value & AHCI_P_CMD_CLO) {
2121 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ);
2122 p->cmd &= ~AHCI_P_CMD_CLO;
2123 }
2124
2125 if (value & AHCI_P_CMD_ICC_MASK) {
2126 p->cmd &= ~AHCI_P_CMD_ICC_MASK;
2127 }
2128
2129 ahci_handle_port(p);
2130 break;
2131 }
2132 case AHCI_P_TFD:
2133 case AHCI_P_SIG:
2134 case AHCI_P_SSTS:
2135 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"", offset);
2136 break;
2137 case AHCI_P_SCTL:
2138 p->sctl = value;
2139 if (!(p->cmd & AHCI_P_CMD_ST)) {
2140 if (value & ATA_SC_DET_RESET)
2141 ahci_port_reset(p);
2142 }
2143 break;
2144 case AHCI_P_SERR:
2145 p->serr &= ~value;
2146 break;
2147 case AHCI_P_SACT:
2148 p->sact |= value;
2149 break;
2150 case AHCI_P_CI:
2151 p->ci |= value;
2152 ahci_handle_port(p);
2153 break;
2154 case AHCI_P_SNTF:
2155 case AHCI_P_FBS:
2156 default:
2157 break;
2158 }
2159 }
2160
2161 static void
2162 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2163 {
2164 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2165 offset, value);
2166
2167 switch (offset) {
2168 case AHCI_CAP:
2169 case AHCI_PI:
2170 case AHCI_VS:
2171 case AHCI_CAP2:
2172 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"", offset);
2173 break;
2174 case AHCI_GHC:
2175 if (value & AHCI_GHC_HR) {
2176 ahci_reset(sc);
2177 break;
2178 }
2179 if (value & AHCI_GHC_IE)
2180 sc->ghc |= AHCI_GHC_IE;
2181 else
2182 sc->ghc &= ~AHCI_GHC_IE;
2183 ahci_generate_intr(sc, 0xffffffff);
2184 break;
2185 case AHCI_IS:
2186 sc->is &= ~value;
2187 ahci_generate_intr(sc, value);
2188 break;
2189 default:
2190 break;
2191 }
2192 }
2193
2194 static void
2195 pci_ahci_write(struct vmctx *ctx __unused,
2196 struct pci_devinst *pi, int baridx, uint64_t offset, int size,
2197 uint64_t value)
2198 {
2199 struct pci_ahci_softc *sc = pi->pi_arg;
2200
2201 assert(baridx == 5);
2202 assert((offset % 4) == 0 && size == 4);
2203
2204 pthread_mutex_lock(&sc->mtx);
2205
2206 if (offset < AHCI_OFFSET)
2207 pci_ahci_host_write(sc, offset, value);
2208 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP)
2209 pci_ahci_port_write(sc, offset, value);
2210 else
2211 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"", offset);
2212
2213 pthread_mutex_unlock(&sc->mtx);
2214 }
2215
2216 static uint64_t
2217 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2218 {
2219 uint32_t value;
2220
2221 switch (offset) {
2222 case AHCI_CAP:
2223 case AHCI_GHC:
2224 case AHCI_IS:
2225 case AHCI_PI:
2226 case AHCI_VS:
2227 case AHCI_CCCC:
2228 case AHCI_CCCP:
2229 case AHCI_EM_LOC:
2230 case AHCI_EM_CTL:
2231 case AHCI_CAP2:
2232 {
2233 uint32_t *p = &sc->cap;
2234 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2235 value = *p;
2236 break;
2237 }
2238 default:
2239 value = 0;
2240 break;
2241 }
2242 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x",
2243 offset, value);
2244
2245 return (value);
2246 }
2247
2248 static uint64_t
2249 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2250 {
2251 uint32_t value;
2252 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2253 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2254
2255 switch (offset) {
2256 case AHCI_P_CLB:
2257 case AHCI_P_CLBU:
2258 case AHCI_P_FB:
2259 case AHCI_P_FBU:
2260 case AHCI_P_IS:
2261 case AHCI_P_IE:
2262 case AHCI_P_CMD:
2263 case AHCI_P_TFD:
2264 case AHCI_P_SIG:
2265 case AHCI_P_SSTS:
2266 case AHCI_P_SCTL:
2267 case AHCI_P_SERR:
2268 case AHCI_P_SACT:
2269 case AHCI_P_CI:
2270 case AHCI_P_SNTF:
2271 case AHCI_P_FBS:
2272 {
2273 uint32_t *p= &sc->port[port].clb;
2274 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2275 value = *p;
2276 break;
2277 }
2278 default:
2279 value = 0;
2280 break;
2281 }
2282
2283 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x",
2284 port, offset, value);
2285
2286 return value;
2287 }
2288
2289 static uint64_t
2290 pci_ahci_read(struct vmctx *ctx __unused,
2291 struct pci_devinst *pi, int baridx, uint64_t regoff, int size)
2292 {
2293 struct pci_ahci_softc *sc = pi->pi_arg;
2294 uint64_t offset;
2295 uint32_t value;
2296
2297 assert(baridx == 5);
2298 assert(size == 1 || size == 2 || size == 4);
2299 assert((regoff & (size - 1)) == 0);
2300
2301 pthread_mutex_lock(&sc->mtx);
2302
2303 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */
2304 if (offset < AHCI_OFFSET)
2305 value = pci_ahci_host_read(sc, offset);
2306 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP)
2307 value = pci_ahci_port_read(sc, offset);
2308 else {
2309 value = 0;
2310 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"",
2311 regoff);
2312 }
2313 value >>= 8 * (regoff & 0x3);
2314
2315 pthread_mutex_unlock(&sc->mtx);
2316
2317 return (value);
2318 }
2319
2320 /*
2321 * Each AHCI controller has a "port" node which contains nodes for
2322 * each port named after the decimal number of the port (no leading
2323 * zeroes). Port nodes contain a "type" ("hd" or "cd"), as well as
2324 * options for blockif. For example:
2325 *
2326 * pci.0.1.0
2327 * .device="ahci"
2328 * .port
2329 * .0
2330 * .type="hd"
2331 * .path="/path/to/image"
2332 */
2333 static int
2334 pci_ahci_legacy_config_port(nvlist_t *nvl, int port, const char *type,
2335 const char *opts)
2336 {
2337 char node_name[sizeof("XX")];
2338 nvlist_t *port_nvl;
2339
2340 snprintf(node_name, sizeof(node_name), "%d", port);
2341 port_nvl = create_relative_config_node(nvl, node_name);
2342 set_config_value_node(port_nvl, "type", type);
2343 return (blockif_legacy_config(port_nvl, opts));
2344 }
2345
2346 static int
2347 pci_ahci_legacy_config(nvlist_t *nvl, const char *opts)
2348 {
2349 nvlist_t *ports_nvl;
2350 const char *type;
2351 char *next, *next2, *str, *tofree;
2352 int p, ret;
2353
2354 if (opts == NULL)
2355 return (0);
2356
2357 ports_nvl = create_relative_config_node(nvl, "port");
2358 ret = 1;
2359 tofree = str = strdup(opts);
2360 for (p = 0; p < MAX_PORTS && str != NULL; p++, str = next) {
2361 /* Identify and cut off type of present port. */
2362 if (strncmp(str, "hd:", 3) == 0) {
2363 type = "hd";
2364 str += 3;
2365 } else if (strncmp(str, "cd:", 3) == 0) {
2366 type = "cd";
2367 str += 3;
2368 } else
2369 type = NULL;
2370
2371 /* Find and cut off the next port options. */
2372 next = strstr(str, ",hd:");
2373 next2 = strstr(str, ",cd:");
2374 if (next == NULL || (next2 != NULL && next2 < next))
2375 next = next2;
2376 if (next != NULL) {
2377 next[0] = 0;
2378 next++;
2379 }
2380
2381 if (str[0] == 0)
2382 continue;
2383
2384 if (type == NULL) {
2385 EPRINTLN("Missing or invalid type for port %d: \"%s\"",
2386 p, str);
2387 goto out;
2388 }
2389
2390 if (pci_ahci_legacy_config_port(ports_nvl, p, type, str) != 0)
2391 goto out;
2392 }
2393 ret = 0;
2394 out:
2395 free(tofree);
2396 return (ret);
2397 }
2398
2399 static int
2400 pci_ahci_cd_legacy_config(nvlist_t *nvl, const char *opts)
2401 {
2402 nvlist_t *ports_nvl;
2403
2404 ports_nvl = create_relative_config_node(nvl, "port");
2405 return (pci_ahci_legacy_config_port(ports_nvl, 0, "cd", opts));
2406 }
2407
2408 static int
2409 pci_ahci_hd_legacy_config(nvlist_t *nvl, const char *opts)
2410 {
2411 nvlist_t *ports_nvl;
2412
2413 ports_nvl = create_relative_config_node(nvl, "port");
2414 return (pci_ahci_legacy_config_port(ports_nvl, 0, "hd", opts));
2415 }
2416
2417 static int
2418 pci_ahci_init(struct vmctx *ctx __unused, struct pci_devinst *pi, nvlist_t *nvl)
2419 {
2420 char bident[sizeof("XXX:XXX:XXX")];
2421 char node_name[sizeof("XX")];
2422 struct blockif_ctxt *bctxt;
2423 struct pci_ahci_softc *sc;
2424 int atapi, ret, slots, p;
2425 MD5_CTX mdctx;
2426 u_char digest[16];
2427 const char *path, *type, *value;
2428 nvlist_t *ports_nvl, *port_nvl;
2429
2430 ret = 0;
2431
2432 #ifdef AHCI_DEBUG
2433 dbg = fopen("/tmp/log", "w+");
2434 #endif
2435
2436 sc = calloc(1, sizeof(struct pci_ahci_softc));
2437 pi->pi_arg = sc;
2438 sc->asc_pi = pi;
2439 pthread_mutex_init(&sc->mtx, NULL);
2440 sc->ports = 0;
2441 sc->pi = 0;
2442 slots = 32;
2443
2444 ports_nvl = find_relative_config_node(nvl, "port");
2445 for (p = 0; ports_nvl != NULL && p < MAX_PORTS; p++) {
2446 struct ata_params *ata_ident = &sc->port[p].ata_ident;
2447 char ident[AHCI_PORT_IDENT];
2448
2449 snprintf(node_name, sizeof(node_name), "%d", p);
2450 port_nvl = find_relative_config_node(ports_nvl, node_name);
2451 if (port_nvl == NULL)
2452 continue;
2453
2454 type = get_config_value_node(port_nvl, "type");
2455 if (type == NULL)
2456 continue;
2457
2458 if (strcmp(type, "hd") == 0)
2459 atapi = 0;
2460 else
2461 atapi = 1;
2462
2463 /*
2464 * Attempt to open the backing image. Use the PCI slot/func
2465 * and the port number for the identifier string.
2466 */
2467 snprintf(bident, sizeof(bident), "%u:%u:%u", pi->pi_slot,
2468 pi->pi_func, p);
2469
2470 bctxt = blockif_open(port_nvl, bident);
2471 if (bctxt == NULL) {
2472 sc->ports = p;
2473 ret = 1;
2474 goto open_fail;
2475 }
2476 sc->port[p].bctx = bctxt;
2477 sc->port[p].pr_sc = sc;
2478 sc->port[p].port = p;
2479 sc->port[p].atapi = atapi;
2480
2481 /*
2482 * Create an identifier for the backing file.
2483 * Use parts of the md5 sum of the filename
2484 */
2485 path = get_config_value_node(port_nvl, "path");
2486 MD5Init(&mdctx);
2487 MD5Update(&mdctx, path, strlen(path));
2488 MD5Final(digest, &mdctx);
2489 snprintf(ident, AHCI_PORT_IDENT,
2490 "BHYVE-%02X%02X-%02X%02X-%02X%02X",
2491 digest[0], digest[1], digest[2], digest[3], digest[4],
2492 digest[5]);
2493
2494 memset(ata_ident, 0, sizeof(struct ata_params));
2495 ata_string((uint8_t*)&ata_ident->serial, ident, 20);
2496 ata_string((uint8_t*)&ata_ident->revision, "001", 8);
2497 if (atapi)
2498 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DVD ROM", 40);
2499 else
2500 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DISK", 40);
2501 value = get_config_value_node(port_nvl, "nmrr");
2502 if (value != NULL)
2503 ata_ident->media_rotation_rate = atoi(value);
2504 value = get_config_value_node(port_nvl, "ser");
2505 if (value != NULL)
2506 ata_string((uint8_t*)(&ata_ident->serial), value, 20);
2507 value = get_config_value_node(port_nvl, "rev");
2508 if (value != NULL)
2509 ata_string((uint8_t*)(&ata_ident->revision), value, 8);
2510 value = get_config_value_node(port_nvl, "model");
2511 if (value != NULL)
2512 ata_string((uint8_t*)(&ata_ident->model), value, 40);
2513 ata_identify_init(&sc->port[p], atapi);
2514
2515 #ifndef __FreeBSD__
2516 /*
2517 * Attempt to enable the write cache for this device, as the
2518 * guest will issue FLUSH commands when it requires durability.
2519 *
2520 * Failure here is fine, since an always-sync device will not
2521 * have an impact on correctness.
2522 */
2523 (void) blockif_set_wce(bctxt, 1);
2524 #endif
2525
2526 /*
2527 * Allocate blockif request structures and add them
2528 * to the free list
2529 */
2530 pci_ahci_ioreq_init(&sc->port[p]);
2531
2532 sc->pi |= (1 << p);
2533 if (sc->port[p].ioqsz < slots)
2534 slots = sc->port[p].ioqsz;
2535 }
2536 sc->ports = p;
2537
2538 /* Intel ICH8 AHCI */
2539 --slots;
2540 if (sc->ports < DEF_PORTS)
2541 sc->ports = DEF_PORTS;
2542 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2543 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2544 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2545 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2546 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2547
2548 sc->vs = 0x10300;
2549 sc->cap2 = AHCI_CAP2_APST;
2550 ahci_reset(sc);
2551
2552 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2553 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2554 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2555 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2556 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2557 p = MIN(sc->ports, 16);
2558 p = flsl(p) - ((p & (p - 1)) ? 0 : 1);
2559 pci_emul_add_msicap(pi, 1 << p);
2560 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2561 AHCI_OFFSET + sc->ports * AHCI_STEP);
2562
2563 pci_lintr_request(pi);
2564
2565 open_fail:
2566 if (ret) {
2567 for (p = 0; p < sc->ports; p++) {
2568 if (sc->port[p].bctx != NULL)
2569 blockif_close(sc->port[p].bctx);
2570 }
2571 free(sc);
2572 }
2573
2574 return (ret);
2575 }
2576
2577 /*
2578 * Use separate emulation names to distinguish drive and atapi devices
2579 */
2580 static const struct pci_devemu pci_de_ahci = {
2581 .pe_emu = "ahci",
2582 .pe_init = pci_ahci_init,
2583 .pe_legacy_config = pci_ahci_legacy_config,
2584 .pe_barwrite = pci_ahci_write,
2585 .pe_barread = pci_ahci_read,
2586 };
2587 PCI_EMUL_SET(pci_de_ahci);
2588
2589 static const struct pci_devemu pci_de_ahci_hd = {
2590 .pe_emu = "ahci-hd",
2591 .pe_legacy_config = pci_ahci_hd_legacy_config,
2592 .pe_alias = "ahci",
2593 };
2594 PCI_EMUL_SET(pci_de_ahci_hd);
2595
2596 static const struct pci_devemu pci_de_ahci_cd = {
2597 .pe_emu = "ahci-cd",
2598 .pe_legacy_config = pci_ahci_cd_legacy_config,
2599 .pe_alias = "ahci",
2600 };
2601 PCI_EMUL_SET(pci_de_ahci_cd);
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