usr/src/cmd/bhyve/mptbl.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2012 NetApp, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/types.h>
  35 #include <sys/errno.h>
  36 #include <x86/mptable.h>
  37
  38 #include <stdio.h>
  39 #include <string.h>
  40
  41 #include "acpi.h"
  42 #include "debug.h"
  43 #include "bhyverun.h"
  44 #include "mptbl.h"
  45 #include "pci_emul.h"
  46
  47 #define MPTABLE_BASE            0xE0000
  48
  49 /* floating pointer length + maximum length of configuration table */
  50 #define MPTABLE_MAX_LENGTH      (65536 + 16)
  51
  52 #define LAPIC_PADDR             0xFEE00000
  53 #define LAPIC_VERSION           16
  54
  55 #define IOAPIC_PADDR            0xFEC00000
  56 #define IOAPIC_VERSION          0x11
  57
  58 #define MP_SPECREV              4
  59 #define MPFP_SIG                "_MP_"
  60
  61 /* Configuration header defines */
  62 #define MPCH_SIG                "PCMP"
  63 #define MPCH_OEMID              "BHyVe   "
  64 #define MPCH_OEMID_LEN          8
  65 #define MPCH_PRODID             "Hypervisor  "
  66 #define MPCH_PRODID_LEN         12
  67
  68 /* Processor entry defines */
  69 #define MPEP_SIG_FAMILY         6       /* XXX bhyve should supply this */
  70 #define MPEP_SIG_MODEL          26
  71 #define MPEP_SIG_STEPPING       5
  72 #define MPEP_SIG                \
  73         ((MPEP_SIG_FAMILY << 8) | \
  74          (MPEP_SIG_MODEL << 4)  | \
  75          (MPEP_SIG_STEPPING))
  76
  77 #define MPEP_FEATURES           (0xBFEBFBFF) /* XXX Intel i7 */
  78
  79 /* Number of local intr entries */
  80 #define MPEII_NUM_LOCAL_IRQ     2
  81
  82 /* Bus entry defines */
  83 #define MPE_NUM_BUSES           2
  84 #define MPE_BUSNAME_LEN         6
  85 #define MPE_BUSNAME_ISA         "ISA   "
  86 #define MPE_BUSNAME_PCI         "PCI   "
  87
  88 static void *oem_tbl_start;
  89 static int oem_tbl_size;
  90
  91 static uint8_t
  92 mpt_compute_checksum(void *base, size_t len)
  93 {
  94         uint8_t *bytes;
  95         uint8_t sum;
  96
  97         for(bytes = base, sum = 0; len > 0; len--) {
  98                 sum += *bytes++;
  99         }
 100
 101         return (256 - sum);
 102 }
 103
 104 static void
 105 mpt_build_mpfp(mpfps_t mpfp, vm_paddr_t gpa)
 106 {
 107
 108         memset(mpfp, 0, sizeof(*mpfp));
 109         memcpy(mpfp->signature, MPFP_SIG, 4);
 110         mpfp->pap = gpa + sizeof(*mpfp);
 111         mpfp->length = 1;
 112         mpfp->spec_rev = MP_SPECREV;
 113         mpfp->checksum = mpt_compute_checksum(mpfp, sizeof(*mpfp));
 114 }
 115
 116 static void
 117 mpt_build_mpch(mpcth_t mpch)
 118 {
 119
 120         memset(mpch, 0, sizeof(*mpch));
 121         memcpy(mpch->signature, MPCH_SIG, 4);
 122         mpch->spec_rev = MP_SPECREV;
 123         memcpy(mpch->oem_id, MPCH_OEMID, MPCH_OEMID_LEN);
 124         memcpy(mpch->product_id, MPCH_PRODID, MPCH_PRODID_LEN);
 125         mpch->apic_address = LAPIC_PADDR;
 126 }
 127
 128 static void
 129 mpt_build_proc_entries(proc_entry_ptr mpep, int ncpu)
 130 {
 131         int i;
 132
 133         for (i = 0; i < ncpu; i++) {
 134                 memset(mpep, 0, sizeof(*mpep));
 135                 mpep->type = MPCT_ENTRY_PROCESSOR;
 136                 mpep->apic_id = i; // XXX
 137                 mpep->apic_version = LAPIC_VERSION;
 138                 mpep->cpu_flags = PROCENTRY_FLAG_EN;
 139                 if (i == 0)
 140                         mpep->cpu_flags |= PROCENTRY_FLAG_BP;
 141                 mpep->cpu_signature = MPEP_SIG;
 142                 mpep->feature_flags = MPEP_FEATURES;
 143                 mpep++;
 144         }
 145 }
 146
 147 static void
 148 mpt_build_localint_entries(int_entry_ptr mpie)
 149 {
 150
 151         /* Hardcode LINT0 as ExtINT on all CPUs. */
 152         memset(mpie, 0, sizeof(*mpie));
 153         mpie->type = MPCT_ENTRY_LOCAL_INT;
 154         mpie->int_type = INTENTRY_TYPE_EXTINT;
 155         mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
 156             INTENTRY_FLAGS_TRIGGER_CONFORM;
 157         mpie->dst_apic_id = 0xff;
 158         mpie->dst_apic_int = 0;
 159         mpie++;
 160
 161         /* Hardcode LINT1 as NMI on all CPUs. */
 162         memset(mpie, 0, sizeof(*mpie));
 163         mpie->type = MPCT_ENTRY_LOCAL_INT;
 164         mpie->int_type = INTENTRY_TYPE_NMI;
 165         mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
 166             INTENTRY_FLAGS_TRIGGER_CONFORM;
 167         mpie->dst_apic_id = 0xff;
 168         mpie->dst_apic_int = 1;
 169 }
 170
 171 static void
 172 mpt_build_bus_entries(bus_entry_ptr mpeb)
 173 {
 174
 175         memset(mpeb, 0, sizeof(*mpeb));
 176         mpeb->type = MPCT_ENTRY_BUS;
 177         mpeb->bus_id = 0;
 178         memcpy(mpeb->bus_type, MPE_BUSNAME_PCI, MPE_BUSNAME_LEN);
 179         mpeb++;
 180
 181         memset(mpeb, 0, sizeof(*mpeb));
 182         mpeb->type = MPCT_ENTRY_BUS;
 183         mpeb->bus_id = 1;
 184         memcpy(mpeb->bus_type, MPE_BUSNAME_ISA, MPE_BUSNAME_LEN);
 185 }
 186
 187 static void
 188 mpt_build_ioapic_entries(io_apic_entry_ptr mpei, int id)
 189 {
 190
 191         memset(mpei, 0, sizeof(*mpei));
 192         mpei->type = MPCT_ENTRY_IOAPIC;
 193         mpei->apic_id = id;
 194         mpei->apic_version = IOAPIC_VERSION;
 195         mpei->apic_flags = IOAPICENTRY_FLAG_EN;
 196         mpei->apic_address = IOAPIC_PADDR;
 197 }
 198
 199 static int
 200 mpt_count_ioint_entries(void)
 201 {
 202         int bus, count;
 203
 204         count = 0;
 205         for (bus = 0; bus <= PCI_BUSMAX; bus++)
 206                 count += pci_count_lintr(bus);
 207
 208         /*
 209          * Always include entries for the first 16 pins along with a entry
 210          * for each active PCI INTx pin.
 211          */
 212         return (16 + count);
 213 }
 214
 215 static void
 216 mpt_generate_pci_int(int bus, int slot, int pin, int pirq_pin __unused,
 217     int ioapic_irq, void *arg)
 218 {
 219         int_entry_ptr *mpiep, mpie;
 220
 221         mpiep = arg;
 222         mpie = *mpiep;
 223         memset(mpie, 0, sizeof(*mpie));
 224
 225         /*
 226          * This is always after another I/O interrupt entry, so cheat
 227          * and fetch the I/O APIC ID from the prior entry.
 228          */
 229         mpie->type = MPCT_ENTRY_INT;
 230         mpie->int_type = INTENTRY_TYPE_INT;
 231         mpie->src_bus_id = bus;
 232         mpie->src_bus_irq = slot << 2 | (pin - 1);
 233         mpie->dst_apic_id = mpie[-1].dst_apic_id;
 234         mpie->dst_apic_int = ioapic_irq;
 235
 236         *mpiep = mpie + 1;
 237 }
 238
 239 static void
 240 mpt_build_ioint_entries(int_entry_ptr mpie, int id)
 241 {
 242         int pin, bus;
 243
 244         /*
 245          * The following config is taken from kernel mptable.c
 246          * mptable_parse_default_config_ints(...), for now
 247          * just use the default config, tweek later if needed.
 248          */
 249
 250         /* First, generate the first 16 pins. */
 251         for (pin = 0; pin < 16; pin++) {
 252                 memset(mpie, 0, sizeof(*mpie));
 253                 mpie->type = MPCT_ENTRY_INT;
 254                 mpie->src_bus_id = 1;
 255                 mpie->dst_apic_id = id;
 256
 257                 /*
 258                  * All default configs route IRQs from bus 0 to the first 16
 259                  * pins of the first I/O APIC with an APIC ID of 2.
 260                  */
 261                 mpie->dst_apic_int = pin;
 262                 switch (pin) {
 263                 case 0:
 264                         /* Pin 0 is an ExtINT pin. */
 265                         mpie->int_type = INTENTRY_TYPE_EXTINT;
 266                         break;
 267                 case 2:
 268                         /* IRQ 0 is routed to pin 2. */
 269                         mpie->int_type = INTENTRY_TYPE_INT;
 270                         mpie->src_bus_irq = 0;
 271                         break;
 272                 case SCI_INT:
 273                         /* ACPI SCI is level triggered and active-lo. */
 274                         mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO |
 275                             INTENTRY_FLAGS_TRIGGER_LEVEL;
 276                         mpie->int_type = INTENTRY_TYPE_INT;
 277                         mpie->src_bus_irq = SCI_INT;
 278                         break;
 279                 default:
 280                         /* All other pins are identity mapped. */
 281                         mpie->int_type = INTENTRY_TYPE_INT;
 282                         mpie->src_bus_irq = pin;
 283                         break;
 284                 }
 285                 mpie++;
 286         }
 287
 288         /* Next, generate entries for any PCI INTx interrupts. */
 289         for (bus = 0; bus <= PCI_BUSMAX; bus++)
 290                 pci_walk_lintr(bus, mpt_generate_pci_int, &mpie);
 291 }
 292
 293 void
 294 mptable_add_oemtbl(void *tbl, int tblsz)
 295 {
 296
 297         oem_tbl_start = tbl;
 298         oem_tbl_size = tblsz;
 299 }
 300
 301 int
 302 mptable_build(struct vmctx *ctx, int ncpu)
 303 {
 304         mpcth_t                 mpch;
 305         bus_entry_ptr           mpeb;
 306         io_apic_entry_ptr       mpei;
 307         proc_entry_ptr          mpep;
 308         mpfps_t                 mpfp;
 309         int_entry_ptr           mpie;
 310         int                     ioints, bus;
 311         char                    *curraddr;
 312         char                    *startaddr;
 313
 314         startaddr = paddr_guest2host(ctx, MPTABLE_BASE, MPTABLE_MAX_LENGTH);
 315         if (startaddr == NULL) {
 316                 EPRINTLN("mptable requires mapped mem");
 317                 return (ENOMEM);
 318         }
 319
 320         /*
 321          * There is no way to advertise multiple PCI hierarchies via MPtable
 322          * so require that there is no PCI hierarchy with a non-zero bus
 323          * number.
 324          */
 325         for (bus = 1; bus <= PCI_BUSMAX; bus++) {
 326                 if (pci_bus_configured(bus)) {
 327                         EPRINTLN("MPtable is incompatible with "
 328                             "multiple PCI hierarchies.");
 329                         EPRINTLN("MPtable generation can be disabled "
 330                             "by passing the -Y option to bhyve(8).");
 331                         return (EINVAL);
 332                 }
 333         }
 334
 335         curraddr = startaddr;
 336         mpfp = (mpfps_t)curraddr;
 337         mpt_build_mpfp(mpfp, MPTABLE_BASE);
 338         curraddr += sizeof(*mpfp);
 339
 340         mpch = (mpcth_t)curraddr;
 341         mpt_build_mpch(mpch);
 342         curraddr += sizeof(*mpch);
 343
 344         mpep = (proc_entry_ptr)curraddr;
 345         mpt_build_proc_entries(mpep, ncpu);
 346         curraddr += sizeof(*mpep) * ncpu;
 347         mpch->entry_count += ncpu;
 348
 349         mpeb = (bus_entry_ptr) curraddr;
 350         mpt_build_bus_entries(mpeb);
 351         curraddr += sizeof(*mpeb) * MPE_NUM_BUSES;
 352         mpch->entry_count += MPE_NUM_BUSES;
 353
 354         mpei = (io_apic_entry_ptr)curraddr;
 355         mpt_build_ioapic_entries(mpei, 0);
 356         curraddr += sizeof(*mpei);
 357         mpch->entry_count++;
 358
 359         mpie = (int_entry_ptr) curraddr;
 360         ioints = mpt_count_ioint_entries();
 361         mpt_build_ioint_entries(mpie, 0);
 362         curraddr += sizeof(*mpie) * ioints;
 363         mpch->entry_count += ioints;
 364
 365         mpie = (int_entry_ptr)curraddr;
 366         mpt_build_localint_entries(mpie);
 367         curraddr += sizeof(*mpie) * MPEII_NUM_LOCAL_IRQ;
 368         mpch->entry_count += MPEII_NUM_LOCAL_IRQ;
 369
 370         if (oem_tbl_start) {
 371                 mpch->oem_table_pointer = curraddr - startaddr + MPTABLE_BASE;
 372                 mpch->oem_table_size = oem_tbl_size;
 373                 memcpy(curraddr, oem_tbl_start, oem_tbl_size);
 374         }
 375
 376         mpch->base_table_length = curraddr - (char *)mpch;
 377         mpch->checksum = mpt_compute_checksum(mpch, mpch->base_table_length);
 378
 379         return (0);
 380 }