4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
30 * Copyright (c) 2012, Joyent, Inc. All rights reserved.
31 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
34 #include <sys/types.h>
35 #include <sys/thread.h>
36 #include <sys/cpuvar.h>
38 #include <sys/t_lock.h>
39 #include <sys/param.h>
42 #include <sys/class.h>
43 #include <sys/cmn_err.h>
44 #include <sys/debug.h>
46 #include <sys/asm_linkage.h>
47 #include <sys/x_call.h>
48 #include <sys/systm.h>
50 #include <sys/vtrace.h>
53 #include <vm/seg_kmem.h>
54 #include <vm/seg_kp.h>
55 #include <sys/segments.h>
57 #include <sys/stack.h>
58 #include <sys/smp_impldefs.h>
59 #include <sys/x86_archext.h>
60 #include <sys/machsystm.h>
61 #include <sys/traptrace.h>
62 #include <sys/clock.h>
63 #include <sys/cpc_impl.h>
66 #include <sys/dtrace.h>
67 #include <sys/archsystm.h>
69 #include <sys/reboot.h>
70 #include <sys/kdi_machimpl.h>
71 #include <vm/hat_i86.h>
72 #include <vm/vm_dep.h>
73 #include <sys/memnode.h>
74 #include <sys/pci_cfgspace.h>
75 #include <sys/mach_mmu.h>
76 #include <sys/sysmacros.h>
78 #include <sys/hypervisor.h>
80 #include <sys/cpu_module.h>
81 #include <sys/ontrap.h>
83 struct cpu cpus
[1]; /* CPU data */
84 struct cpu
*cpu
[NCPU
] = {&cpus
[0]}; /* pointers to all CPUs */
85 struct cpu
*cpu_free_list
; /* list for released CPUs */
86 cpu_core_t cpu_core
[NCPU
]; /* cpu_core structures */
88 #define cpu_next_free cpu_prev
91 * Useful for disabling MP bring-up on a MP capable system.
96 * to be set by a PSM to indicate what cpus
97 * are sitting around on the system.
102 * This variable is used by the hat layer to decide whether or not
103 * critical sections are needed to prevent race conditions. For sun4m,
104 * this variable is set once enough MP initialization has been done in
105 * order to allow cross calls.
107 int flushes_require_xcalls
;
109 cpuset_t cpu_ready_set
; /* initialized in startup() */
111 static void mp_startup_boot(void);
112 static void mp_startup_hotplug(void);
114 static void cpu_sep_enable(void);
115 static void cpu_sep_disable(void);
116 static void cpu_asysc_enable(void);
117 static void cpu_asysc_disable(void);
120 * Init CPU info - get CPU type info for processor_info system call.
123 init_cpu_info(struct cpu
*cp
)
125 processor_info_t
*pi
= &cp
->cpu_type_info
;
128 * Get clock-frequency property for the CPU.
130 pi
->pi_clock
= cpu_freq
;
133 * Current frequency in Hz.
135 cp
->cpu_curr_clock
= cpu_freq_hz
;
138 * Supported frequencies.
140 if (cp
->cpu_supp_freqs
== NULL
) {
141 cpu_set_supp_freqs(cp
, NULL
);
144 (void) strcpy(pi
->pi_processor_type
, "i386");
146 (void) strcpy(pi
->pi_fputypes
, "i387 compatible");
148 cp
->cpu_idstr
= kmem_zalloc(CPU_IDSTRLEN
, KM_SLEEP
);
149 cp
->cpu_brandstr
= kmem_zalloc(CPU_IDSTRLEN
, KM_SLEEP
);
152 * If called for the BSP, cp is equal to current CPU.
153 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
154 * of current CPU as default values for cpu_idstr and cpu_brandstr.
155 * They will be corrected in mp_startup_common() after cpuid_pass1()
156 * has been invoked on target CPU.
158 (void) cpuid_getidstr(CPU
, cp
->cpu_idstr
, CPU_IDSTRLEN
);
159 (void) cpuid_getbrandstr(CPU
, cp
->cpu_brandstr
, CPU_IDSTRLEN
);
163 * Configure syscall support on this CPU.
167 init_cpu_syscall(struct cpu
*cp
)
172 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
173 is_x86_feature(x86_featureset
, X86FSET_ASYSC
)) {
177 * The syscall instruction imposes a certain ordering on
178 * segment selectors, so we double-check that ordering
181 ASSERT(KDS_SEL
== KCS_SEL
+ 8);
182 ASSERT(UDS_SEL
== U32CS_SEL
+ 8);
183 ASSERT(UCS_SEL
== U32CS_SEL
+ 16);
186 * Turn syscall/sysret extensions on.
191 * Program the magic registers ..
194 ((uint64_t)(U32CS_SEL
<< 16 | KCS_SEL
)) << 32);
195 wrmsr(MSR_AMD_LSTAR
, (uint64_t)(uintptr_t)sys_syscall
);
196 wrmsr(MSR_AMD_CSTAR
, (uint64_t)(uintptr_t)sys_syscall32
);
199 * This list of flags is masked off the incoming
200 * %rfl when we enter the kernel.
202 wrmsr(MSR_AMD_SFMASK
, (uint64_t)(uintptr_t)(PS_IE
| PS_T
));
207 * On 32-bit kernels, we use sysenter/sysexit because it's too
208 * hard to use syscall/sysret, and it is more portable anyway.
210 * On 64-bit kernels on Nocona machines, the 32-bit syscall
211 * variant isn't available to 32-bit applications, but sysenter is.
213 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
214 is_x86_feature(x86_featureset
, X86FSET_SEP
)) {
218 * The sysenter instruction imposes a certain ordering on
219 * segment selectors, so we double-check that ordering
220 * here. See "sysenter" in Intel document 245471-012, "IA-32
221 * Intel Architecture Software Developer's Manual Volume 2:
222 * Instruction Set Reference"
224 ASSERT(KDS_SEL
== KCS_SEL
+ 8);
226 ASSERT32(UCS_SEL
== ((KCS_SEL
+ 16) | 3));
227 ASSERT32(UDS_SEL
== UCS_SEL
+ 8);
229 ASSERT64(U32CS_SEL
== ((KCS_SEL
+ 16) | 3));
230 ASSERT64(UDS_SEL
== U32CS_SEL
+ 8);
236 * resume() sets this value to the base of the threads stack
237 * via a context handler.
239 wrmsr(MSR_INTC_SEP_ESP
, 0);
240 wrmsr(MSR_INTC_SEP_EIP
, (uint64_t)(uintptr_t)sys_sysenter
);
247 * Multiprocessor initialization.
249 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
250 * startup and idle threads for the specified CPU.
251 * Parameter boot is true for boot time operations and is false for CPU
255 mp_cpu_configure_common(int cpun
, boolean_t boot
)
262 extern int idle_cpu_prefer_mwait
;
263 extern void cpu_idle_mwait();
266 extern void cpu_idle();
269 trap_trace_ctl_t
*ttc
= &trap_trace_ctl
[cpun
];
272 ASSERT(MUTEX_HELD(&cpu_lock
));
273 ASSERT(cpun
< NCPU
&& cpu
[cpun
] == NULL
);
275 if (cpu_free_list
== NULL
) {
276 cp
= kmem_zalloc(sizeof (*cp
), KM_SLEEP
);
279 cpu_free_list
= cp
->cpu_next_free
;
282 cp
->cpu_m
.mcpu_istamp
= cpun
<< 16;
284 /* Create per CPU specific threads in the process p0. */
288 * Initialize the dispatcher first.
292 cpu_vm_data_init(cp
);
295 * Allocate and initialize the startup thread for this CPU.
296 * Interrupt and process switch stacks get allocated later
297 * when the CPU starts running.
299 tp
= thread_create(NULL
, 0, NULL
, NULL
, 0, procp
,
300 TS_STOPPED
, maxclsyspri
);
303 * Set state to TS_ONPROC since this thread will start running
304 * as soon as the CPU comes online.
306 * All the other fields of the thread structure are setup by
309 THREAD_ONPROC(tp
, cp
);
311 tp
->t_bound_cpu
= cp
;
312 tp
->t_affinitycnt
= 1;
314 tp
->t_disp_queue
= cp
->cpu_disp
;
317 * Setup thread to start in mp_startup_common.
320 tp
->t_sp
= (uintptr_t)(sp
- MINFRAME
);
322 tp
->t_sp
-= STACK_ENTRY_ALIGN
; /* fake a call */
325 * Setup thread start entry point for boot or hotplug.
328 tp
->t_pc
= (uintptr_t)mp_startup_boot
;
330 tp
->t_pc
= (uintptr_t)mp_startup_hotplug
;
337 cp
->cpu_dispthread
= tp
;
338 cp
->cpu_dispatch_pri
= DISP_PRIO(tp
);
341 * cpu_base_spl must be set explicitly here to prevent any blocking
342 * operations in mp_startup_common from causing the spl of the cpu
343 * to drop to 0 (allowing device interrupts before we're ready) in
345 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
346 * As an extra bit of security on DEBUG kernels, this is enforced with
347 * an assertion in mp_startup_common() -- before cpu_base_spl is set
348 * to its proper value.
350 cp
->cpu_base_spl
= ipltospl(LOCK_LEVEL
);
353 * Now, initialize per-CPU idle thread for this CPU.
355 tp
= thread_create(NULL
, PAGESIZE
, idle
, NULL
, 0, procp
, TS_ONPROC
, -1);
357 cp
->cpu_idle_thread
= tp
;
360 tp
->t_bound_cpu
= cp
;
361 tp
->t_affinitycnt
= 1;
363 tp
->t_disp_queue
= cp
->cpu_disp
;
366 * Bootstrap the CPU's PG data
368 pg_cpu_bootstrap(cp
);
371 * Perform CPC initialization on the new CPU.
376 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
379 setup_vaddr_for_ppcopy(cp
);
382 * Allocate page for new GDT and initialize from current GDT.
385 ASSERT((sizeof (*cp
->cpu_gdt
) * NGDT
) <= PAGESIZE
);
387 cp
->cpu_gdt
= kmem_zalloc(PAGESIZE
, KM_SLEEP
);
388 bcopy(CPU
->cpu_gdt
, cp
->cpu_gdt
, (sizeof (*cp
->cpu_gdt
) * NGDT
));
394 set_usegd(&cp
->cpu_gdt
[GDT_GS
], cp
, sizeof (struct cpu
) -1, SDT_MEMRWA
,
399 * If we have more than one node, each cpu gets a copy of IDT
400 * local to its node. If this is a Pentium box, we use cpu 0's
401 * IDT. cpu 0's IDT has been made read-only to workaround the
402 * cmpxchgl register bug
404 if (system_hardware
.hd_nodes
&& x86_type
!= X86_TYPE_P5
) {
406 ASSERT((sizeof (*CPU
->cpu_idt
) * NIDT
) <= PAGESIZE
);
408 cp
->cpu_idt
= kmem_zalloc(PAGESIZE
, KM_SLEEP
);
409 bcopy(CPU
->cpu_idt
, cp
->cpu_idt
, PAGESIZE
);
411 cp
->cpu_idt
= CPU
->cpu_idt
;
415 * Get interrupt priority data from cpu 0.
417 cp
->cpu_pri_data
= CPU
->cpu_pri_data
;
420 * alloc space for cpuid info
422 cpuid_alloc_space(cp
);
424 if (is_x86_feature(x86_featureset
, X86FSET_MWAIT
) &&
425 idle_cpu_prefer_mwait
) {
426 cp
->cpu_m
.mcpu_mwait
= cpuid_mwait_alloc(cp
);
427 cp
->cpu_m
.mcpu_idle_cpu
= cpu_idle_mwait
;
430 cp
->cpu_m
.mcpu_idle_cpu
= cpu_idle
;
435 * alloc space for ucode_info
437 ucode_alloc_space(cp
);
443 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
445 ttc
->ttc_first
= (uintptr_t)kmem_zalloc(trap_trace_bufsize
, KM_SLEEP
);
446 ttc
->ttc_next
= ttc
->ttc_first
;
447 ttc
->ttc_limit
= ttc
->ttc_first
+ trap_trace_bufsize
;
451 * Record that we have another CPU.
454 * Initialize the interrupt threads for this CPU
456 cpu_intr_alloc(cp
, NINTR_THREADS
);
458 cp
->cpu_flags
= CPU_OFFLINE
| CPU_QUIESCED
| CPU_POWEROFF
;
462 * Add CPU to list of available CPUs. It'll be on the active list
463 * after mp_startup_common().
471 * Undo what was done in mp_cpu_configure_common
474 mp_cpu_unconfigure_common(struct cpu
*cp
, int error
)
476 ASSERT(MUTEX_HELD(&cpu_lock
));
479 * Remove the CPU from the list of available CPUs.
481 cpu_del_unit(cp
->cpu_id
);
483 if (error
== ETIMEDOUT
) {
485 * The cpu was started, but never *seemed* to run any
486 * code in the kernel; it's probably off spinning in its
487 * own private world, though with potential references to
488 * our kmem-allocated IDTs and GDTs (for example).
490 * Worse still, it may actually wake up some time later,
491 * so rather than guess what it might or might not do, we
492 * leave the fundamental data structures intact.
499 * At this point, the only threads bound to this CPU should
500 * special per-cpu threads: it's idle thread, it's pause threads,
501 * and it's interrupt threads. Clean these up.
503 cpu_destroy_bound_threads(cp
);
504 cp
->cpu_idle_thread
= NULL
;
507 * Free the interrupt stack.
510 cp
->cpu_intr_stack
- (INTR_STACK_SIZE
- SA(MINFRAME
)));
511 cp
->cpu_intr_stack
= NULL
;
515 * Discard the trap trace buffer
518 trap_trace_ctl_t
*ttc
= &trap_trace_ctl
[cp
->cpu_id
];
520 kmem_free((void *)ttc
->ttc_first
, trap_trace_bufsize
);
521 ttc
->ttc_first
= NULL
;
527 ucode_free_space(cp
);
529 /* Free CPU ID string and brand string. */
531 kmem_free(cp
->cpu_idstr
, CPU_IDSTRLEN
);
532 cp
->cpu_idstr
= NULL
;
534 if (cp
->cpu_brandstr
) {
535 kmem_free(cp
->cpu_brandstr
, CPU_IDSTRLEN
);
536 cp
->cpu_brandstr
= NULL
;
540 if (cp
->cpu_m
.mcpu_mwait
!= NULL
) {
541 cpuid_mwait_free(cp
);
542 cp
->cpu_m
.mcpu_mwait
= NULL
;
545 cpuid_free_space(cp
);
547 if (cp
->cpu_idt
!= CPU
->cpu_idt
)
548 kmem_free(cp
->cpu_idt
, PAGESIZE
);
551 kmem_free(cp
->cpu_gdt
, PAGESIZE
);
554 if (cp
->cpu_supp_freqs
!= NULL
) {
555 size_t len
= strlen(cp
->cpu_supp_freqs
) + 1;
556 kmem_free(cp
->cpu_supp_freqs
, len
);
557 cp
->cpu_supp_freqs
= NULL
;
560 teardown_vaddr_for_ppcopy(cp
);
564 cp
->cpu_dispthread
= NULL
;
565 cp
->cpu_thread
= NULL
; /* discarded by cpu_destroy_bound_threads() */
567 cpu_vm_data_destroy(cp
);
573 bzero(cp
, sizeof (*cp
));
574 cp
->cpu_next_free
= cpu_free_list
;
579 * Apply workarounds for known errata, and warn about those that are absent.
581 * System vendors occasionally create configurations which contain different
582 * revisions of the CPUs that are almost but not exactly the same. At the
583 * time of writing, this meant that their clock rates were the same, their
584 * feature sets were the same, but the required workaround were -not-
585 * necessarily the same. So, this routine is invoked on -every- CPU soon
586 * after starting to make sure that the resulting system contains the most
587 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
590 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
591 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
592 * prior to acknowledging their readiness to the master, so this routine will
593 * never be executed by multiple CPUs in parallel, thus making updates to
596 * These workarounds are based on Rev 3.57 of the Revision Guide for
597 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
600 #if defined(OPTERON_ERRATUM_88)
601 int opteron_erratum_88
; /* if non-zero -> at least one cpu has it */
604 #if defined(OPTERON_ERRATUM_91)
605 int opteron_erratum_91
; /* if non-zero -> at least one cpu has it */
608 #if defined(OPTERON_ERRATUM_93)
609 int opteron_erratum_93
; /* if non-zero -> at least one cpu has it */
612 #if defined(OPTERON_ERRATUM_95)
613 int opteron_erratum_95
; /* if non-zero -> at least one cpu has it */
616 #if defined(OPTERON_ERRATUM_100)
617 int opteron_erratum_100
; /* if non-zero -> at least one cpu has it */
620 #if defined(OPTERON_ERRATUM_108)
621 int opteron_erratum_108
; /* if non-zero -> at least one cpu has it */
624 #if defined(OPTERON_ERRATUM_109)
625 int opteron_erratum_109
; /* if non-zero -> at least one cpu has it */
628 #if defined(OPTERON_ERRATUM_121)
629 int opteron_erratum_121
; /* if non-zero -> at least one cpu has it */
632 #if defined(OPTERON_ERRATUM_122)
633 int opteron_erratum_122
; /* if non-zero -> at least one cpu has it */
636 #if defined(OPTERON_ERRATUM_123)
637 int opteron_erratum_123
; /* if non-zero -> at least one cpu has it */
640 #if defined(OPTERON_ERRATUM_131)
641 int opteron_erratum_131
; /* if non-zero -> at least one cpu has it */
644 #if defined(OPTERON_WORKAROUND_6336786)
645 int opteron_workaround_6336786
; /* non-zero -> WA relevant and applied */
646 int opteron_workaround_6336786_UP
= 0; /* Not needed for UP */
649 #if defined(OPTERON_WORKAROUND_6323525)
650 int opteron_workaround_6323525
; /* if non-zero -> at least one cpu has it */
653 #if defined(OPTERON_ERRATUM_298)
654 int opteron_erratum_298
;
657 #if defined(OPTERON_ERRATUM_721)
658 int opteron_erratum_721
;
662 workaround_warning(cpu_t
*cp
, uint_t erratum
)
664 cmn_err(CE_WARN
, "cpu%d: no workaround for erratum %u",
665 cp
->cpu_id
, erratum
);
669 workaround_applied(uint_t erratum
)
671 if (erratum
> 1000000)
672 cmn_err(CE_CONT
, "?workaround applied for cpu issue #%d\n",
675 cmn_err(CE_CONT
, "?workaround applied for cpu erratum #%d\n",
680 msr_warning(cpu_t
*cp
, const char *rw
, uint_t msr
, int error
)
682 cmn_err(CE_WARN
, "cpu%d: couldn't %smsr 0x%x, error %d",
683 cp
->cpu_id
, rw
, msr
, error
);
687 * Determine the number of nodes in a Hammer / Greyhound / Griffin family
691 opteron_get_nnodes(void)
693 static uint_t nnodes
= 0;
700 * This routine uses a PCI config space based mechanism
701 * for retrieving the number of nodes in the system.
702 * Device 24, function 0, offset 0x60 as used here is not
703 * AMD processor architectural, and may not work on processor
704 * families other than those listed below.
706 * Callers of this routine must ensure that we're running on
707 * a processor which supports this mechanism.
708 * The assertion below is meant to catch calls on unsupported
711 family
= cpuid_getfamily(CPU
);
712 ASSERT(family
== 0xf || family
== 0x10 || family
== 0x11);
716 * Obtain the number of nodes in the system from
717 * bits [6:4] of the Node ID register on node 0.
719 * The actual node count is NodeID[6:4] + 1
721 * The Node ID register is accessed via function 0,
722 * offset 0x60. Node 0 is device 24.
724 nnodes
= ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
730 do_erratum_298(struct cpu
*cpu
)
732 static int osvwrc
= -3;
733 extern int osvw_opteron_erratum(cpu_t
*, uint_t
);
736 * L2 Eviction May Occur During Processor Operation To Set
737 * Accessed or Dirty Bit.
740 osvwrc
= osvw_opteron_erratum(cpu
, 298);
742 /* osvw return codes should be consistent for all cpus */
743 ASSERT(osvwrc
== osvw_opteron_erratum(cpu
, 298));
747 case 0: /* erratum is not present: do nothing */
749 case 1: /* erratum is present: BIOS workaround applied */
751 * check if workaround is actually in place and issue warning
754 if (((rdmsr(MSR_AMD_HWCR
) & AMD_HWCR_TLBCACHEDIS
) == 0) ||
755 ((rdmsr(MSR_AMD_BU_CFG
) & AMD_BU_CFG_E298
) == 0)) {
756 #if defined(OPTERON_ERRATUM_298)
757 opteron_erratum_298
++;
759 workaround_warning(cpu
, 298);
764 case -1: /* cannot determine via osvw: check cpuid */
765 if ((cpuid_opteron_erratum(cpu
, 298) > 0) &&
766 (((rdmsr(MSR_AMD_HWCR
) & AMD_HWCR_TLBCACHEDIS
) == 0) ||
767 ((rdmsr(MSR_AMD_BU_CFG
) & AMD_BU_CFG_E298
) == 0))) {
768 #if defined(OPTERON_ERRATUM_298)
769 opteron_erratum_298
++;
771 workaround_warning(cpu
, 298);
781 workaround_errata(struct cpu
*cpu
)
788 if (cpuid_opteron_erratum(cpu
, 88) > 0) {
790 * SWAPGS May Fail To Read Correct GS Base
792 #if defined(OPTERON_ERRATUM_88)
794 * The workaround is an mfence in the relevant assembler code
796 opteron_erratum_88
++;
798 workaround_warning(cpu
, 88);
803 if (cpuid_opteron_erratum(cpu
, 91) > 0) {
805 * Software Prefetches May Report A Page Fault
807 #if defined(OPTERON_ERRATUM_91)
811 opteron_erratum_91
++;
813 workaround_warning(cpu
, 91);
818 if (cpuid_opteron_erratum(cpu
, 93) > 0) {
820 * RSM Auto-Halt Restart Returns to Incorrect RIP
822 #if defined(OPTERON_ERRATUM_93)
826 opteron_erratum_93
++;
828 workaround_warning(cpu
, 93);
834 if (cpuid_opteron_erratum(cpu
, 95) > 0) {
836 * RET Instruction May Return to Incorrect EIP
838 #if defined(OPTERON_ERRATUM_95)
841 * Workaround this by ensuring that 32-bit user code and
842 * 64-bit kernel code never occupy the same address
845 if (_userlimit32
> 0xc0000000ul
)
846 *(uintptr_t *)&_userlimit32
= 0xc0000000ul
;
849 ASSERT((uint32_t)COREHEAP_BASE
== 0xc0000000u
);
850 opteron_erratum_95
++;
853 workaround_warning(cpu
, 95);
858 if (cpuid_opteron_erratum(cpu
, 100) > 0) {
860 * Compatibility Mode Branches Transfer to Illegal Address
862 #if defined(OPTERON_ERRATUM_100)
866 opteron_erratum_100
++;
868 workaround_warning(cpu
, 100);
874 if (cpuid_opteron_erratum(cpu
, 108) > 0) {
876 * CPUID Instruction May Return Incorrect Model Number In
879 #if defined(OPTERON_ERRATUM_108)
881 * (Our cpuid-handling code corrects the model number on
885 workaround_warning(cpu
, 108);
891 if (cpuid_opteron_erratum(cpu
, 109) > 0) do {
893 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
895 #if defined(OPTERON_ERRATUM_109)
897 * The "workaround" is to print a warning to upgrade the BIOS
900 const uint_t msr
= MSR_AMD_PATCHLEVEL
;
903 if ((err
= checked_rdmsr(msr
, &value
)) != 0) {
904 msr_warning(cpu
, "rd", msr
, err
);
905 workaround_warning(cpu
, 109);
909 opteron_erratum_109
++;
911 workaround_warning(cpu
, 109);
914 /*CONSTANTCONDITION*/
918 if (cpuid_opteron_erratum(cpu
, 121) > 0) {
920 * Sequential Execution Across Non_Canonical Boundary Caused
923 #if defined(OPTERON_ERRATUM_121)
926 * Erratum 121 is only present in long (64 bit) mode.
927 * Workaround is to include the page immediately before the
928 * va hole to eliminate the possibility of system hangs due to
929 * sequential execution across the va hole boundary.
931 if (opteron_erratum_121
)
932 opteron_erratum_121
++;
935 hole_start
-= PAGESIZE
;
938 * hole_start not yet initialized by
939 * mmu_init. Initialize hole_start
940 * with value to be subtracted.
942 hole_start
= PAGESIZE
;
944 opteron_erratum_121
++;
948 workaround_warning(cpu
, 121);
954 if (cpuid_opteron_erratum(cpu
, 122) > 0) do {
956 * TLB Flush Filter May Cause Coherency Problem in
957 * Multiprocessor Systems
959 #if defined(OPTERON_ERRATUM_122)
961 const uint_t msr
= MSR_AMD_HWCR
;
965 * Erratum 122 is only present in MP configurations (multi-core
966 * or multi-processor).
969 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
971 if (!opteron_erratum_122
&& xpv_nr_phys_cpus() == 1)
974 if (!opteron_erratum_122
&& opteron_get_nnodes() == 1 &&
975 cpuid_get_ncpu_per_chip(cpu
) == 1)
978 /* disable TLB Flush Filter */
980 if ((error
= checked_rdmsr(msr
, &value
)) != 0) {
981 msr_warning(cpu
, "rd", msr
, error
);
982 workaround_warning(cpu
, 122);
985 value
|= (uint64_t)AMD_HWCR_FFDIS
;
986 if ((error
= checked_wrmsr(msr
, value
)) != 0) {
987 msr_warning(cpu
, "wr", msr
, error
);
988 workaround_warning(cpu
, 122);
992 opteron_erratum_122
++;
994 workaround_warning(cpu
, 122);
997 /*CONSTANTCONDITION*/
1001 if (cpuid_opteron_erratum(cpu
, 123) > 0) do {
1003 * Bypassed Reads May Cause Data Corruption of System Hang in
1004 * Dual Core Processors
1006 #if defined(OPTERON_ERRATUM_123)
1008 const uint_t msr
= MSR_AMD_PATCHLEVEL
;
1012 * Erratum 123 applies only to multi-core cpus.
1014 if (cpuid_get_ncpu_per_chip(cpu
) < 2)
1017 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
1021 * The "workaround" is to print a warning to upgrade the BIOS
1023 if ((err
= checked_rdmsr(msr
, &value
)) != 0) {
1024 msr_warning(cpu
, "rd", msr
, err
);
1025 workaround_warning(cpu
, 123);
1029 opteron_erratum_123
++;
1031 workaround_warning(cpu
, 123);
1035 /*CONSTANTCONDITION*/
1039 if (cpuid_opteron_erratum(cpu
, 131) > 0) do {
1041 * Multiprocessor Systems with Four or More Cores May Deadlock
1042 * Waiting for a Probe Response
1044 #if defined(OPTERON_ERRATUM_131)
1046 const uint_t msr
= MSR_AMD_NB_CFG
;
1047 const uint64_t wabits
=
1048 AMD_NB_CFG_SRQ_HEARTBEAT
| AMD_NB_CFG_SRQ_SPR
;
1052 * Erratum 131 applies to any system with four or more cores.
1054 if (opteron_erratum_131
)
1057 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
1059 if (xpv_nr_phys_cpus() < 4)
1062 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu
) < 4)
1066 * Print a warning if neither of the workarounds for
1067 * erratum 131 is present.
1069 if ((error
= checked_rdmsr(msr
, &nbcfg
)) != 0) {
1070 msr_warning(cpu
, "rd", msr
, error
);
1071 workaround_warning(cpu
, 131);
1073 } else if ((nbcfg
& wabits
) == 0) {
1074 opteron_erratum_131
++;
1076 /* cannot have both workarounds set */
1077 ASSERT((nbcfg
& wabits
) != wabits
);
1080 workaround_warning(cpu
, 131);
1083 /*CONSTANTCONDITION*/
1087 * This isn't really an erratum, but for convenience the
1088 * detection/workaround code lives here and in cpuid_opteron_erratum.
1090 if (cpuid_opteron_erratum(cpu
, 6336786) > 0) {
1091 #if defined(OPTERON_WORKAROUND_6336786)
1093 * Disable C1-Clock ramping on multi-core/multi-processor
1094 * K8 platforms to guard against TSC drift.
1096 if (opteron_workaround_6336786
) {
1097 opteron_workaround_6336786
++;
1099 } else if ((DOMAIN_IS_INITDOMAIN(xen_info
) &&
1100 xpv_nr_phys_cpus() > 1) ||
1101 opteron_workaround_6336786_UP
) {
1103 * XXPV Hmm. We can't walk the Northbridges on
1104 * the hypervisor; so just complain and drive
1105 * on. This probably needs to be fixed in
1106 * the hypervisor itself.
1108 opteron_workaround_6336786
++;
1109 workaround_warning(cpu
, 6336786);
1111 } else if ((opteron_get_nnodes() *
1112 cpuid_get_ncpu_per_chip(cpu
) > 1) ||
1113 opteron_workaround_6336786_UP
) {
1115 uint_t node
, nnodes
;
1118 nnodes
= opteron_get_nnodes();
1119 for (node
= 0; node
< nnodes
; node
++) {
1121 * Clear PMM7[1:0] (function 3, offset 0x87)
1122 * Northbridge device is the node id + 24.
1124 data
= pci_getb_func(0, node
+ 24, 3, 0x87);
1126 pci_putb_func(0, node
+ 24, 3, 0x87, data
);
1128 opteron_workaround_6336786
++;
1132 workaround_warning(cpu
, 6336786);
1139 * Mutex primitives don't work as expected.
1141 if (cpuid_opteron_erratum(cpu
, 6323525) > 0) {
1142 #if defined(OPTERON_WORKAROUND_6323525)
1144 * This problem only occurs with 2 or more cores. If bit in
1145 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1146 * is to patch the semaphone routines with the lfence
1147 * instruction to provide necessary load memory barrier with
1148 * possible subsequent read-modify-write ops.
1150 * It is too early in boot to call the patch routine so
1151 * set erratum variable to be done in startup_end().
1153 if (opteron_workaround_6323525
) {
1154 opteron_workaround_6323525
++;
1156 } else if (is_x86_feature(x86_featureset
, X86FSET_SSE2
)) {
1157 if (DOMAIN_IS_INITDOMAIN(xen_info
)) {
1159 * XXPV Use dom0_msr here when extended
1160 * operations are supported?
1162 if (xpv_nr_phys_cpus() > 1)
1163 opteron_workaround_6323525
++;
1166 * We have no way to tell how many physical
1167 * cpus there are, or even if this processor
1168 * has the problem, so enable the workaround
1169 * unconditionally (at some performance cost).
1171 opteron_workaround_6323525
++;
1174 } else if (is_x86_feature(x86_featureset
, X86FSET_SSE2
) &&
1175 ((opteron_get_nnodes() *
1176 cpuid_get_ncpu_per_chip(cpu
)) > 1)) {
1177 if ((xrdmsr(MSR_AMD_BU_CFG
) & (UINT64_C(1) << 33)) == 0)
1178 opteron_workaround_6323525
++;
1182 workaround_warning(cpu
, 6323525);
1187 missing
+= do_erratum_298(cpu
);
1189 if (cpuid_opteron_erratum(cpu
, 721) > 0) {
1190 #if defined(OPTERON_ERRATUM_721)
1193 if (!on_trap(&otd
, OT_DATA_ACCESS
))
1194 wrmsr(MSR_AMD_DE_CFG
,
1195 rdmsr(MSR_AMD_DE_CFG
) | AMD_DE_CFG_E721
);
1198 opteron_erratum_721
++;
1200 workaround_warning(cpu
, 721);
1213 workaround_errata_end()
1215 #if defined(OPTERON_ERRATUM_88)
1216 if (opteron_erratum_88
)
1217 workaround_applied(88);
1219 #if defined(OPTERON_ERRATUM_91)
1220 if (opteron_erratum_91
)
1221 workaround_applied(91);
1223 #if defined(OPTERON_ERRATUM_93)
1224 if (opteron_erratum_93
)
1225 workaround_applied(93);
1227 #if defined(OPTERON_ERRATUM_95)
1228 if (opteron_erratum_95
)
1229 workaround_applied(95);
1231 #if defined(OPTERON_ERRATUM_100)
1232 if (opteron_erratum_100
)
1233 workaround_applied(100);
1235 #if defined(OPTERON_ERRATUM_108)
1236 if (opteron_erratum_108
)
1237 workaround_applied(108);
1239 #if defined(OPTERON_ERRATUM_109)
1240 if (opteron_erratum_109
) {
1242 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1243 " processor\nerratum 109 was not detected; updating your"
1244 " system's BIOS to a version\ncontaining this"
1245 " microcode patch is HIGHLY recommended or erroneous"
1246 " system\noperation may occur.\n");
1249 #if defined(OPTERON_ERRATUM_121)
1250 if (opteron_erratum_121
)
1251 workaround_applied(121);
1253 #if defined(OPTERON_ERRATUM_122)
1254 if (opteron_erratum_122
)
1255 workaround_applied(122);
1257 #if defined(OPTERON_ERRATUM_123)
1258 if (opteron_erratum_123
) {
1260 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1261 " processor\nerratum 123 was not detected; updating your"
1262 " system's BIOS to a version\ncontaining this"
1263 " microcode patch is HIGHLY recommended or erroneous"
1264 " system\noperation may occur.\n");
1267 #if defined(OPTERON_ERRATUM_131)
1268 if (opteron_erratum_131
) {
1270 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1271 " processor\nerratum 131 was not detected; updating your"
1272 " system's BIOS to a version\ncontaining this"
1273 " microcode patch is HIGHLY recommended or erroneous"
1274 " system\noperation may occur.\n");
1277 #if defined(OPTERON_WORKAROUND_6336786)
1278 if (opteron_workaround_6336786
)
1279 workaround_applied(6336786);
1281 #if defined(OPTERON_WORKAROUND_6323525)
1282 if (opteron_workaround_6323525
)
1283 workaround_applied(6323525);
1285 #if defined(OPTERON_ERRATUM_298)
1286 if (opteron_erratum_298
) {
1288 "BIOS microcode patch for AMD 64/Opteron(tm)"
1289 " processor\nerratum 298 was not detected; updating your"
1290 " system's BIOS to a version\ncontaining this"
1291 " microcode patch is HIGHLY recommended or erroneous"
1292 " system\noperation may occur.\n");
1295 #if defined(OPTERON_ERRATUM_721)
1296 if (opteron_erratum_721
)
1297 workaround_applied(721);
1302 * The procset_slave and procset_master are used to synchronize
1303 * between the control CPU and the target CPU when starting CPUs.
1305 static cpuset_t procset_slave
, procset_master
;
1308 mp_startup_wait(cpuset_t
*sp
, processorid_t cpuid
)
1312 for (tempset
= *sp
; !CPU_IN_SET(tempset
, cpuid
);
1313 tempset
= *(volatile cpuset_t
*)sp
) {
1316 CPUSET_ATOMIC_DEL(*(cpuset_t
*)sp
, cpuid
);
1320 mp_startup_signal(cpuset_t
*sp
, processorid_t cpuid
)
1324 CPUSET_ATOMIC_ADD(*(cpuset_t
*)sp
, cpuid
);
1325 for (tempset
= *sp
; CPU_IN_SET(tempset
, cpuid
);
1326 tempset
= *(volatile cpuset_t
*)sp
) {
1332 mp_start_cpu_common(cpu_t
*cp
, boolean_t boot
)
1334 _NOTE(ARGUNUSED(boot
));
1340 processorid_t cpuid
;
1342 extern void cpupm_init(cpu_t
*);
1347 ctx
= mach_cpucontext_alloc(cp
);
1350 "cpu%d: failed to allocate context", cp
->cpu_id
);
1353 error
= mach_cpu_start(cp
, ctx
);
1356 "cpu%d: failed to start, error %d", cp
->cpu_id
, error
);
1357 mach_cpucontext_free(cp
, ctx
, error
);
1361 for (delays
= 0, tempset
= procset_slave
; !CPU_IN_SET(tempset
, cpuid
);
1363 if (delays
== 500) {
1365 * After five seconds, things are probably looking
1366 * a bit bleak - explain the hang.
1368 cmn_err(CE_NOTE
, "cpu%d: started, "
1369 "but not running in the kernel yet", cpuid
);
1370 } else if (delays
> 2000) {
1372 * We waited at least 20 seconds, bail ..
1375 cmn_err(CE_WARN
, "cpu%d: timed out", cpuid
);
1376 mach_cpucontext_free(cp
, ctx
, error
);
1381 * wait at least 10ms, then check again..
1383 delay(USEC_TO_TICK_ROUNDUP(10000));
1384 tempset
= *((volatile cpuset_t
*)&procset_slave
);
1386 CPUSET_ATOMIC_DEL(procset_slave
, cpuid
);
1388 mach_cpucontext_free(cp
, ctx
, 0);
1391 if (tsc_gethrtime_enable
)
1392 tsc_sync_master(cpuid
);
1395 if (dtrace_cpu_init
!= NULL
) {
1396 (*dtrace_cpu_init
)(cpuid
);
1400 * During CPU DR operations, the cpu_lock is held by current
1401 * (the control) thread. We can't release the cpu_lock here
1402 * because that will break the CPU DR logic.
1403 * On the other hand, CPUPM and processor group initialization
1404 * routines need to access the cpu_lock. So we invoke those
1405 * routines here on behalf of mp_startup_common().
1407 * CPUPM and processor group initialization routines depend
1408 * on the cpuid probing results. Wait for mp_startup_common()
1409 * to signal that cpuid probing is done.
1411 mp_startup_wait(&procset_slave
, cpuid
);
1415 (void) pg_cpu_init(cp
, B_FALSE
);
1417 mp_startup_signal(&procset_master
, cpuid
);
1423 * Start a single cpu, assuming that the kernel context is available
1424 * to successfully start another cpu.
1426 * (For example, real mode code is mapped into the right place
1427 * in memory and is ready to be run.)
1430 start_cpu(processorid_t who
)
1439 * Check if there's at least a Mbyte of kmem available
1440 * before attempting to start the cpu.
1442 if (kmem_avail() < 1024 * 1024) {
1444 * Kick off a reap in case that helps us with
1452 * First configure cpu.
1454 cp
= mp_cpu_configure_common(who
, B_TRUE
);
1460 error
= mp_start_cpu_common(cp
, B_TRUE
);
1462 mp_cpu_unconfigure_common(cp
, error
);
1466 mutex_exit(&cpu_lock
);
1467 tempset
= cpu_ready_set
;
1468 while (!CPU_IN_SET(tempset
, who
)) {
1470 tempset
= *((volatile cpuset_t
*)&cpu_ready_set
);
1472 mutex_enter(&cpu_lock
);
1478 start_other_cpus(int cprboot
)
1480 _NOTE(ARGUNUSED(cprboot
));
1483 uint_t bootcpuid
= 0;
1486 * Initialize our own cpu_info.
1490 cmn_err(CE_CONT
, "?cpu%d: %s\n", CPU
->cpu_id
, CPU
->cpu_idstr
);
1491 cmn_err(CE_CONT
, "?cpu%d: %s\n", CPU
->cpu_id
, CPU
->cpu_brandstr
);
1494 * Initialize our syscall handlers
1496 init_cpu_syscall(CPU
);
1499 * Take the boot cpu out of the mp_cpus set because we know
1500 * it's already running. Add it to the cpu_ready_set for
1501 * precisely the same reason.
1503 CPUSET_DEL(mp_cpus
, bootcpuid
);
1504 CPUSET_ADD(cpu_ready_set
, bootcpuid
);
1507 * skip the rest of this if
1508 * . only 1 cpu dectected and system isn't hotplug-capable
1511 if ((CPUSET_ISNULL(mp_cpus
) && plat_dr_support_cpu() == 0) ||
1514 cmn_err(CE_CONT
, "?***** Not in MP mode\n");
1519 * perform such initialization as is needed
1520 * to be able to take CPUs on- and off-line.
1524 xc_init_cpu(CPU
); /* initialize processor crosscalls */
1526 if (mach_cpucontext_init() != 0)
1529 flushes_require_xcalls
= 1;
1532 * We lock our affinity to the master CPU to ensure that all slave CPUs
1533 * do their TSC syncs with the same CPU.
1535 affinity_set(CPU_CURRENT
);
1537 for (who
= 0; who
< NCPU
; who
++) {
1538 if (!CPU_IN_SET(mp_cpus
, who
))
1540 ASSERT(who
!= bootcpuid
);
1542 mutex_enter(&cpu_lock
);
1543 if (start_cpu(who
) != 0)
1544 CPUSET_DEL(mp_cpus
, who
);
1545 cpu_state_change_notify(who
, CPU_SETUP
);
1546 mutex_exit(&cpu_lock
);
1549 /* Free the space allocated to hold the microcode file */
1554 mach_cpucontext_fini();
1557 if (get_hwenv() == HW_NATIVE
)
1558 workaround_errata_end();
1559 cmi_post_mpstartup();
1561 if (use_mp
&& ncpus
!= boot_max_ncpus
) {
1563 "System detected %d cpus, but "
1564 "only %d cpu(s) were enabled during boot.",
1565 boot_max_ncpus
, ncpus
);
1567 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1573 mp_cpu_configure(int cpuid
)
1577 if (use_mp
== 0 || plat_dr_support_cpu() == 0) {
1581 cp
= cpu_get(cpuid
);
1587 * Check if there's at least a Mbyte of kmem available
1588 * before attempting to start the cpu.
1590 if (kmem_avail() < 1024 * 1024) {
1592 * Kick off a reap in case that helps us with
1599 cp
= mp_cpu_configure_common(cpuid
, B_FALSE
);
1600 ASSERT(cp
!= NULL
&& cpu_get(cpuid
) == cp
);
1602 return (cp
!= NULL
? 0 : EAGAIN
);
1606 mp_cpu_unconfigure(int cpuid
)
1610 if (use_mp
== 0 || plat_dr_support_cpu() == 0) {
1612 } else if (cpuid
< 0 || cpuid
>= max_ncpus
) {
1616 cp
= cpu_get(cpuid
);
1620 mp_cpu_unconfigure_common(cp
, 0);
1626 * Startup function for 'other' CPUs (besides boot cpu).
1627 * Called from real_mode_start.
1629 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1630 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1631 * hat_unload which requires CPU_READY to be set.
1634 mp_startup_common(boolean_t boot
)
1637 uchar_t new_x86_featureset
[BT_SIZEOFMAP(NUM_X86_FEATURES
)];
1638 extern void cpu_event_init_cpu(cpu_t
*);
1641 * We need to get TSC on this proc synced (i.e., any delta
1642 * from cpu0 accounted for) as soon as we can, because many
1643 * many things use gethrtime/pc_gethrestime, including
1644 * interrupts, cmn_err, etc.
1647 /* Let the control CPU continue into tsc_sync_master() */
1648 mp_startup_signal(&procset_slave
, cp
->cpu_id
);
1651 if (tsc_gethrtime_enable
)
1656 * Once this was done from assembly, but it's safer here; if
1657 * it blocks, we need to be able to swtch() to and from, and
1658 * since we get here by calling t_pc, we need to do that call
1659 * before swtch() overwrites it.
1661 (void) (*ap_mlsetup
)();
1663 bzero(new_x86_featureset
, BT_SIZEOFMAP(NUM_X86_FEATURES
));
1664 cpuid_pass1(cp
, new_x86_featureset
);
1668 * Program this cpu's PAT
1670 if (is_x86_feature(x86_featureset
, X86FSET_PAT
))
1675 * Set up TSC_AUX to contain the cpuid for this processor
1676 * for the rdtscp instruction.
1678 if (is_x86_feature(x86_featureset
, X86FSET_TSCP
))
1679 (void) wrmsr(MSR_AMD_TSCAUX
, cp
->cpu_id
);
1682 * Initialize this CPU's syscall handlers
1684 init_cpu_syscall(cp
);
1687 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1688 * highest level at which a routine is permitted to block on
1689 * an adaptive mutex (allows for cpu poke interrupt in case
1690 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1691 * device interrupts that may end up in the hat layer issuing cross
1692 * calls before CPU_READY is set.
1694 splx(ipltospl(LOCK_LEVEL
));
1698 * Do a sanity check to make sure this new CPU is a sane thing
1699 * to add to the collection of processors running this system.
1701 * XXX Clearly this needs to get more sophisticated, if x86
1702 * systems start to get built out of heterogenous CPUs; as is
1703 * likely to happen once the number of processors in a configuration
1704 * gets large enough.
1706 if (compare_x86_featureset(x86_featureset
, new_x86_featureset
) ==
1708 cmn_err(CE_CONT
, "cpu%d: featureset\n", cp
->cpu_id
);
1709 print_x86_featureset(new_x86_featureset
);
1710 cmn_err(CE_WARN
, "cpu%d feature mismatch", cp
->cpu_id
);
1714 * We do not support cpus with mixed monitor/mwait support if the
1715 * boot cpu supports monitor/mwait.
1717 if (is_x86_feature(x86_featureset
, X86FSET_MWAIT
) !=
1718 is_x86_feature(new_x86_featureset
, X86FSET_MWAIT
))
1719 panic("unsupported mixed cpu monitor/mwait support detected");
1722 * We could be more sophisticated here, and just mark the CPU
1723 * as "faulted" but at this point we'll opt for the easier
1724 * answer of dying horribly. Provided the boot cpu is ok,
1725 * the system can be recovered by booting with use_mp set to zero.
1727 if (workaround_errata(cp
) != 0)
1728 panic("critical workaround(s) missing for cpu%d", cp
->cpu_id
);
1731 * We can touch cpu_flags here without acquiring the cpu_lock here
1732 * because the cpu_lock is held by the control CPU which is running
1733 * mp_start_cpu_common().
1734 * Need to clear CPU_QUIESCED flag before calling any function which
1735 * may cause thread context switching, such as kmem_alloc() etc.
1736 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1737 * it's set. So the startup thread may have no chance to switch back
1738 * again if it's switched away with CPU_QUIESCED set.
1740 cp
->cpu_flags
&= ~(CPU_POWEROFF
| CPU_QUIESCED
);
1743 * Setup this processor for XSAVE.
1745 if (fp_save_mech
== FP_XSAVE
) {
1746 xsave_setup_msr(cp
);
1751 cpuid_pass4(cp
, NULL
);
1754 * Correct cpu_idstr and cpu_brandstr on target CPU after
1755 * cpuid_pass1() is done.
1757 (void) cpuid_getidstr(cp
, cp
->cpu_idstr
, CPU_IDSTRLEN
);
1758 (void) cpuid_getbrandstr(cp
, cp
->cpu_brandstr
, CPU_IDSTRLEN
);
1760 cp
->cpu_flags
|= CPU_RUNNING
| CPU_READY
| CPU_EXISTS
;
1762 post_startup_cpu_fixups();
1764 cpu_event_init_cpu(cp
);
1767 * Enable preemption here so that contention for any locks acquired
1768 * later in mp_startup_common may be preempted if the thread owning
1769 * those locks is continuously executing on other CPUs (for example,
1770 * this CPU must be preemptible to allow other CPUs to pause it during
1771 * their startup phases). It's safe to enable preemption here because
1772 * the CPU state is pretty-much fully constructed.
1774 curthread
->t_preempt
= 0;
1776 /* The base spl should still be at LOCK LEVEL here */
1777 ASSERT(cp
->cpu_base_spl
== ipltospl(LOCK_LEVEL
));
1778 set_base_spl(); /* Restore the spl to its proper value */
1780 pghw_physid_create(cp
);
1782 * Delegate initialization tasks, which need to access the cpu_lock,
1783 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1784 * during CPU DR operations.
1786 mp_startup_signal(&procset_slave
, cp
->cpu_id
);
1787 mp_startup_wait(&procset_master
, cp
->cpu_id
);
1788 pg_cmt_cpu_startup(cp
);
1791 mutex_enter(&cpu_lock
);
1792 cp
->cpu_flags
&= ~CPU_OFFLINE
;
1793 cpu_enable_intr(cp
);
1795 mutex_exit(&cpu_lock
);
1798 /* Enable interrupts */
1802 * Fill out cpu_ucode_info. Update microcode if necessary.
1809 * Set up the CPU module for this CPU. This can't be done
1810 * before this CPU is made CPU_READY, because we may (in
1811 * heterogeneous systems) need to go load another CPU module.
1812 * The act of attempting to load a module may trigger a
1813 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1817 if ((hdl
= cmi_init(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(CPU
),
1818 cmi_ntv_hwcoreid(CPU
), cmi_ntv_hwstrandid(CPU
))) != NULL
) {
1819 if (is_x86_feature(x86_featureset
, X86FSET_MCA
))
1821 cp
->cpu_m
.mcpu_cmi_hdl
= hdl
;
1826 if (boothowto
& RB_DEBUG
)
1830 * Setting the bit in cpu_ready_set must be the last operation in
1831 * processor initialization; the boot CPU will continue to boot once
1832 * it sees this bit set for all active CPUs.
1834 CPUSET_ATOMIC_ADD(cpu_ready_set
, cp
->cpu_id
);
1836 (void) mach_cpu_create_device_node(cp
, NULL
);
1838 cmn_err(CE_CONT
, "?cpu%d: %s\n", cp
->cpu_id
, cp
->cpu_idstr
);
1839 cmn_err(CE_CONT
, "?cpu%d: %s\n", cp
->cpu_id
, cp
->cpu_brandstr
);
1840 cmn_err(CE_CONT
, "?cpu%d initialization complete - online\n",
1844 * Now we are done with the startup thread, so free it up.
1847 panic("mp_startup: cannot return");
1852 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1855 mp_startup_boot(void)
1857 mp_startup_common(B_TRUE
);
1861 * Startup function for hotplug CPUs at runtime.
1864 mp_startup_hotplug(void)
1866 mp_startup_common(B_FALSE
);
1870 * Start CPU on user request.
1874 mp_cpu_start(struct cpu
*cp
)
1876 ASSERT(MUTEX_HELD(&cpu_lock
));
1881 * Stop CPU on user request.
1884 mp_cpu_stop(struct cpu
*cp
)
1886 extern int cbe_psm_timer_mode
;
1887 ASSERT(MUTEX_HELD(&cpu_lock
));
1891 * We can't offline vcpu0.
1893 if (cp
->cpu_id
== 0)
1898 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1899 * can't stop it. (This is true only for machines with no TSC.)
1902 if ((cbe_psm_timer_mode
== TIMER_PERIODIC
) && (cp
->cpu_id
== 0))
1909 * Take the specified CPU out of participation in interrupts.
1912 cpu_disable_intr(struct cpu
*cp
)
1914 if (psm_disable_intr(cp
->cpu_id
) != DDI_SUCCESS
)
1917 cp
->cpu_flags
&= ~CPU_ENABLE
;
1922 * Allow the specified CPU to participate in interrupts.
1925 cpu_enable_intr(struct cpu
*cp
)
1927 ASSERT(MUTEX_HELD(&cpu_lock
));
1928 cp
->cpu_flags
|= CPU_ENABLE
;
1929 psm_enable_intr(cp
->cpu_id
);
1933 mp_cpu_faulted_enter(struct cpu
*cp
)
1936 _NOTE(ARGUNUSED(cp
));
1938 cmi_hdl_t hdl
= cp
->cpu_m
.mcpu_cmi_hdl
;
1943 hdl
= cmi_hdl_lookup(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(cp
),
1944 cmi_ntv_hwcoreid(cp
), cmi_ntv_hwstrandid(cp
));
1947 cmi_faulted_enter(hdl
);
1954 mp_cpu_faulted_exit(struct cpu
*cp
)
1957 _NOTE(ARGUNUSED(cp
));
1959 cmi_hdl_t hdl
= cp
->cpu_m
.mcpu_cmi_hdl
;
1964 hdl
= cmi_hdl_lookup(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(cp
),
1965 cmi_ntv_hwcoreid(cp
), cmi_ntv_hwstrandid(cp
));
1968 cmi_faulted_exit(hdl
);
1975 * The following two routines are used as context operators on threads belonging
1976 * to processes with a private LDT (see sysi86). Due to the rarity of such
1977 * processes, these routines are currently written for best code readability and
1978 * organization rather than speed. We could avoid checking x86_featureset at
1979 * every context switch by installing different context ops, depending on
1980 * x86_featureset, at LDT creation time -- one for each combination of fast
1986 cpu_fast_syscall_disable(void *arg
)
1988 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
1989 is_x86_feature(x86_featureset
, X86FSET_SEP
))
1991 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
1992 is_x86_feature(x86_featureset
, X86FSET_ASYSC
))
1993 cpu_asysc_disable();
1998 cpu_fast_syscall_enable(void *arg
)
2000 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2001 is_x86_feature(x86_featureset
, X86FSET_SEP
))
2003 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2004 is_x86_feature(x86_featureset
, X86FSET_ASYSC
))
2009 cpu_sep_enable(void)
2011 ASSERT(is_x86_feature(x86_featureset
, X86FSET_SEP
));
2012 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2014 wrmsr(MSR_INTC_SEP_CS
, (uint64_t)(uintptr_t)KCS_SEL
);
2018 cpu_sep_disable(void)
2020 ASSERT(is_x86_feature(x86_featureset
, X86FSET_SEP
));
2021 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2024 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2025 * the sysenter or sysexit instruction to trigger a #gp fault.
2027 wrmsr(MSR_INTC_SEP_CS
, 0);
2031 cpu_asysc_enable(void)
2033 ASSERT(is_x86_feature(x86_featureset
, X86FSET_ASYSC
));
2034 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2036 wrmsr(MSR_AMD_EFER
, rdmsr(MSR_AMD_EFER
) |
2037 (uint64_t)(uintptr_t)AMD_EFER_SCE
);
2041 cpu_asysc_disable(void)
2043 ASSERT(is_x86_feature(x86_featureset
, X86FSET_ASYSC
));
2044 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2047 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2048 * executing syscall or sysret with this bit off will incur a #ud trap.
2050 wrmsr(MSR_AMD_EFER
, rdmsr(MSR_AMD_EFER
) &
2051 ~((uint64_t)(uintptr_t)AMD_EFER_SCE
));