4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
28 * This file is part of the Chelsio T1 Ethernet driver.
30 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
34 * Solaris Multithreaded STREAMS Chelsio PCI Ethernet Driver.
38 #include <sys/types.h>
39 #include <sys/systm.h>
40 #include <sys/cmn_err.h>
42 #include <sys/sunddi.h>
43 #include <sys/byteorder.h>
44 #include <sys/atomic.h>
45 #include <sys/ethernet.h>
46 #if PE_PROFILING_ENABLED
53 #ifdef CONFIG_CHELSIO_T1_1G
54 #include "fpga_defs.h"
57 #ifdef CONFIG_CHELSIO_T1_OFFLOAD
63 #ifdef CONFIG_CHELSIO_T1_OFFLOAD
70 #include "suni1x10gexp_regs.h"
73 #define MLEN(mp) ((mp)->b_wptr - (mp)->b_rptr)
75 extern uint32_t buffers_in_use
[];
76 extern kmutex_t in_use_l
;
77 extern uint32_t in_use_index
;
79 static void link_start(ch_t
*sa
, struct pe_port_t
*pp
);
80 static ch_esb_t
*ch_alloc_small_esbbuf(ch_t
*sa
, uint32_t i
);
81 static ch_esb_t
*ch_alloc_big_esbbuf(ch_t
*sa
, uint32_t i
);
82 void ch_big_rbuf_recycle(ch_esb_t
*rbp
);
83 void ch_small_rbuf_recycle(ch_esb_t
*rbp
);
84 static const struct board_info
*pe_sa_init(ch_t
*sa
);
85 static int ch_set_config_data(ch_t
*chp
);
86 void pe_rbuf_pool_free(ch_t
*chp
);
87 static void pe_free_driver_resources(ch_t
*sa
);
88 static void update_mtu_tab(ch_t
*adapter
);
89 static int pe_change_mtu(ch_t
*chp
);
92 * CPL5 Defines (from netinet/cpl5_commands.h)
94 #define FLITSTOBYTES 8
96 #define CPL_FORMAT_0_SIZE 8
97 #define CPL_FORMAT_1_SIZE 16
98 #define CPL_FORMAT_2_SIZE 24
99 #define CPL_FORMAT_3_SIZE 32
100 #define CPL_FORMAT_4_SIZE 40
101 #define CPL_FORMAT_5_SIZE 48
103 #define TID_MASK 0xffffff
105 #define PE_LINK_SPEED_AUTONEG 5
107 static int pe_small_rbuf_pool_init(ch_t
*sa
);
108 static int pe_big_rbuf_pool_init(ch_t
*sa
);
109 static int pe_make_fake_arp(ch_t
*chp
, unsigned char *arpp
);
110 static uint32_t pe_get_ip(unsigned char *arpp
);
113 * May be set in /etc/system to 0 to use default latency timer for 10G.
114 * See PCI register 0xc definition.
116 int enable_latency_timer
= 1;
119 * May be set in /etc/system to 0 to disable hardware checksum for
122 int enable_checksum_offload
= 1;
125 * Multiplier for freelist pool.
127 int fl_sz_multiplier
= 6;
132 mutex_enter(&sa
->ch_intr
);
134 if (sge_data_in(sa
->sge
)) {
136 mutex_exit(&sa
->ch_intr
);
137 return (DDI_INTR_CLAIMED
);
140 mutex_exit(&sa
->ch_intr
);
142 return (DDI_INTR_UNCLAIMED
);
146 * Each setup struct will call this function to
158 * Need to count the number of times this routine is called
159 * because we only want the resources to be allocated once.
160 * The 7500 has four ports and so this routine can be called
161 * once for each port.
163 if (sa
->init_counter
== 0) {
164 for_each_port(sa
, i
) {
167 * We only want to initialize the line if it is down.
169 if (sa
->port
[i
].line_up
== 0) {
170 link_start(sa
, &sa
->port
[i
]);
171 sa
->port
[i
].line_up
= 1;
175 (void) t1_init_hw_modules(sa
);
178 * Enable/Disable checksum offloading.
180 if (sa
->ch_config
.cksum_enabled
) {
181 if (sa
->config_data
.offload_ip_cksum
) {
182 /* Notify that HW will do the checksum. */
183 t1_tp_set_ip_checksum_offload(sa
->tp
, 1);
186 if (sa
->config_data
.offload_tcp_cksum
) {
187 /* Notify that HW will do the checksum. */
188 t1_tp_set_tcp_checksum_offload(sa
->tp
, 1);
191 if (sa
->config_data
.offload_udp_cksum
) {
192 /* Notify that HW will do the checksum. */
193 t1_tp_set_udp_checksum_offload(sa
->tp
, 1);
197 sa
->ch_flags
|= PEINITDONE
;
203 * Enable interrupts after starting the SGE so
204 * that the SGE is ready to handle interrupts.
206 (void) sge_start(sa
->sge
);
207 t1_interrupts_enable(sa
);
210 * set mtu (either 1500 or bigger)
212 (void) pe_change_mtu(sa
);
215 * get the configured value of the MAC.
217 (void) t1_tpi_read(sa
, SUNI1x10GEXP_REG_TXXG_CONFIG_1
<< 2,
224 link_start(ch_t
*sa
, struct pe_port_t
*p
)
226 struct cmac
*mac
= p
->mac
;
228 mac
->ops
->reset(mac
);
229 if (mac
->ops
->macaddress_set
)
230 mac
->ops
->macaddress_set(mac
, p
->enaddr
);
231 (void) t1_link_start(p
->phy
, mac
, &p
->link_config
);
232 mac
->ops
->enable(mac
, MAC_DIRECTION_RX
| MAC_DIRECTION_TX
);
236 * turn off interrupts...
241 t1_interrupts_disable(sa
);
242 (void) sge_stop(sa
->sge
);
245 * we can still be running an interrupt thread in sge_data_in().
246 * If we are, we'll block on the ch_intr lock
248 mutex_enter(&sa
->ch_intr
);
249 mutex_exit(&sa
->ch_intr
);
253 * output mblk to SGE level and out to the wire.
257 pe_start(ch_t
*sa
, mblk_t
*mp
, uint32_t flg
)
262 cmdQ_ce_t
*hmp
= &cm
[0]; /* head of cm table (may be kmem_alloed) */
263 int cm_flg
= 0; /* flag (1 - if kmem-alloced) */
264 int nseg
= 0; /* number cmdQ_ce entries created */
265 int mseg
= 16; /* maximum entries in hmp arrary */
266 int freeme
= 0; /* we have an mblk to free in case of error */
267 uint32_t ch_bind_dma_handle(ch_t
*, int, caddr_t
, cmdQ_ce_t
*,
270 uint32_t ch_bind_dvma_handle(ch_t
*, int, caddr_t
, cmdQ_ce_t
*,
273 int rv
; /* return value on error */
275 #ifdef CONFIG_CHELSIO_T1_OFFLOAD
276 if (flg
& CH_OFFLOAD
) {
277 hmp
->ce_pa
= ((tbuf_t
*)mp
)->tb_pa
;
279 hmp
->ce_flg
= DH_TOE
;
280 hmp
->ce_len
= ((tbuf_t
*)mp
)->tb_len
;
283 /* make sure data is flushed to physical memory */
284 (void) ddi_dma_sync((ddi_dma_handle_t
)((tbuf_t
*)mp
)->tb_dh
,
285 (off_t
)0, hmp
->ce_len
, DDI_DMA_SYNC_FORDEV
);
287 if (sge_data_out(sa
->sge
, 0, mp
, hmp
, 1, flg
) == 0) {
292 * set a flag so we'll restart upper layer when
293 * resources become available.
298 #endif /* CONFIG_CHELSIO_T1_OFFLOAD */
300 /* writes from toe will always have CPL header in place */
301 if (flg
& CH_NO_CPL
) {
302 struct cpl_tx_pkt
*cpl
;
304 /* PR2928 & PR3309 */
305 if (sa
->ch_ip
== NULL
) {
306 ushort_t ethertype
= ntohs(*(short *)&mp
->b_rptr
[12]);
307 if (ethertype
== ETHERTYPE_ARP
) {
310 * We assume here that the arp will be
311 * contained in one mblk.
313 if (pe_make_fake_arp(sa
, mp
->b_rptr
)) {
319 sa
->ch_ip
= pe_get_ip(mp
->b_rptr
);
325 * if space in front of packet big enough for CPL
326 * header, then use it. We'll allocate an mblk
329 if ((mp
->b_rptr
- mp
->b_datap
->db_base
) >= SZ_CPL_TX_PKT
) {
331 mp
->b_rptr
-= SZ_CPL_TX_PKT
;
336 sa
->sge
->intr_cnt
.tx_need_cpl_space
++;
338 m0
= allocb(SZ_CPL_TX_PKT
, BPRI_HI
);
345 m0
->b_wptr
= m0
->b_rptr
+ SZ_CPL_TX_PKT
;
352 /* fill in cpl header */
353 cpl
= (struct cpl_tx_pkt
*)mp
->b_rptr
;
354 cpl
->opcode
= CPL_TX_PKT
;
355 cpl
->iff
= 0; /* XXX port 0 needs fixing with NEMO */
356 cpl
->ip_csum_dis
= 1; /* no IP header cksum */
358 flg
& CH_NO_HWCKSUM
; /* CH_NO_HWCKSUM == 1 */
359 cpl
->vlan_valid
= 0; /* no vlan */
365 sa
->sge
->intr_cnt
.tx_multi_mblks
++;
369 int lseg
; /* added by ch_bind_dma_handle() */
373 /* skip mlks with no data */
380 * if we've run out of space on stack, then we
381 * allocate a temporary buffer to hold the
382 * information. This will kill the the performance,
383 * but since it shouldn't really occur, we can live
384 * with it. Since jumbo frames may map multiple
385 * descriptors, we reallocate the hmp[] array before
388 if (nseg
>= (mseg
-4)) {
392 buf
= kmem_alloc(sizeof (cmdQ_ce_t
) * 2 * mseg
,
395 for (j
= 0; j
< nseg
; j
++)
400 mseg
* sizeof (cmdQ_ce_t
));
408 * We've used up ch table on stack
413 if (sa
->ch_config
.enable_dvma
) {
414 lseg
= ch_bind_dvma_handle(sa
, len
,
416 &hmp
[nseg
], mseg
- nseg
);
418 sa
->sge
->intr_cnt
.tx_no_dvma1
++;
419 if ((lseg
= ch_bind_dma_handle(sa
, len
,
422 mseg
- nseg
)) == NULL
) {
423 sa
->sge
->intr_cnt
.tx_no_dma1
++;
426 * ran out of space. Gonna bale
431 * we may have processed
432 * previous mblks and have
433 * descriptors. If so, we need
434 * to free the meta struct
435 * entries before freeing
444 lseg
= ch_bind_dma_handle(sa
, len
,
445 (void *)mp
->b_rptr
, &hmp
[nseg
],
448 sa
->sge
->intr_cnt
.tx_no_dma1
++;
451 * ran out of space. Gona bale
456 * we may have processed previous
457 * mblks and have descriptors. If so,
458 * we need to free the meta struct
459 * entries before freeing the mblk.
466 #else /* defined(__sparc) */
467 lseg
= ch_bind_dma_handle(sa
, len
,
468 (void *)mp
->b_rptr
, &hmp
[nseg
],
471 sa
->sge
->intr_cnt
.tx_no_dma1
++;
474 * ran out of space. Gona bale
479 * we may have processed previous mblks and
480 * have descriptors. If so, we need to free
481 * the meta struct entries before freeing
488 #endif /* defined(__sparc) */
494 * SHOULD NEVER OCCUR, BUT...
495 * no data if nseg 0 or
496 * nseg 1 and a CPL mblk (CPL mblk only with offload mode)
499 if ((nseg
== 0) || (freeme
&& (nseg
== 1))) {
507 /* we assume that we always have data with one packet */
511 if (sa
->ch_config
.enable_dvma
) {
512 nseg
= ch_bind_dvma_handle(sa
, len
,
516 sa
->sge
->intr_cnt
.tx_no_dvma2
++;
517 nseg
= ch_bind_dma_handle(sa
, len
,
521 sa
->sge
->intr_cnt
.tx_no_dma2
++;
524 * ran out of space. Gona bale
531 nseg
= ch_bind_dma_handle(sa
, len
,
532 (void *)mp
->b_rptr
, &hmp
[0], 16);
534 sa
->sge
->intr_cnt
.tx_no_dma2
++;
537 * ran out of space. Gona bale
543 #else /* defined(__sparc) */
544 nseg
= ch_bind_dma_handle(sa
, len
,
545 (void *)mp
->b_rptr
, &hmp
[0], 16);
547 sa
->sge
->intr_cnt
.tx_no_dma2
++;
550 * ran out of space. Gona bale
555 #endif /* defined(__sparc) */
558 * dummy arp message to handle PR3309 & PR2928
561 hmp
->ce_flg
|= DH_ARP
;
564 if (sge_data_out(sa
->sge
, 0, m0
, hmp
, nseg
, flg
) == 0) {
566 kmem_free(hmp
, mseg
* sizeof (cmdQ_ce_t
));
571 * set a flag so we'll restart upper layer when
572 * resources become available.
574 if ((flg
& CH_ARP
) == 0)
580 * unmap the physical addresses allocated earlier.
583 for (--nseg
; nseg
>= 0; nseg
--) {
585 if (cmp
->ce_flg
== DH_DMA
)
586 ch_unbind_dma_handle(sa
, cmp
->ce_dh
);
589 ch_unbind_dvma_handle(sa
, cmp
->ce_dh
);
597 /* free the temporary array */
599 kmem_free(hmp
, mseg
* sizeof (cmdQ_ce_t
));
602 * if we've allocated an mblk above, then we need to free it
603 * before returning. This is safe since we haven't done anything to
604 * the original message. The caller, gld, will still have a pointer
605 * to the original mblk.
609 /* we had to allocate an mblk. Free it. */
612 /* adjust the mblk back to original start */
614 m0
->b_rptr
+= SZ_CPL_TX_PKT
;
624 /* KLUDGE ALERT. HARD WIRED TO PORT ZERO */
626 pe_set_mac(ch_t
*sa
, unsigned char *ac_enaddr
)
628 sa
->port
[0].mac
->ops
->macaddress_set(sa
->port
[0].mac
, ac_enaddr
);
631 /* KLUDGE ALERT. HARD WIRED TO PORT ZERO */
635 return (sa
->port
[0].enaddr
);
638 /* KLUDGE ALERT. HARD WIRED TO ONE PORT */
640 pe_set_promiscuous(ch_t
*sa
, int flag
)
642 struct cmac
*mac
= sa
->port
[0].mac
;
643 struct t1_rx_mode rm
;
646 case 0: /* turn off promiscuous mode */
647 sa
->ch_flags
&= ~(PEPROMISC
|PEALLMULTI
);
650 case 1: /* turn on promiscuous mode */
651 sa
->ch_flags
|= PEPROMISC
;
654 case 2: /* turn on multicast reception */
655 sa
->ch_flags
|= PEALLMULTI
;
659 mutex_enter(&sa
->ch_mc_lck
);
663 mac
->ops
->set_rx_mode(mac
, &rm
);
664 mutex_exit(&sa
->ch_mc_lck
);
668 pe_set_mc(ch_t
*sa
, uint8_t *ep
, int flg
)
670 struct cmac
*mac
= sa
->port
[0].mac
;
671 struct t1_rx_mode rm
;
673 if (flg
== GLD_MULTI_ENABLE
) {
676 mcp
= (ch_mc_t
*)kmem_zalloc(sizeof (struct ch_mc
),
679 return (GLD_NORESOURCES
);
681 bcopy(ep
, &mcp
->cmc_mca
, 6);
683 mutex_enter(&sa
->ch_mc_lck
);
684 mcp
->cmc_next
= sa
->ch_mc
;
687 mutex_exit(&sa
->ch_mc_lck
);
689 } else if (flg
== GLD_MULTI_DISABLE
) {
690 ch_mc_t
**p
= &sa
->ch_mc
;
693 mutex_enter(&sa
->ch_mc_lck
);
696 if (bcmp(ep
, (*p
)->cmc_mca
, 6) == 0) {
699 kmem_free(q
, sizeof (*q
));
706 mutex_exit(&sa
->ch_mc_lck
);
713 mutex_enter(&sa
->ch_mc_lck
);
717 mac
->ops
->set_rx_mode(mac
, &rm
);
718 mutex_exit(&sa
->ch_mc_lck
);
720 return (GLD_SUCCESS
);
724 * return: speed - bandwidth of interface
725 * return: intrcnt - # interrupts
726 * return: norcvbuf - # recedived packets dropped by driver
727 * return: oerrors - # bad send packets
728 * return: ierrors - # bad receive packets
729 * return: underrun - # bad underrun xmit packets
730 * return: overrun - # bad overrun recv packets
731 * return: framing - # bad aligned recv packets
732 * return: crc - # bad FCS (crc) recv packets
733 * return: carrier - times carrier was lost
734 * return: collisions - # xmit collisions
735 * return: xcollisions - # xmit pkts dropped due to collisions
736 * return: late - # late xmit collisions
737 * return: defer - # deferred xmit packets
738 * return: xerrs - # xmit dropped packets
739 * return: rerrs - # recv dropped packets
740 * return: toolong - # recv pkts too long
741 * return: runt - # recv runt pkts
742 * return: multixmt - # multicast pkts xmitted
743 * return: multircv - # multicast pkts recved
744 * return: brdcstxmt - # broadcast pkts xmitted
745 * return: brdcstrcv - # broadcast pkts rcv
749 pe_get_stats(ch_t
*sa
, uint64_t *speed
, uint32_t *intrcnt
, uint32_t *norcvbuf
,
750 uint32_t *oerrors
, uint32_t *ierrors
, uint32_t *underrun
,
751 uint32_t *overrun
, uint32_t *framing
, uint32_t *crc
,
752 uint32_t *carrier
, uint32_t *collisions
, uint32_t *xcollisions
,
753 uint32_t *late
, uint32_t *defer
, uint32_t *xerrs
, uint32_t *rerrs
,
754 uint32_t *toolong
, uint32_t *runt
, ulong_t
*multixmt
, ulong_t
*multircv
,
755 ulong_t
*brdcstxmt
, ulong_t
*brdcstrcv
)
757 struct pe_port_t
*pt
;
762 const struct cmac_statistics
*sp
;
765 (void) pt
->phy
->ops
->get_link_status(pt
->phy
,
766 &line_is_active
, &line_speed
, &line_duplex
, NULL
);
768 switch (line_speed
) {
780 * kludge to get 10,000,000,000 constant (and keep
791 *intrcnt
= sa
->isr_intr
;
792 *norcvbuf
= sa
->norcvbuf
;
794 sp
= sa
->port
[0].mac
->ops
->statistics_update(sa
->port
[0].mac
,
795 MAC_STATS_UPDATE_FULL
);
797 *ierrors
= sp
->RxOctetsBad
;
800 * not sure this is correct. # aborted at driver level +
801 * # at hardware level
803 *oerrors
= sa
->oerr
+ sp
->TxFramesAbortedDueToXSCollisions
+
804 sp
->TxUnderrun
+ sp
->TxLengthErrors
+
805 sp
->TxInternalMACXmitError
+
806 sp
->TxFramesWithExcessiveDeferral
+
809 *underrun
= sp
->TxUnderrun
;
810 *overrun
= sp
->RxFrameTooLongErrors
;
811 *framing
= sp
->RxAlignErrors
;
812 *crc
= sp
->RxFCSErrors
;
813 *carrier
= 0; /* need to find this */
814 *collisions
= sp
->TxTotalCollisions
;
815 *xcollisions
= sp
->TxFramesAbortedDueToXSCollisions
;
816 *late
= sp
->TxLateCollisions
;
817 *defer
= sp
->TxFramesWithDeferredXmissions
;
818 *xerrs
= sp
->TxUnderrun
+ sp
->TxLengthErrors
+
819 sp
->TxInternalMACXmitError
+ sp
->TxFCSErrors
;
820 *rerrs
= sp
->RxSymbolErrors
+ sp
->RxSequenceErrors
+ sp
->RxRuntErrors
+
821 sp
->RxJabberErrors
+ sp
->RxInternalMACRcvError
+
822 sp
->RxInRangeLengthErrors
+ sp
->RxOutOfRangeLengthField
;
823 *toolong
= sp
->RxFrameTooLongErrors
;
824 *runt
= sp
->RxRuntErrors
;
826 *multixmt
= sp
->TxMulticastFramesOK
;
827 *multircv
= sp
->RxMulticastFramesOK
;
828 *brdcstxmt
= sp
->TxBroadcastFramesOK
;
829 *brdcstrcv
= sp
->RxBroadcastFramesOK
;
861 uint32_t ch_gtm
= 0; /* Default: Global Tunnel Mode off */
862 uint32_t ch_global_config
= 0x07000000; /* Default: errors, warnings, status */
863 uint32_t ch_is_asic
= 0; /* Default: non-ASIC */
864 uint32_t ch_link_speed
= PE_LINK_SPEED_AUTONEG
; /* Default: auto-negoiate */
865 uint32_t ch_num_of_ports
= 1; /* Default: 1 port */
866 uint32_t ch_tp_reset_cm
= 1; /* Default: reset CM memory map */
867 uint32_t ch_phy_tx_fifo
= 0; /* Default: 0 phy tx fifo depth */
868 uint32_t ch_phy_rx_fifo
= 0; /* Default: 0 phy rx fifo depth */
869 uint32_t ch_phy_force_master
= 1; /* Default: link always master mode */
870 uint32_t ch_mc5_rtbl_size
= 2048; /* Default: TCAM routing table size */
871 uint32_t ch_mc5_dbsvr_size
= 128; /* Default: TCAM server size */
872 uint32_t ch_mc5_parity
= 1; /* Default: parity error checking */
873 uint32_t ch_mc5_issue_syn
= 0; /* Default: Allow transaction overlap */
874 uint32_t ch_packet_tracing
= 0; /* Default: no packet tracing */
875 uint32_t ch_server_region_len
=
876 DEFAULT_SERVER_REGION_LEN
;
877 uint32_t ch_rt_region_len
=
878 DEFAULT_RT_REGION_LEN
;
879 uint32_t ch_offload_ip_cksum
= 0; /* Default: no checksum offloading */
880 uint32_t ch_offload_udp_cksum
= 1; /* Default: offload UDP ckecksum */
881 uint32_t ch_offload_tcp_cksum
= 1; /* Default: offload TCP checksum */
882 uint32_t ch_sge_cmdq_threshold
= 0; /* Default: threshold 0 */
883 uint32_t ch_sge_flq_threshold
= 0; /* Default: SGE flq threshold */
884 uint32_t ch_sge_cmdq0_cnt
= /* Default: cmd queue 0 size */
886 uint32_t ch_sge_cmdq1_cnt
= /* Default: cmd queue 1 size */
888 uint32_t ch_sge_flq0_cnt
= /* Default: free list queue-0 length */
890 uint32_t ch_sge_flq1_cnt
= /* Default: free list queue-1 length */
892 uint32_t ch_sge_respq_cnt
= /* Default: reqsponse queue size */
894 uint32_t ch_stats
= 1; /* Default: Automatic Update MAC stats */
895 uint32_t ch_tx_delay_us
= 0; /* Default: No Msec delay to Tx pkts */
896 int32_t ch_chip
= -1; /* Default: use hardware lookup tbl */
897 uint32_t ch_exit_early
= 0; /* Default: complete initialization */
898 uint32_t ch_rb_num_of_entries
= 1000; /* Default: number ring buffer entries */
899 uint32_t ch_rb_size_of_entries
= 64; /* Default: ring buffer entry size */
900 uint32_t ch_rb_flag
= 1; /* Default: ring buffer flag */
902 uint64_t ch_cat_opt0
= 0;
903 uint64_t ch_cat_opt1
= 0;
904 uint32_t ch_timer_delay
= 0; /* Default: use value from board entry */
910 const struct board_info
*bi
;
913 (void) ch_set_config_data(chp
);
915 bi
= pe_sa_init(chp
);
919 if (t1_init_sw_modules(chp
, bi
) < 0)
922 if (pe_small_rbuf_pool_init(chp
) == NULL
)
925 if (pe_big_rbuf_pool_init(chp
) == NULL
)
929 * We gain significaint performance improvements when we
930 * increase the PCI's maximum memory read byte count to
931 * 2K(HW doesn't support 4K at this time) and set the PCI's
932 * maximum outstanding split transactions to 4. We want to do
933 * this for 10G. Done by software utility.
936 if (board_info(chp
)->caps
& SUPPORTED_10000baseT_Full
) {
937 (void) t1_os_pci_read_config_4(chp
, A_PCICFG_PCIX_CMD
,
940 * if the burstsize is set, then use it instead of default
942 if (chp
->ch_config
.burstsize_set
) {
943 pcix_cmd
&= ~0xc0000;
944 pcix_cmd
|= (chp
->ch_config
.burstsize
<< 18);
947 * if the split transaction count is set, then use it.
949 if (chp
->ch_config
.transaction_cnt_set
) {
950 pcix_cmd
&= ~ 0x700000;
951 pcix_cmd
|= (chp
->ch_config
.transaction_cnt
<< 20);
955 * set ralaxed ordering flag as configured in chxge.conf
957 pcix_cmd
|= (chp
->ch_config
.relaxed_ordering
<< 17);
959 (void) t1_os_pci_write_config_4(chp
, A_PCICFG_PCIX_CMD
,
964 * set the latency time to F8 for 10G cards.
965 * Done by software utiltiy.
967 if (enable_latency_timer
) {
968 if (board_info(chp
)->caps
& SUPPORTED_10000baseT_Full
) {
969 (void) t1_os_pci_write_config_4(chp
, 0xc, 0xf800);
974 * update mtu table (regs: 0x404 - 0x420) with bigger values than
980 * Clear all interrupts now. Don't enable
983 t1_interrupts_clear(chp
);
986 * Function succeeded.
994 * DESC: Read variables set in /boot/loader.conf and save
995 * them internally. These internal values are then
996 * used to make decisions at run-time on behavior thus
997 * allowing a certain level of customization.
998 * OUT: p_config - pointer to config structure that
999 * contains all of the new values.
1003 ch_set_config_data(ch_t
*chp
)
1005 pe_config_data_t
*p_config
= (pe_config_data_t
*)&chp
->config_data
;
1007 bzero(p_config
, sizeof (pe_config_data_t
));
1010 * Global Tunnel Mode configuration
1012 p_config
->gtm
= ch_gtm
;
1014 p_config
->global_config
= ch_global_config
;
1017 p_config
->global_config
|= CFGMD_TUNNEL
;
1019 p_config
->tp_reset_cm
= ch_tp_reset_cm
;
1020 p_config
->is_asic
= ch_is_asic
;
1023 * MC5 configuration.
1025 p_config
->mc5_rtbl_size
= ch_mc5_rtbl_size
;
1026 p_config
->mc5_dbsvr_size
= ch_mc5_dbsvr_size
;
1027 p_config
->mc5_parity
= ch_mc5_parity
;
1028 p_config
->mc5_issue_syn
= ch_mc5_issue_syn
;
1030 p_config
->offload_ip_cksum
= ch_offload_ip_cksum
;
1031 p_config
->offload_udp_cksum
= ch_offload_udp_cksum
;
1032 p_config
->offload_tcp_cksum
= ch_offload_tcp_cksum
;
1034 p_config
->packet_tracing
= ch_packet_tracing
;
1036 p_config
->server_region_len
= ch_server_region_len
;
1037 p_config
->rt_region_len
= ch_rt_region_len
;
1040 * Link configuration.
1042 * 5-auto-neg 2-1000Gbps; 1-100Gbps; 0-10Gbps
1044 p_config
->link_speed
= ch_link_speed
;
1045 p_config
->num_of_ports
= ch_num_of_ports
;
1050 p_config
->cat_opt0
= ch_cat_opt0
;
1051 p_config
->cat_opt1
= ch_cat_opt1
;
1054 * SGE configuration.
1056 p_config
->sge_cmdq0_cnt
= ch_sge_cmdq0_cnt
;
1057 p_config
->sge_cmdq1_cnt
= ch_sge_cmdq1_cnt
;
1058 p_config
->sge_flq0_cnt
= ch_sge_flq0_cnt
;
1059 p_config
->sge_flq1_cnt
= ch_sge_flq1_cnt
;
1060 p_config
->sge_respq_cnt
= ch_sge_respq_cnt
;
1062 p_config
->phy_rx_fifo
= ch_phy_rx_fifo
;
1063 p_config
->phy_tx_fifo
= ch_phy_tx_fifo
;
1065 p_config
->sge_cmdq_threshold
= ch_sge_cmdq_threshold
;
1067 p_config
->sge_flq_threshold
= ch_sge_flq_threshold
;
1069 p_config
->phy_force_master
= ch_phy_force_master
;
1071 p_config
->rb_num_of_entries
= ch_rb_num_of_entries
;
1073 p_config
->rb_size_of_entries
= ch_rb_size_of_entries
;
1075 p_config
->rb_flag
= ch_rb_flag
;
1077 p_config
->exit_early
= ch_exit_early
;
1079 p_config
->chip
= ch_chip
;
1081 p_config
->stats
= ch_stats
;
1083 p_config
->tx_delay_us
= ch_tx_delay_us
;
1088 static const struct board_info
*
1089 pe_sa_init(ch_t
*sa
)
1092 uint16_t device_subid
;
1093 const struct board_info
*bi
;
1095 sa
->config
= sa
->config_data
.global_config
;
1096 device_id
= pci_config_get16(sa
->ch_hpci
, 2);
1097 device_subid
= pci_config_get16(sa
->ch_hpci
, 0x2e);
1099 bi
= t1_get_board_info_from_ids(device_id
, device_subid
);
1102 "The adapter with device_id %d %d is not supported.\n",
1103 device_id
, device_subid
);
1107 if (t1_get_board_rev(sa
, bi
, &sa
->params
)) {
1108 cmn_err(CE_NOTE
, "unknown device_id %d %d\n",
1109 device_id
, device_subid
);
1110 return ((const struct board_info
*)NULL
);
1117 * allocate pool of small receive buffers (with vaddr & paddr) and
1118 * receiver buffer control structure (ch_esb_t *rbp).
1119 * XXX we should allow better tuning of the # of preallocated
1120 * free buffers against the # of freelist entries.
1123 pe_small_rbuf_pool_init(ch_t
*sa
)
1127 extern uint32_t sge_flq0_cnt
;
1128 extern uint32_t sge_flq1_cnt
;
1133 size
= sge_flq1_cnt
* fl_sz_multiplier
;
1135 size
= sge_flq0_cnt
* fl_sz_multiplier
;
1137 mutex_init(&sa
->ch_small_esbl
, NULL
, MUTEX_DRIVER
, sa
->ch_icookp
);
1139 mutex_enter(&in_use_l
);
1141 if (in_use_index
>= SZ_INUSE
)
1143 mutex_exit(&in_use_l
);
1145 sa
->ch_small_owner
= NULL
;
1146 sa
->ch_sm_index
= j
;
1147 sa
->ch_small_esb_free
= NULL
;
1148 for (i
= 0; i
< size
; i
++) {
1149 rbp
= ch_alloc_small_esbbuf(sa
, j
);
1153 * add entry to free list
1155 rbp
->cs_next
= sa
->ch_small_esb_free
;
1156 sa
->ch_small_esb_free
= rbp
;
1159 * add entry to owned list
1161 rbp
->cs_owner
= sa
->ch_small_owner
;
1162 sa
->ch_small_owner
= rbp
;
1167 sa
->ch_small_owner
= NULL
;
1169 /* free whatever we've already allocated */
1170 pe_rbuf_pool_free(sa
);
1176 * allocate pool of receive buffers (with vaddr & paddr) and
1177 * receiver buffer control structure (ch_esb_t *rbp).
1178 * XXX we should allow better tuning of the # of preallocated
1179 * free buffers against the # of freelist entries.
1182 pe_big_rbuf_pool_init(ch_t
*sa
)
1186 extern uint32_t sge_flq0_cnt
;
1187 extern uint32_t sge_flq1_cnt
;
1192 size
= sge_flq0_cnt
* fl_sz_multiplier
;
1194 size
= sge_flq1_cnt
* fl_sz_multiplier
;
1196 mutex_init(&sa
->ch_big_esbl
, NULL
, MUTEX_DRIVER
, sa
->ch_icookp
);
1198 mutex_enter(&in_use_l
);
1200 if (in_use_index
>= SZ_INUSE
)
1202 mutex_exit(&in_use_l
);
1204 sa
->ch_big_owner
= NULL
;
1205 sa
->ch_big_index
= j
;
1206 sa
->ch_big_esb_free
= NULL
;
1207 for (i
= 0; i
< size
; i
++) {
1208 rbp
= ch_alloc_big_esbbuf(sa
, j
);
1211 rbp
->cs_next
= sa
->ch_big_esb_free
;
1212 sa
->ch_big_esb_free
= rbp
;
1215 * add entry to owned list
1217 rbp
->cs_owner
= sa
->ch_big_owner
;
1218 sa
->ch_big_owner
= rbp
;
1223 sa
->ch_big_owner
= NULL
;
1225 /* free whatever we've already allocated */
1226 pe_rbuf_pool_free(sa
);
1232 * allocate receive buffer structure and dma mapped buffer (SGE_SM_BUF_SZ bytes)
1233 * note that we will DMA at a 2 byte offset for Solaris when checksum offload
1237 ch_alloc_small_esbbuf(ch_t
*sa
, uint32_t i
)
1241 rbp
= (ch_esb_t
*)kmem_zalloc(sizeof (ch_esb_t
), KM_SLEEP
);
1243 return ((ch_esb_t
*)0);
1246 #if BYTE_ORDER == BIG_ENDIAN
1247 rbp
->cs_buf
= (caddr_t
)ch_alloc_dma_mem(sa
, 1, DMA_STREAM
|DMA_SMALN
,
1248 SGE_SM_BUF_SZ(sa
), &rbp
->cs_pa
, &rbp
->cs_dh
, &rbp
->cs_ah
);
1250 rbp
->cs_buf
= (caddr_t
)ch_alloc_dma_mem(sa
, 0, DMA_STREAM
|DMA_SMALN
,
1251 SGE_SM_BUF_SZ(sa
), &rbp
->cs_pa
, &rbp
->cs_dh
, &rbp
->cs_ah
);
1254 if (rbp
->cs_buf
== NULL
) {
1255 kmem_free(rbp
, sizeof (ch_esb_t
));
1256 return ((ch_esb_t
*)0);
1262 rbp
->cs_frtn
.free_func
= (void (*)())&ch_small_rbuf_recycle
;
1263 rbp
->cs_frtn
.free_arg
= (caddr_t
)rbp
;
1269 * allocate receive buffer structure and dma mapped buffer (SGE_BG_BUF_SZ bytes)
1270 * note that we will DMA at a 2 byte offset for Solaris when checksum offload
1274 ch_alloc_big_esbbuf(ch_t
*sa
, uint32_t i
)
1278 rbp
= (ch_esb_t
*)kmem_zalloc(sizeof (ch_esb_t
), KM_SLEEP
);
1280 return ((ch_esb_t
*)0);
1283 #if BYTE_ORDER == BIG_ENDIAN
1284 rbp
->cs_buf
= (caddr_t
)ch_alloc_dma_mem(sa
, 1, DMA_STREAM
|DMA_BGALN
,
1285 SGE_BG_BUF_SZ(sa
), &rbp
->cs_pa
, &rbp
->cs_dh
, &rbp
->cs_ah
);
1287 rbp
->cs_buf
= (caddr_t
)ch_alloc_dma_mem(sa
, 0, DMA_STREAM
|DMA_BGALN
,
1288 SGE_BG_BUF_SZ(sa
), &rbp
->cs_pa
, &rbp
->cs_dh
, &rbp
->cs_ah
);
1291 if (rbp
->cs_buf
== NULL
) {
1292 kmem_free(rbp
, sizeof (ch_esb_t
));
1293 return ((ch_esb_t
*)0);
1299 rbp
->cs_frtn
.free_func
= (void (*)())&ch_big_rbuf_recycle
;
1300 rbp
->cs_frtn
.free_arg
= (caddr_t
)rbp
;
1306 * free entries on the receive buffer list.
1309 pe_rbuf_pool_free(ch_t
*sa
)
1313 mutex_enter(&sa
->ch_small_esbl
);
1316 * Now set-up the rest to commit suicide.
1318 while (sa
->ch_small_owner
) {
1319 rbp
= sa
->ch_small_owner
;
1320 sa
->ch_small_owner
= rbp
->cs_owner
;
1321 rbp
->cs_owner
= NULL
;
1325 while ((rbp
= sa
->ch_small_esb_free
) != NULL
) {
1326 /* advance head ptr to next entry */
1327 sa
->ch_small_esb_free
= rbp
->cs_next
;
1328 /* free private buffer allocated in ch_alloc_esbbuf() */
1329 ch_free_dma_mem(rbp
->cs_dh
, rbp
->cs_ah
);
1330 /* free descripter buffer */
1331 kmem_free(rbp
, sizeof (ch_esb_t
));
1334 mutex_exit(&sa
->ch_small_esbl
);
1336 /* destroy ch_esbl lock */
1337 mutex_destroy(&sa
->ch_small_esbl
);
1340 mutex_enter(&sa
->ch_big_esbl
);
1343 * Now set-up the rest to commit suicide.
1345 while (sa
->ch_big_owner
) {
1346 rbp
= sa
->ch_big_owner
;
1347 sa
->ch_big_owner
= rbp
->cs_owner
;
1348 rbp
->cs_owner
= NULL
;
1352 while ((rbp
= sa
->ch_big_esb_free
) != NULL
) {
1353 /* advance head ptr to next entry */
1354 sa
->ch_big_esb_free
= rbp
->cs_next
;
1355 /* free private buffer allocated in ch_alloc_esbbuf() */
1356 ch_free_dma_mem(rbp
->cs_dh
, rbp
->cs_ah
);
1357 /* free descripter buffer */
1358 kmem_free(rbp
, sizeof (ch_esb_t
));
1361 mutex_exit(&sa
->ch_big_esbl
);
1363 /* destroy ch_esbl lock */
1364 mutex_destroy(&sa
->ch_big_esbl
);
1368 ch_small_rbuf_recycle(ch_esb_t
*rbp
)
1370 ch_t
*sa
= rbp
->cs_sa
;
1375 * free private buffer allocated in ch_alloc_esbbuf()
1377 ch_free_dma_mem(rbp
->cs_dh
, rbp
->cs_ah
);
1382 * free descripter buffer
1384 kmem_free(rbp
, sizeof (ch_esb_t
));
1387 * decrement count of receive buffers freed by callback
1388 * We decrement here so anyone trying to do fini will
1389 * only remove the driver once the counts go to 0.
1391 atomic_dec_32(&buffers_in_use
[i
]);
1396 mutex_enter(&sa
->ch_small_esbl
);
1397 rbp
->cs_next
= sa
->ch_small_esb_free
;
1398 sa
->ch_small_esb_free
= rbp
;
1399 mutex_exit(&sa
->ch_small_esbl
);
1402 * decrement count of receive buffers freed by callback
1404 atomic_dec_32(&buffers_in_use
[rbp
->cs_index
]);
1408 * callback function from freeb() when esballoced mblk freed.
1411 ch_big_rbuf_recycle(ch_esb_t
*rbp
)
1413 ch_t
*sa
= rbp
->cs_sa
;
1418 * free private buffer allocated in ch_alloc_esbbuf()
1420 ch_free_dma_mem(rbp
->cs_dh
, rbp
->cs_ah
);
1425 * free descripter buffer
1427 kmem_free(rbp
, sizeof (ch_esb_t
));
1430 * decrement count of receive buffers freed by callback
1431 * We decrement here so anyone trying to do fini will
1432 * only remove the driver once the counts go to 0.
1434 atomic_dec_32(&buffers_in_use
[i
]);
1439 mutex_enter(&sa
->ch_big_esbl
);
1440 rbp
->cs_next
= sa
->ch_big_esb_free
;
1441 sa
->ch_big_esb_free
= rbp
;
1442 mutex_exit(&sa
->ch_big_esbl
);
1445 * decrement count of receive buffers freed by callback
1447 atomic_dec_32(&buffers_in_use
[rbp
->cs_index
]);
1451 * get a pre-allocated, pre-mapped receive buffer from free list.
1455 ch_get_small_rbuf(ch_t
*sa
)
1459 mutex_enter(&sa
->ch_small_esbl
);
1460 rbp
= sa
->ch_small_esb_free
;
1462 sa
->ch_small_esb_free
= rbp
->cs_next
;
1464 mutex_exit(&sa
->ch_small_esbl
);
1470 * get a pre-allocated, pre-mapped receive buffer from free list.
1475 ch_get_big_rbuf(ch_t
*sa
)
1479 mutex_enter(&sa
->ch_big_esbl
);
1480 rbp
= sa
->ch_big_esb_free
;
1482 sa
->ch_big_esb_free
= rbp
->cs_next
;
1484 mutex_exit(&sa
->ch_big_esbl
);
1492 (void) sge_stop(sa
->sge
);
1494 pe_free_driver_resources(sa
);
1498 pe_free_driver_resources(ch_t
*sa
)
1501 t1_free_sw_modules(sa
);
1503 /* free pool of receive buffers */
1504 pe_rbuf_pool_free(sa
);
1509 * Processes elmer0 external interrupts in process context.
1512 ext_intr_task(ch_t
*adapter
)
1516 (void) elmer0_ext_intr_handler(adapter
);
1518 /* Now reenable external interrupts */
1519 t1_write_reg_4(adapter
, A_PL_CAUSE
, F_PL_INTR_EXT
);
1520 enable
= t1_read_reg_4(adapter
, A_PL_ENABLE
);
1521 t1_write_reg_4(adapter
, A_PL_ENABLE
, enable
| F_PL_INTR_EXT
);
1522 adapter
->slow_intr_mask
|= F_PL_INTR_EXT
;
1526 * Interrupt-context handler for elmer0 external interrupts.
1529 t1_os_elmer0_ext_intr(ch_t
*adapter
)
1531 u32 enable
= t1_read_reg_4(adapter
, A_PL_ENABLE
);
1533 adapter
->slow_intr_mask
&= ~F_PL_INTR_EXT
;
1534 t1_write_reg_4(adapter
, A_PL_ENABLE
, enable
& ~F_PL_INTR_EXT
);
1536 schedule_work(&adapter
->ext_intr_handler_task
);
1538 ext_intr_task(adapter
);
1543 t1_get_next_mcaddr(struct t1_rx_mode
*rmp
)
1547 addr
= rmp
->mc
->cmc_mca
;
1548 rmp
->mc
= rmp
->mc
->cmc_next
;
1554 pe_dma_handle_init(ch_t
*chp
, int cnt
)
1557 #if defined(__sparc)
1560 for (; cnt
; cnt
--) {
1561 dhe
= ch_get_dvma_handle(chp
);
1564 mutex_enter(&chp
->ch_dh_lck
);
1565 dhe
->dhe_next
= chp
->ch_vdh
;
1567 mutex_exit(&chp
->ch_dh_lck
);
1573 dhe
= ch_get_dma_handle(chp
);
1576 mutex_enter(&chp
->ch_dh_lck
);
1577 dhe
->dhe_next
= chp
->ch_dh
;
1579 mutex_exit(&chp
->ch_dh_lck
);
1584 * Write new values to the MTU table. Caller must validate that the new MTUs
1585 * are in ascending order. params.mtus[] is initialized by init_mtus()
1586 * called in t1_init_sw_modules().
1588 #define MTUREG(idx) (A_TP_MTU_REG0 + (idx) * 4)
1591 update_mtu_tab(ch_t
*adapter
)
1595 for (i
= 0; i
< NMTUS
; ++i
) {
1596 int mtu
= (unsigned int)adapter
->params
.mtus
[i
];
1598 t1_write_reg_4(adapter
, MTUREG(i
), mtu
);
1603 pe_change_mtu(ch_t
*chp
)
1605 struct cmac
*mac
= chp
->port
[0].mac
;
1608 if (!mac
->ops
->set_mtu
) {
1609 return (EOPNOTSUPP
);
1611 if (chp
->ch_mtu
< 68) {
1614 if (ret
= mac
->ops
->set_mtu(mac
, chp
->ch_mtu
)) {
1621 typedef struct fake_arp
{
1622 char fa_dst
[6]; /* ethernet header */
1623 char fa_src
[6]; /* ethernet header */
1624 ushort_t fa_typ
; /* ethernet header */
1626 ushort_t fa_hrd
; /* arp */
1639 * construct packet in mblk and attach it to sge structure.
1642 pe_make_fake_arp(ch_t
*chp
, unsigned char *arpp
)
1644 pesge
*sge
= chp
->sge
;
1647 static char buf
[6] = {0, 7, 0x43, 0, 0, 0};
1648 struct cpl_tx_pkt
*cpl
;
1650 bp
= allocb(sizeof (struct fake_arp
) + SZ_CPL_TX_PKT
, BPRI_HI
);
1654 bzero(bp
->b_rptr
, sizeof (struct fake_arp
) + SZ_CPL_TX_PKT
);
1656 /* fill in cpl header */
1657 cpl
= (struct cpl_tx_pkt
*)bp
->b_rptr
;
1658 cpl
->opcode
= CPL_TX_PKT
;
1659 cpl
->iff
= 0; /* XXX port 0 needs fixing with NEMO */
1660 cpl
->ip_csum_dis
= 1; /* no IP header cksum */
1661 cpl
->l4_csum_dis
= 1; /* no tcp/udp cksum */
1662 cpl
->vlan_valid
= 0; /* no vlan */
1664 fap
= (fake_arp_t
*)&bp
->b_rptr
[SZ_CPL_TX_PKT
];
1666 bcopy(arpp
, fap
, sizeof (*fap
)); /* copy first arp to mblk */
1668 bcopy(buf
, fap
->fa_dst
, 6); /* overwrite dst mac */
1669 chp
->ch_ip
= fap
->fa_src_ip
; /* not used yet */
1670 bcopy(buf
, fap
->fa_dst_mac
, 6); /* overwrite dst mac */
1672 bp
->b_wptr
= bp
->b_rptr
+ sizeof (struct fake_arp
)+SZ_CPL_TX_PKT
;
1674 sge_add_fake_arp(sge
, (void *)bp
);
1681 * free the fake arp's mblk on sge structure.
1684 pe_free_fake_arp(void *arp
)
1686 mblk_t
*bp
= (mblk_t
*)(arp
);
1692 * extract ip address of nic from first outgoing arp.
1695 pe_get_ip(unsigned char *arpp
)
1700 * first copy packet to buffer so we know
1701 * it will be properly aligned.
1703 bcopy(arpp
, &fap
, sizeof (fap
)); /* copy first arp to buffer */
1704 return (fap
.fa_src_ip
);
1709 t1_os_link_changed(ch_t
*obj
, int port_id
, int link_status
,
1710 int speed
, int duplex
, int fc
)
1712 gld_mac_info_t
*macinfo
= obj
->ch_macp
;
1714 gld_linkstate(macinfo
, GLD_LINKSTATE_UP
);
1716 * Link states should be reported to user
1717 * whenever it changes
1719 cmn_err(CE_NOTE
, "%s: link is up", adapter_name(obj
));
1721 gld_linkstate(macinfo
, GLD_LINKSTATE_DOWN
);
1723 * Link states should be reported to user
1724 * whenever it changes
1726 cmn_err(CE_NOTE
, "%s: link is down", adapter_name(obj
));