kernel/arch/sparc64/src/mm/tlb.c

   1 /*
   2  * Copyright (C) 2005 Jakub Jermar
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * - Redistributions of source code must retain the above copyright
  10  *   notice, this list of conditions and the following disclaimer.
  11  * - Redistributions in binary form must reproduce the above copyright
  12  *   notice, this list of conditions and the following disclaimer in the
  13  *   documentation and/or other materials provided with the distribution.
  14  * - The name of the author may not be used to endorse or promote products
  15  *   derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @addtogroup sparc64mm
  30  * @{
  31  */
  32 /** @file
  33  */
  34
  35 #include <arch/mm/tlb.h>
  36 #include <mm/tlb.h>
  37 #include <mm/as.h>
  38 #include <mm/asid.h>
  39 #include <arch/mm/frame.h>
  40 #include <arch/mm/page.h>
  41 #include <arch/mm/mmu.h>
  42 #include <arch/interrupt.h>
  43 #include <arch.h>
  44 #include <print.h>
  45 #include <arch/types.h>
  46 #include <typedefs.h>
  47 #include <config.h>
  48 #include <arch/trap/trap.h>
  49 #include <panic.h>
  50 #include <arch/asm.h>
  51 #include <symtab.h>
  52
  53 static void dtlb_pte_copy(pte_t *t, bool ro);
  54 static void itlb_pte_copy(pte_t *t);
  55 static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str);
  56 static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
  57 static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
  58
  59 char *context_encoding[] = {
  60         "Primary",
  61         "Secondary",
  62         "Nucleus",
  63         "Reserved"
  64 };
  65
  66 void tlb_arch_init(void)
  67 {
  68         /*
  69          * TLBs are actually initialized early
  70          * in start.S.
  71          */
  72 }
  73
  74 /** Insert privileged mapping into DMMU TLB.
  75  *
  76  * @param page Virtual page address.
  77  * @param frame Physical frame address.
  78  * @param pagesize Page size.
  79  * @param locked True for permanent mappings, false otherwise.
  80  * @param cacheable True if the mapping is cacheable, false otherwise.
  81  */
  82 void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
  83 {
  84         tlb_tag_access_reg_t tag;
  85         tlb_data_t data;
  86         page_address_t pg;
  87         frame_address_t fr;
  88
  89         pg.address = page;
  90         fr.address = frame;
  91
  92         tag.value = ASID_KERNEL;
  93         tag.vpn = pg.vpn;
  94
  95         dtlb_tag_access_write(tag.value);
  96
  97         data.value = 0;
  98         data.v = true;
  99         data.size = pagesize;
 100         data.pfn = fr.pfn;
 101         data.l = locked;
 102         data.cp = cacheable;
 103         data.cv = cacheable;
 104         data.p = true;
 105         data.w = true;
 106         data.g = true;
 107
 108         dtlb_data_in_write(data.value);
 109 }
 110
 111 /** Copy PTE to TLB.
 112  *
 113  * @param t Page Table Entry to be copied.
 114  * @param ro If true, the entry will be created read-only, regardless of its w field.
 115  */
 116 void dtlb_pte_copy(pte_t *t, bool ro)
 117 {
 118         tlb_tag_access_reg_t tag;
 119         tlb_data_t data;
 120         page_address_t pg;
 121         frame_address_t fr;
 122
 123         pg.address = t->page;
 124         fr.address = t->frame;
 125
 126         tag.value = 0;
 127         tag.context = t->as->asid;
 128         tag.vpn = pg.vpn;
 129
 130         dtlb_tag_access_write(tag.value);
 131
 132         data.value = 0;
 133         data.v = true;
 134         data.size = PAGESIZE_8K;
 135         data.pfn = fr.pfn;
 136         data.l = false;
 137         data.cp = t->c;
 138         data.cv = t->c;
 139         data.p = t->k;          /* p like privileged */
 140         data.w = ro ? false : t->w;
 141         data.g = t->g;
 142
 143         dtlb_data_in_write(data.value);
 144 }
 145
 146 void itlb_pte_copy(pte_t *t)
 147 {
 148         tlb_tag_access_reg_t tag;
 149         tlb_data_t data;
 150         page_address_t pg;
 151         frame_address_t fr;
 152
 153         pg.address = t->page;
 154         fr.address = t->frame;
 155
 156         tag.value = 0;
 157         tag.context = t->as->asid;
 158         tag.vpn = pg.vpn;
 159
 160         itlb_tag_access_write(tag.value);
 161
 162         data.value = 0;
 163         data.v = true;
 164         data.size = PAGESIZE_8K;
 165         data.pfn = fr.pfn;
 166         data.l = false;
 167         data.cp = t->c;
 168         data.cv = t->c;
 169         data.p = t->k;          /* p like privileged */
 170         data.w = false;
 171         data.g = t->g;
 172
 173         itlb_data_in_write(data.value);
 174 }
 175
 176 /** ITLB miss handler. */
 177 void fast_instruction_access_mmu_miss(int n, istate_t *istate)
 178 {
 179         uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
 180         pte_t *t;
 181
 182         page_table_lock(AS, true);
 183         t = page_mapping_find(AS, va);
 184         if (t && PTE_EXECUTABLE(t)) {
 185                 /*
 186                  * The mapping was found in the software page hash table.
 187                  * Insert it into ITLB.
 188                  */
 189                 t->a = true;
 190                 itlb_pte_copy(t);
 191                 page_table_unlock(AS, true);
 192         } else {
 193                 /*
 194                  * Forward the page fault to the address space page fault handler.
 195                  */
 196                 page_table_unlock(AS, true);
 197                 if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
 198                         do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
 199                 }
 200         }
 201 }
 202
 203 /** DTLB miss handler.
 204  *
 205  * Note that some faults (e.g. kernel faults) were already resolved
 206  * by the low-level, assembly language part of the fast_data_access_mmu_miss
 207  * handler.
 208  */
 209 void fast_data_access_mmu_miss(int n, istate_t *istate)
 210 {
 211         tlb_tag_access_reg_t tag;
 212         uintptr_t va;
 213         pte_t *t;
 214
 215         tag.value = dtlb_tag_access_read();
 216         va = tag.vpn << PAGE_WIDTH;
 217
 218         if (tag.context == ASID_KERNEL) {
 219                 if (!tag.vpn) {
 220                         /* NULL access in kernel */
 221                         do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
 222                 }
 223                 do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
 224         }
 225
 226         page_table_lock(AS, true);
 227         t = page_mapping_find(AS, va);
 228         if (t) {
 229                 /*
 230                  * The mapping was found in the software page hash table.
 231                  * Insert it into DTLB.
 232                  */
 233                 t->a = true;
 234                 dtlb_pte_copy(t, true);
 235                 page_table_unlock(AS, true);
 236         } else {
 237                 /*
 238                  * Forward the page fault to the address space page fault handler.
 239                  */
 240                 page_table_unlock(AS, true);
 241                 if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
 242                         do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
 243                 }
 244         }
 245 }
 246
 247 /** DTLB protection fault handler. */
 248 void fast_data_access_protection(int n, istate_t *istate)
 249 {
 250         tlb_tag_access_reg_t tag;
 251         uintptr_t va;
 252         pte_t *t;
 253
 254         tag.value = dtlb_tag_access_read();
 255         va = tag.vpn << PAGE_WIDTH;
 256
 257         page_table_lock(AS, true);
 258         t = page_mapping_find(AS, va);
 259         if (t && PTE_WRITABLE(t)) {
 260                 /*
 261                  * The mapping was found in the software page hash table and is writable.
 262                  * Demap the old mapping and insert an updated mapping into DTLB.
 263                  */
 264                 t->a = true;
 265                 t->d = true;
 266                 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
 267                 dtlb_pte_copy(t, false);
 268                 page_table_unlock(AS, true);
 269         } else {
 270                 /*
 271                  * Forward the page fault to the address space page fault handler.
 272                  */
 273                 page_table_unlock(AS, true);
 274                 if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
 275                         do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
 276                 }
 277         }
 278 }
 279
 280 /** Print contents of both TLBs. */
 281 void tlb_print(void)
 282 {
 283         int i;
 284         tlb_data_t d;
 285         tlb_tag_read_reg_t t;
 286
 287         printf("I-TLB contents:\n");
 288         for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
 289                 d.value = itlb_data_access_read(i);
 290                 t.value = itlb_tag_read_read(i);
 291
 292                 printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
 293                         i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
 294         }
 295
 296         printf("D-TLB contents:\n");
 297         for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
 298                 d.value = dtlb_data_access_read(i);
 299                 t.value = dtlb_tag_read_read(i);
 300
 301                 printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
 302                         i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
 303         }
 304
 305 }
 306
 307 void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str)
 308 {
 309         char *tpc_str = get_symtab_entry(istate->tpc);
 310
 311         printf("TPC=%p, (%s)\n", istate->tpc, tpc_str);
 312         panic("%s\n", str);
 313 }
 314
 315 void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
 316 {
 317         uintptr_t va;
 318         char *tpc_str = get_symtab_entry(istate->tpc);
 319
 320         va = tag.vpn << PAGE_WIDTH;
 321
 322         printf("Faulting page: %p, ASID=%d\n", va, tag.context);
 323         printf("TPC=%p, (%s)\n", istate->tpc, tpc_str);
 324         panic("%s\n", str);
 325 }
 326
 327 void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
 328 {
 329         uintptr_t va;
 330         char *tpc_str = get_symtab_entry(istate->tpc);
 331
 332         va = tag.vpn << PAGE_WIDTH;
 333
 334         printf("Faulting page: %p, ASID=%d\n", va, tag.context);
 335         printf("TPC=%p, (%s)\n", istate->tpc, tpc_str);
 336         panic("%s\n", str);
 337 }
 338
 339 /** Invalidate all unlocked ITLB and DTLB entries. */
 340 void tlb_invalidate_all(void)
 341 {
 342         int i;
 343         tlb_data_t d;
 344         tlb_tag_read_reg_t t;
 345
 346         for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
 347                 d.value = itlb_data_access_read(i);
 348                 if (!d.l) {
 349                         t.value = itlb_tag_read_read(i);
 350                         d.v = false;
 351                         itlb_tag_access_write(t.value);
 352                         itlb_data_access_write(i, d.value);
 353                 }
 354         }
 355
 356         for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
 357                 d.value = dtlb_data_access_read(i);
 358                 if (!d.l) {
 359                         t.value = dtlb_tag_read_read(i);
 360                         d.v = false;
 361                         dtlb_tag_access_write(t.value);
 362                         dtlb_data_access_write(i, d.value);
 363                 }
 364         }
 365
 366 }
 367
 368 /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
 369  *
 370  * @param asid Address Space ID.
 371  */
 372 void tlb_invalidate_asid(asid_t asid)
 373 {
 374         tlb_context_reg_t pc_save, ctx;
 375
 376         /* switch to nucleus because we are mapped by the primary context */
 377         nucleus_enter();
 378
 379         ctx.v = pc_save.v = mmu_primary_context_read();
 380         ctx.context = asid;
 381         mmu_primary_context_write(ctx.v);
 382
 383         itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
 384         dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
 385
 386         mmu_primary_context_write(pc_save.v);
 387
 388         nucleus_leave();
 389 }
 390
 391 /** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
 392  *
 393  * @param asid Address Space ID.
 394  * @param page First page which to sweep out from ITLB and DTLB.
 395  * @param cnt Number of ITLB and DTLB entries to invalidate.
 396  */
 397 void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
 398 {
 399         int i;
 400         tlb_context_reg_t pc_save, ctx;
 401
 402         /* switch to nucleus because we are mapped by the primary context */
 403         nucleus_enter();
 404
 405         ctx.v = pc_save.v = mmu_primary_context_read();
 406         ctx.context = asid;
 407         mmu_primary_context_write(ctx.v);
 408
 409         for (i = 0; i < cnt; i++) {
 410                 itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
 411                 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
 412         }
 413
 414         mmu_primary_context_write(pc_save.v);
 415
 416         nucleus_leave();
 417 }
 418
 419 /** @}
 420  */