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[helenos.git] / kernel / arch / mips32 / include / mm / page.h
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1 /*
2 * Copyright (c) 2003-2004 Jakub Jermar
3 * All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 /** @addtogroup mips32mm
30 * @{
32 /** @file
35 #ifndef KERN_mips32_PAGE_H_
36 #define KERN_mips32_PAGE_H_
38 #include <arch/mm/frame.h>
40 #define PAGE_WIDTH FRAME_WIDTH
41 #define PAGE_SIZE FRAME_SIZE
43 #define PAGE_COLOR_BITS 0 /* dummy */
45 #ifndef __ASM__
46 # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
47 # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
48 #else
49 # define KA2PA(x) ((x) - 0x80000000)
50 # define PA2KA(x) ((x) + 0x80000000)
51 #endif
53 #ifdef KERNEL
56 * Implementation of generic 4-level page table interface.
58 * Page table layout:
59 * - 32-bit virtual addresses
60 * - Offset is 14 bits => pages are 16K long
61 * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
62 * - PTE's replace EntryLo v (valid) bit with p (present) bit
63 * - PTE's use only one bit to distinguish between cacheable and uncacheable mappings
64 * - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared
65 * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed)
66 * - PTL0 has 64 entries (6 bits)
67 * - PTL1 is not used
68 * - PTL2 is not used
69 * - PTL3 has 4096 entries (12 bits)
72 #define PTL0_ENTRIES_ARCH 64
73 #define PTL1_ENTRIES_ARCH 0
74 #define PTL2_ENTRIES_ARCH 0
75 #define PTL3_ENTRIES_ARCH 4096
77 #define PTL0_INDEX_ARCH(vaddr) ((vaddr)>>26)
78 #define PTL1_INDEX_ARCH(vaddr) 0
79 #define PTL2_INDEX_ARCH(vaddr) 0
80 #define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>14) & 0xfff)
82 #define SET_PTL0_ADDRESS_ARCH(ptl0)
84 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].pfn<<12)
85 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
86 #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
87 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].pfn<<12)
89 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
90 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
91 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
92 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
94 #define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i))
95 #define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
96 #define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
97 #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i))
99 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
100 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
101 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
102 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
104 #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0)
105 #define PTE_PRESENT_ARCH(pte) ((pte)->p != 0)
106 #define PTE_GET_FRAME_ARCH(pte) ((pte)->pfn<<12)
107 #define PTE_WRITABLE_ARCH(pte) ((pte)->w != 0)
108 #define PTE_EXECUTABLE_ARCH(pte) 1
110 #ifndef __ASM__
112 #include <arch/mm/tlb.h>
113 #include <mm/page.h>
114 #include <arch/mm/frame.h>
115 #include <arch/types.h>
117 static inline int get_pt_flags(pte_t *pt, index_t i)
119 pte_t *p = &pt[i];
121 return (
122 (p->cacheable<<PAGE_CACHEABLE_SHIFT) |
123 ((!p->p)<<PAGE_PRESENT_SHIFT) |
124 (1<<PAGE_USER_SHIFT) |
125 (1<<PAGE_READ_SHIFT) |
126 ((p->w)<<PAGE_WRITE_SHIFT) |
127 (1<<PAGE_EXEC_SHIFT) |
128 (p->g<<PAGE_GLOBAL_SHIFT)
133 static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
135 pte_t *p = &pt[i];
137 p->cacheable = (flags & PAGE_CACHEABLE) != 0;
138 p->p = !(flags & PAGE_NOT_PRESENT);
139 p->g = (flags & PAGE_GLOBAL) != 0;
140 p->w = (flags & PAGE_WRITE) != 0;
143 * Ensure that valid entries have at least one bit set.
145 p->soft_valid = 1;
148 extern void page_arch_init(void);
150 #endif /* __ASM__ */
152 #endif /* KERNEL */
154 #endif
156 /** @}