kernel/arch/amd64/src/cpu/cpu.c

   1 /*
   2  * Copyright (c) 2001-2004 Jakub Jermar
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * - Redistributions of source code must retain the above copyright
  10  *   notice, this list of conditions and the following disclaimer.
  11  * - Redistributions in binary form must reproduce the above copyright
  12  *   notice, this list of conditions and the following disclaimer in the
  13  *   documentation and/or other materials provided with the distribution.
  14  * - The name of the author may not be used to endorse or promote products
  15  *   derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @addtogroup amd64
  30  * @{
  31  */
  32 /** @file
  33  */
  34
  35 #include <arch/cpu.h>
  36 #include <arch/cpuid.h>
  37 #include <arch/pm.h>
  38
  39 #include <arch.h>
  40 #include <arch/types.h>
  41 #include <print.h>
  42 #include <typedefs.h>
  43 #include <fpu_context.h>
  44
  45 /*
  46  * Identification of CPUs.
  47  * Contains only non-MP-Specification specific SMP code.
  48  */
  49 #define AMD_CPUID_EBX   0x68747541
  50 #define AMD_CPUID_ECX   0x444d4163
  51 #define AMD_CPUID_EDX   0x69746e65
  52
  53 #define INTEL_CPUID_EBX 0x756e6547
  54 #define INTEL_CPUID_ECX 0x6c65746e
  55 #define INTEL_CPUID_EDX 0x49656e69
  56
  57
  58 enum vendor {
  59         VendorUnknown=0,
  60         VendorAMD,
  61         VendorIntel
  62 };
  63
  64 static char *vendor_str[] = {
  65         "Unknown Vendor",
  66         "AuthenticAMD",
  67         "GenuineIntel"
  68 };
  69
  70
  71 /** Setup flags on processor so that we can use the FPU
  72  *
  73  * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
  74  * cr0.em = 0 -> we do not emulate coprocessor
  75  * cr0.mp = 1 -> we do want lazy context switch
  76  */
  77 void cpu_setup_fpu(void)
  78 {
  79         __asm__ volatile (
  80                 "movq %%cr0, %%rax;"
  81                 "btsq $1, %%rax;" /* cr0.mp */
  82                 "btrq $2, %%rax;"  /* cr0.em */
  83                 "movq %%rax, %%cr0;"
  84
  85                 "movq %%cr4, %%rax;"
  86                 "bts $9, %%rax;" /* cr4.osfxsr */
  87                 "movq %%rax, %%cr4;"
  88                 :
  89                 :
  90                 :"%rax"
  91                 );
  92 }
  93
  94 /** Set the TS flag to 1.
  95  *
  96  * If a thread accesses coprocessor, exception is run, which
  97  * does a lazy fpu context switch.
  98  *
  99  */
 100 void fpu_disable(void)
 101 {
 102         __asm__ volatile (
 103                 "mov %%cr0,%%rax;"
 104                 "bts $3,%%rax;"
 105                 "mov %%rax,%%cr0;"
 106                 :
 107                 :
 108                 :"%rax"
 109                 );
 110 }
 111
 112 void fpu_enable(void)
 113 {
 114         __asm__ volatile (
 115                 "mov %%cr0,%%rax;"
 116                 "btr $3,%%rax;"
 117                 "mov %%rax,%%cr0;"
 118                 :
 119                 :
 120                 :"%rax"
 121                 );
 122 }
 123
 124 void cpu_arch_init(void)
 125 {
 126         CPU->arch.tss = tss_p;
 127         CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);
 128         CPU->fpu_owner = NULL;
 129 }
 130
 131 void cpu_identify(void)
 132 {
 133         cpu_info_t info;
 134
 135         CPU->arch.vendor = VendorUnknown;
 136         if (has_cpuid()) {
 137                 cpuid(0, &info);
 138
 139                 /*
 140                  * Check for AMD processor.
 141                  */
 142                 if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
 143                         CPU->arch.vendor = VendorAMD;
 144                 }
 145
 146                 /*
 147                  * Check for Intel processor.
 148                  */
 149                 if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
 150                         CPU->arch.vendor = VendorIntel;
 151                 }
 152
 153                 cpuid(1, &info);
 154                 CPU->arch.family = (info.cpuid_eax>>8)&0xf;
 155                 CPU->arch.model = (info.cpuid_eax>>4)&0xf;
 156                 CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
 157         }
 158 }
 159
 160 void cpu_print_report(cpu_t* m)
 161 {
 162         printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
 163                 m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
 164                 m->frequency_mhz);
 165 }
 166
 167 /** @}
 168  */