2 * Copyright (C) 2005 - 2006 Jakub Jermar
3 * Copyright (C) 2006 Jakub Vana
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 /** @addtogroup ia64mm
36 #ifndef KERN_ia64_PAGE_H_
37 #define KERN_ia64_PAGE_H_
39 #include <arch/mm/frame.h>
41 #define PAGE_SIZE FRAME_SIZE
42 #define PAGE_WIDTH FRAME_WIDTH
44 #define PAGE_COLOR_BITS 0 /* dummy */
48 /** Bit width of the TLB-locked portion of kernel address space. */
49 #define KERNEL_PAGE_WIDTH 28 /* 256M */
54 #define VRN_MASK (7LL << VRN_SHIFT)
55 #define VA2VRN(va) ((va)>>VRN_SHIFT)
60 #define VRN_KERNEL 7LL
63 #define REGION_REGISTERS 8
65 #define KA2PA(x) ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT)))
66 #define PA2KA(x) ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT)))
68 #define VHPT_WIDTH 20 /* 1M */
69 #define VHPT_SIZE (1 << VHPT_WIDTH)
71 #define PTA_BASE_SHIFT 15
73 /** Memory Attributes. */
74 #define MA_WRITEBACK 0x0
75 #define MA_UNCACHEABLE 0x4
77 /** Privilege Levels. Only the most and the least privileged ones are ever used. */
81 /* Access Rigths. Only certain combinations are used by the kernel. */
83 #define AR_EXECUTE 0x1
88 #include <arch/mm/frame.h>
89 #include <arch/barrier.h>
90 #include <genarch/mm/page_ht.h>
91 #include <arch/mm/asid.h>
92 #include <arch/types.h>
96 struct vhpt_tag_info
{
97 unsigned long long tag
: 63;
99 } __attribute__ ((packed
));
102 struct vhpt_tag_info tag_info
;
106 struct vhpt_entry_present
{
115 unsigned long long ppn
: 38;
131 } __attribute__ ((packed
));
133 struct vhpt_entry_not_present
{
136 unsigned long long ig0
: 52;
142 unsigned long long ig2
: 56;
149 } __attribute__ ((packed
));
151 typedef union vhpt_entry
{
152 struct vhpt_entry_present present
;
153 struct vhpt_entry_not_present not_present
;
157 struct region_register_map
{
163 } __attribute__ ((packed
));
165 typedef union region_register
{
166 struct region_register_map map
;
167 unsigned long long word
;
170 struct pta_register_map
{
176 unsigned long long base
: 49;
177 } __attribute__ ((packed
));
179 typedef union pta_register
{
180 struct pta_register_map map
;
184 /** Return Translation Hashed Entry Address.
186 * VRN bits are used to read RID (ASID) from one
187 * of the eight region registers registers.
189 * @param va Virtual address including VRN bits.
191 * @return Address of the head of VHPT collision chain.
193 static inline uint64_t thash(uint64_t va
)
197 __asm__
volatile ("thash %0 = %1\n" : "=r" (ret
) : "r" (va
));
202 /** Return Translation Hashed Entry Tag.
204 * VRN bits are used to read RID (ASID) from one
205 * of the eight region registers.
207 * @param va Virtual address including VRN bits.
209 * @return The unique tag for VPN and RID in the collision chain returned by thash().
211 static inline uint64_t ttag(uint64_t va
)
215 __asm__
volatile ("ttag %0 = %1\n" : "=r" (ret
) : "r" (va
));
220 /** Read Region Register.
222 * @param i Region register index.
224 * @return Current contents of rr[i].
226 static inline uint64_t rr_read(index_t i
)
229 ASSERT(i
< REGION_REGISTERS
);
230 __asm__
volatile ("mov %0 = rr[%1]\n" : "=r" (ret
) : "r" (i
<< VRN_SHIFT
));
234 /** Write Region Register.
236 * @param i Region register index.
237 * @param v Value to be written to rr[i].
239 static inline void rr_write(index_t i
, uint64_t v
)
241 ASSERT(i
< REGION_REGISTERS
);
245 : "r" (i
<< VRN_SHIFT
), "r" (v
)
249 /** Read Page Table Register.
251 * @return Current value stored in PTA.
253 static inline uint64_t pta_read(void)
257 __asm__
volatile ("mov %0 = cr.pta\n" : "=r" (ret
));
262 /** Write Page Table Register.
264 * @param v New value to be stored in PTA.
266 static inline void pta_write(uint64_t v
)
268 __asm__
volatile ("mov cr.pta = %0\n" : : "r" (v
));
271 extern void page_arch_init(void);
273 extern vhpt_entry_t
*vhpt_hash(uintptr_t page
, asid_t asid
);
274 extern bool vhpt_compare(uintptr_t page
, asid_t asid
, vhpt_entry_t
*v
);
275 extern void vhpt_set_record(vhpt_entry_t
*v
, uintptr_t page
, asid_t asid
, uintptr_t frame
, int flags
);