kernel/genarch/include/genarch/drivers/amdm37x/uart_regs.h

   1 /*
   2  * Copyright (c) 2012 Jan Vesely
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * - Redistributions of source code must retain the above copyright
  10  *   notice, this list of conditions and the following disclaimer.
  11  * - Redistributions in binary form must reproduce the above copyright
  12  *   notice, this list of conditions and the following disclaimer in the
  13  *   documentation and/or other materials provided with the distribution.
  14  * - The name of the author may not be used to endorse or promote products
  15  *   derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28 /** @addtogroup genarch
  29  * @{
  30  */
  31 /**
  32  * @file
  33  * @brief Texas Instruments AMDM37x UART memory mapped registers.
  34  */
  35
  36 #ifndef KERN_AMDM37x_UART_H_
  37 #define KERN_AMDM37x_UART_H_
  38
  39 #include <typedefs.h>
  40 #include <console/chardev.h>
  41 #include <ddi/irq.h>
  42
  43 typedef struct {
  44         union {
  45                 /** Stores lower part of the 14-bit baud divisor */
  46                 ioport32_t dll;
  47 #define AMDM37x_UART_DLL_MASK   (0xff)
  48
  49                 /** Receive holding register */
  50                 const ioport32_t rhr;
  51 #define AMDM37x_UART_RHR_MASK   (0xff)
  52
  53                 /** Transmit holding register */
  54                 ioport32_t thr;
  55 #define AMDM37x_UART_THR_MASK   (0xff)
  56         };
  57
  58         union {
  59                 /** Stores higher part of the 14-bit baud divisor */
  60                 ioport32_t dlh;
  61 #define AMDM37x_UART_DLH_MASK   (0x1f)
  62
  63                 /** Interrupt enable registers */
  64                 ioport32_t ier;
  65 #define AMDM37x_UART_IER_RHR_IRQ_FLAG   (1 << 0)
  66 #define AMDM37x_UART_IER_THR_IRQ_FLAG   (1 << 1)
  67 #define AMDM37x_UART_IER_LINE_STS_IRQ_FLAG   (1 << 2)
  68 #define AMDM37x_UART_IER_MODEM_STS_IRQ_FLAG   (1 << 3)
  69 #define AMDM37x_UART_IER_SLEEP_MODE_FLAG   (1 << 4)
  70 #define AMDM37x_UART_IER_XOFF_IRQ_FLAG   (1 << 5)
  71 #define AMDM37x_UART_IER_RTS_IRQ_FLAG   (1 << 6)
  72 #define AMDM37x_UART_IER_CTS_IRQ_FLAG   (1 << 7)
  73
  74 #define AMDM37x_CIR_IER_RHR_IRQ_FLAG   (1 << 0)
  75 #define AMDM37x_CIR_IER_THR_IRQ_FLAG   (1 << 1)
  76 #define AMDM37x_CIR_IER_RX_STOP_IRQ_FLAG   (1 << 2)
  77 #define AMDM37x_CIR_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
  78 #define AMDM37x_CIR_IER_TX_STS_IRQ_FLAG   (1 << 5)
  79
  80 #define AMDM37x_IRDA_IER_RHR_IRQ_FLAG   (1 << 0)
  81 #define AMDM37x_IRDA_IER_THR_IRQ_FLAG   (1 << 1)
  82 #define AMDM37x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG   (1 << 2)
  83 #define AMDM37x_IRDA_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
  84 #define AMDM37x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG   (1 << 4)
  85 #define AMDM37x_IRDA_IER_TX_STS_IRQ_FLAG   (1 << 5)
  86 #define AMDM37x_IRDA_IER_LINE_STS_IRQ_FLAG   (1 << 6)
  87 #define AMDM37x_IRDA_IER_EOF_IRQ_FLAG   (1 << 7)
  88         };
  89
  90         union {
  91                 /** Interrupt identification register */
  92                 const ioport32_t iir;
  93 #define AMDM37x_UART_IIR_IRQ_PENDING_FLAG   (1 << 0)
  94 #define AMDM37x_UART_IIR_TYPE_MASK   (0x1f)
  95 #define AMDM37x_UART_IIR_TYPE_SHIFT   (1)
  96 #define AMDM37x_UART_IIR_FCR_MASK   (0x3)
  97 #define AMDM37x_UART_IIR_FCR_SHIFT   (6)
  98
  99 #define AMDM37x_CIR_IIR_RHR_IRQ_FLAG   (1 << 0)
 100 #define AMDM37x_CIR_IIR_THR_IRQ_FLAG   (1 << 1)
 101 #define AMDM37x_CIR_IIR_RX_STOP_IRQ_FLAG   (1 << 2)
 102 #define AMDM37x_CIR_IIR_RX_OE_IRQ_FLAG   (1 << 3)
 103 #define AMDM37x_CIR_IIR_TX_STS_IRQ_FLAG   (1 << 5)
 104
 105 #define AMDM37x_IRDA_IIR_RHR_IRQ_FLAG   (1 << 0)
 106 #define AMDM37x_IRDA_IIR_THR_IRQ_FLAG   (1 << 1)
 107 #define AMDM37x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG   (1 << 2)
 108 #define AMDM37x_IRDA_IIR_RX_OE_IRQ_FLAG   (1 << 3)
 109 #define AMDM37x_IRDA_IIR_STS_FIFO_IRQ_FLAG   (1 << 4)
 110 #define AMDM37x_IRDA_IIR_TX_STS_IRQ_FLAG   (1 << 5)
 111 #define AMDM37x_IRDA_IIR_LINE_STS_IRQ_FLAG   (1 << 6)
 112 #define AMDM37x_IRDA_IIR_EOF_IRQ_FLAG   (1 << 7)
 113
 114                 /** FIFO control register */
 115                 ioport32_t fcr;
 116 #define AMDM37x_UART_FCR_FIFO_EN_FLAG   (1 << 0)
 117 #define AMDM37x_UART_FCR_RX_FIFO_CLR_FLAG   (1 << 1)
 118 #define AMDM37x_UART_FCR_TX_FIFO_CLR_FLAG   (1 << 3)
 119 #define AMDM37x_UART_FCR_DMA_MODE_FLAG   (1 << 4)
 120
 121 #define AMDM37x_UART_FCR_TX_FIFO_TRIG_MASK   (0x3)
 122 #define AMDM37x_UART_FCR_TX_FIFO_TRIG_SHIFT   (4)
 123
 124 #define AMDM37x_UART_FCR_RX_FIFO_TRIG_MASK   (0x3)
 125 #define AMDM37x_UART_FCR_RX_FIFO_TRIG_SHIFT   (6)
 126
 127                 /** Enhanced feature register */
 128                 ioport32_t efr;
 129 #define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_MASK   (0x3)
 130 #define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT   (0)
 131 #define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_MASK   (0x3)
 132 #define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT   (2)
 133
 134 #define AMDM37x_UART_EFR_SW_FLOW_CTRL_NONE   (0x0)
 135 #define AMDM37x_UART_EFR_SW_FLOW_CTRL_X2   (0x1)
 136 #define AMDM37x_UART_EFR_SW_FLOW_CTRL_X1   (0x2)
 137 #define AMDM37x_UART_EFR_SW_FLOW_CTRL_XBOTH   (0x3)
 138
 139 #define AMDM37x_UART_EFR_ENH_FLAG   (1 << 4)
 140 #define AMDM37x_UART_EFR_SPEC_CHAR_FLAG   (1 << 5)
 141 #define AMDM37x_UART_EFR_AUTO_RTS_EN_FLAG   (1 << 6)
 142 #define AMDM37x_UART_EFR_AUTO_CTS_EN_FLAG   (1 << 7)
 143         };
 144
 145         /** Line control register */
 146         ioport32_t lcr;
 147 #define AMDM37x_UART_LCR_CHAR_LENGTH_MASK   (0x3)
 148 #define AMDM37x_UART_LCR_CHAR_LENGTH_SHIFT   (0)
 149 #define AMDM37x_UART_LCR_CHAR_LENGTH_5BITS   (0x0)
 150 #define AMDM37x_UART_LCR_CHAR_LENGTH_6BITS   (0x1)
 151 #define AMDM37x_UART_LCR_CHAR_LENGTH_7BITS   (0x2)
 152 #define AMDM37x_UART_LCR_CHAR_LENGTH_8BITS   (0x3)
 153 #define AMDM37x_UART_LCR_NB_STOP_FLAG   (1 << 2)
 154 #define AMDM37x_UART_LCR_PARITY_EN_FLAG   (1 << 3)
 155 #define AMDM37x_UART_LCR_PARITY_TYPE1_FLAG   (1 << 4)
 156 #define AMDM37x_UART_LCR_PARITY_TYPE2_FLAG   (1 << 5)
 157 #define AMDM37x_UART_LCR_BREAK_EN_FLAG   (1 << 6)
 158 #define AMDM37x_UART_LCR_DIV_EN_FLAG   (1 << 7)
 159
 160
 161         union {
 162                 /** Modem control register */
 163                 ioport32_t mcr;
 164 #define AMDM37x_UART_MCR_DTR_FLAG   (1 << 0)
 165 #define AMDM37x_UART_MCR_RTS_FLAG   (1 << 1)
 166 #define AMDM37x_UART_MCR_RI_STS_CH_FLAG   (1 << 2)
 167 #define AMDM37x_UART_MCR_CD_STS_CH_FLAG   (1 << 3)
 168 #define AMDM37x_UART_MCR_LOOPBACK_EN_FLAG   (1 << 4)
 169 #define AMDM37x_UART_MCR_XON_EN_FLAG   (1 << 5)
 170 #define AMDM37x_UART_MCR_TCR_TLR_FLAG   (1 << 6)
 171
 172                 /** UART: XON1 char, IRDA: ADDR1 address */
 173                 ioport32_t xon1_addr1;
 174 #define AMDM37x_UART_XON1_ADDR1_MASK   (0xff)
 175         };
 176
 177         union {
 178                 /** Line status register */
 179                 const ioport32_t lsr;
 180 #define AMDM37x_UART_LSR_RX_FIFO_E_FLAG   (1 << 0)
 181 #define AMDM37x_UART_LSR_RX_OE_FLAG   (1 << 1)
 182 #define AMDM37x_UART_LSR_RX_PE_FLAG   (1 << 2)
 183 #define AMDM37x_UART_LSR_RX_FE_FLAG   (1 << 3)
 184 #define AMDM37x_UART_LSR_RX_BI_FLAG   (1 << 4)
 185 #define AMDM37x_UART_LSR_TX_FIFO_E_FLAG   (1 << 5)
 186 #define AMDM37x_UART_LSR_TX_SR_E_FLAG   (1 << 6)
 187 #define AMDM37x_UART_LSR_RX_FIFO_STS_FLAG   (1 << 7)
 188
 189 #define AMDM37x_CIR_LSR_RX_FIFO_E_FLAG   (1 << 0)
 190 #define AMDM37x_CIR_LSR_RX_STOP_FLAG   (1 << 5)
 191 #define AMDM37x_CIR_LSR_THR_EMPTY_FLAG   (1 << 7)
 192
 193 #define AMDM37x_IRDA_LSR_RX_FIFO_E_FLAG   (1 << 0)
 194 #define AMDM37x_IRDA_LSR_STS_FIFO_E_FLAG   (1 << 1)
 195 #define AMDM37x_IRDA_LSR_CRC_FLAG   (1 << 2)
 196 #define AMDM37x_IRDA_LSR_ABORT_FLAG   (1 << 3)
 197 #define AMDM37x_IRDA_LSR_FTL_FLAG   (1 << 4)
 198 #define AMDM37x_IRDA_LSR_RX_LAST_FLAG   (1 << 5)
 199 #define AMDM37x_IRDA_LSR_STS_FIFO_FULL_FLAG   (1 << 6)
 200 #define AMDM37x_IRDA_LSR_THR_EMPTY_FLAG   (1 << 7)
 201
 202                 /** UART: XON2 char, IRDA: ADDR2 address */
 203                 ioport32_t xon2_addr2;
 204         };
 205
 206         union {
 207                 /** Modem status register */
 208                 const ioport32_t msr;
 209 #define AMDM37x_UART_MSR_CTS_STS_FLAG   (1 << 0)
 210 #define AMDM37x_UART_MSR_DSR_STS_FLAG   (1 << 1)
 211 #define AMDM37x_UART_MSR_RI_STS_FLAG   (1 << 2)
 212 #define AMDM37x_UART_MSR_DCD_STS_FLAG   (1 << 3)
 213 #define AMDM37x_UART_MSR_NCTS_STS_FLAG   (1 << 4)
 214 #define AMDM37x_UART_MSR_NDSR_STS_FLAG   (1 << 5)
 215 #define AMDM37x_UART_MSR_NRI_STS_FLAG   (1 << 6)
 216 #define AMDM37x_UART_MSR_NCD_STS_FLAG   (1 << 7)
 217
 218                 /** Transmission control register */
 219                 ioport32_t tcr;
 220 #define AMDM37x_UART_TCR_FIFO_TRIG_MASK   (0xf)
 221 #define AMDM37x_UART_TCR_FIFO_TRIG_HALT_SHIFT   (0)
 222 #define AMDM37x_UART_TCR_FIFO_TRIG_START_SHIFT   (4)
 223
 224                 /** UART: XOFF1 char */
 225                 ioport32_t xoff1;
 226 #define AMDM37x_UART_XOFF1_MASK   (0xff)
 227         };
 228
 229         union {
 230                 /* Scratchpad register, does nothing */
 231                 ioport32_t spr;
 232 #define AMDM37x_UART_SPR_MASK   (0xff)
 233
 234                 /* Trigger level register */
 235                 ioport32_t tlr;
 236 #define AMDM37x_UART_TLR_LEVEL_MASK   (0xf)
 237 #define AMDM37x_UART_TLR_TX_FIFO_TRIG_SHIFT   (0)
 238 #define AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT   (4)
 239
 240                 /** UART: XOFF2 char */
 241                 ioport32_t xoff2;
 242 #define AMDM37x_UART_XOFF2_MASK   (0xff)
 243         };
 244
 245         /** Mode definition register. */
 246         ioport32_t mdr1;
 247 #define AMDM37x_UART_MDR_MS_MASK   (0x7)
 248 #define AMDM37x_UART_MDR_MS_SHIFT   (0)
 249 #define AMDM37x_UART_MDR_MS_UART16   (0x0)
 250 #define AMDM37x_UART_MDR_MS_SIR   (0x1)
 251 #define AMDM37x_UART_MDR_MS_UART16_AUTO   (0x2)
 252 #define AMDM37x_UART_MDR_MS_UART13   (0x3)
 253 #define AMDM37x_UART_MDR_MS_MIR   (0x4)
 254 #define AMDM37x_UART_MDR_MS_FIR   (0x5)
 255 #define AMDM37x_UART_MDR_MS_CIR   (0x6)
 256 #define AMDM37x_UART_MDR_MS_DISABLE   (0x7)
 257
 258 #define AMDM37x_UART_MDR_IR_SLEEP_FLAG   (1 << 3)
 259 #define AMDM37x_UART_MDR_SET_TXIR_FLAG   (1 << 4)
 260 #define AMDM37x_UART_MDR_SCT_FLAG   (1 << 5)
 261 #define AMDM37x_UART_MDR_SIP_FLAG   (1 << 6)
 262 #define AMDM37x_UART_MDR_FRAME_END_MODE_FLAG   (1 << 7)
 263
 264         /** Mode definition register */
 265         ioport32_t mdr2;
 266 #define AMDM37x_UART_MDR_IRTX_UNDERRUN_FLAG   (1 << 0)
 267 #define AMDM37x_UART_MDR_STS_FIFO_TRIG_MASK   (0x3)
 268 #define AMDM37x_UART_MDR_STS_FIFO_TRIG_SHIFT   (1)
 269 #define AMDM37x_UART_MDR_PULSE_SHAPING_FLAG   (1 << 3)
 270 #define AMDM37x_UART_MDR_CIR_PULSE_MODE_MASK   (0x3)
 271 #define AMDM37x_UART_MDR_CIR_PULSE_MODE_SHIFT   (4)
 272 #define AMDM37x_UART_MDR_IRRXINVERT_FLAG   (1 << 6)
 273
 274
 275         /* UART3 specific */
 276         union {
 277                 /** Status FIFO line status register (IrDA only) */
 278                 const ioport32_t sflsr;
 279 #define AMDM37x_IRDA_SFLSR_CRC_ERROR_FLAG   (1 << 1)
 280 #define AMDM37x_IRDA_SFLSR_ABORT_FLAG   (1 << 2)
 281 #define AMDM37x_IRDA_SFLSR_FTL_FLAG   (1 << 3)
 282 #define AMDM37x_IRDA_SFLSR_OE_FLAG   (1 << 4)
 283
 284                 /** Transmit frame length low (IrDA only) */
 285                 ioport32_t txfll;
 286 #define AMDM37x_UART_TXFLL_MASK   (0xff)
 287         };
 288
 289         /* UART3 specific */
 290         union {
 291                 /** Dummy register to restart TX or RX (IrDA only) */
 292                 const ioport32_t resume;
 293                 /** Transmit frame length high (IrDA only) */
 294                 ioport32_t txflh;
 295 #define AMDM37x_UART_TXFLH_MASK   (0xff)
 296         };
 297
 298         /* UART3 specific */
 299         union {
 300                 /** Status FIFO register low (IrDA only) */
 301                 const ioport32_t sfregl;
 302 #define AMDM37x_UART_SFREGL_MASK   (0xff)
 303                 /** Received frame length low (IrDA only) */
 304                 ioport32_t rxfll;
 305 #define AMDM37x_UART_RXFLL_MASK   (0xff)
 306         };
 307
 308         /* UART3 specific */
 309         union {
 310                 /** Status FIFO register high (IrDA only) */
 311                 const ioport32_t sfregh;
 312 #define AMDM37x_UART_SFREGH_MASK   (0xf)
 313                 /** Received frame length high (IrDA only) */
 314                 ioport32_t rxflh;
 315 #define AMDM37x_UART_RXFLH_MASK   (0xf)
 316         };
 317
 318         union {
 319                 /** UART autobauding status register */
 320                 const ioport32_t uasr;
 321 #define AMDM37x_UART_UASR_SPEED_MASK   (0x1f)
 322 #define AMDM37x_UART_UASR_SPEED_SHIFT   (0)
 323 #define AMDM37x_UART_UASR_8BIT_CHAR_FLAG   (1 << 5)
 324 #define AMDM37x_UART_UASR_PARITY_MASK   (0x3)
 325 #define AMDM37x_UART_UASR_PARITY_SHIFT   (6)
 326
 327                 /** BOF control register (IrDA only) */
 328                 ioport32_t blr; /* UART3 specific */
 329 #define AMDM37x_IRDA_BLR_XBOF_TYPE_FLAG   (1 << 6)
 330 #define AMDM37x_IRDA_BLR_STS_FIFO_RESET   (1 << 7)
 331         };
 332
 333         /** Auxiliary control register (IrDA only) */
 334         ioport32_t acreg; /* UART3 specific */
 335 #define AMDM37x_IRDA_ACREG_EOT_EN_FLAG   (1 << 0)
 336 #define AMDM37x_IRDA_ACREG_ABORT_EN_FLAG   (1 << 1)
 337 #define AMDM37x_IRDA_ACREG_SCTX_EN_FLAG   (1 << 2)
 338 #define AMDM37x_IRDA_ACREG_SEND_SIP_FLAG   (1 << 3)
 339 #define AMDM37x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG   (1 << 4)
 340 #define AMDM37x_IRDA_ACREG_DIS_IR_RX_FLAG   (1 << 5)
 341 #define AMDM37x_IRDA_ACREG_SD_MOD_FLAG   (1 << 6)
 342 #define AMDM37x_IRDA_ACREG_PULSE_TYPE_FLAG   (1 << 7)
 343
 344         /** Supplementary control register */
 345         ioport32_t scr;
 346 #define AMDM37x_UART_SCR_DMA_MODE_CTL_FLAG   (1 << 0)
 347 #define AMDM37x_UART_SCR_DMA_MODE_MASK   (0x3)
 348 #define AMDM37x_UART_SCR_DMA_MODE_SHIFT   (1)
 349 #define AMDM37x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG   (1 << 3)
 350 #define AMDM37x_UART_SCR_RX_CTS_WU_EN_FLAG   (1 << 4)
 351 #define AMDM37x_UART_SCR_TX_TRIG_GRANU1_FLAG   (1 << 6)
 352 #define AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG   (1 << 7)
 353
 354         /** Supplementary status register */
 355         const ioport32_t ssr;
 356 #define AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG   (1 << 0)
 357 #define AMDM37x_UART_SSR_RX_CTS_WU_STS_FLAG   (1 << 1)
 358 #define AMDM37x_UART_SSR_DMA_COUNTER_RESET_FLAG   (1 << 2)
 359
 360         /** BOF Length register (IrDA only)*/
 361         ioport32_t eblr; /* UART3 specific */
 362 #define AMDM37x_IRDA_EBLR_DISABLED   (0x00)
 363 #define AMDM37x_IRDA_EBLR_RX_STOP_BITS(bits)   (bits & 0xff)
 364
 365         uint32_t padd0_;
 366
 367         /** Module version register */
 368         const ioport32_t mvr;
 369 #define AMDM37x_UART_MVR_MINOR_MASK   (0xf)
 370 #define AMDM37x_UART_MVR_MINOR_SHIFT   (0)
 371 #define AMDM37x_UART_MVR_MAJOR_MASK   (0xf)
 372 #define AMDM37x_UART_MVR_MAJOR_SHIFT   (4)
 373
 374         /** System configuration register */
 375         ioport32_t sysc;
 376 #define AMDM37x_UART_SYSC_AUTOIDLE_FLAG   (1 << 0)
 377 #define AMDM37x_UART_SYSC_SOFTRESET_FLAG   (1 << 1)
 378 #define AMDM37x_UART_SYSC_ENWAKEUP_FLAG   (1 << 2)
 379 #define AMDM37x_UART_SYSC_IDLE_MODE_MASK   (0x3)
 380 #define AMDM37x_UART_SYSC_IDLE_MODE_SHIFT   (3)
 381 #define AMDM37x_UART_SYSC_IDLE_MODE_FORCE   (0x0)
 382 #define AMDM37x_UART_SYSC_IDLE_MODE_NO   (0x1)
 383 #define AMDM37x_UART_SYSC_IDLE_MODE_SMART   (0x2)
 384
 385         /** System status register */
 386         const ioport32_t syss;
 387 #define AMDM37x_UART_SYSS_RESETDONE_FLAG   (1 << 0)
 388
 389         /** Wake-up enable register */
 390         ioport32_t wer;
 391 #define AMDM37x_UART_WER_CTS_ACTIVITY_FLAG  (1 << 0)
 392 #define AMDM37x_UART_WER_RI_ACTIVITY_FLAG  (1 << 2)
 393 #define AMDM37x_UART_WER_RX_ACTIVITY_FLAG  (1 << 4)
 394 #define AMDM37x_UART_WER_RHR_IRQ_FLAG  (1 << 5)
 395 #define AMDM37x_UART_WER_RLS_IRQ_FLAG  (1 << 6)
 396 #define AMDM37x_UART_WER_TX_WAKEUP_EN_FLAG  (1 << 7)
 397
 398         /** Carrier frequency prescaler */
 399         ioport32_t cfps;        /* UART3 specific */
 400 #define AMDM37x_UART_CFPS_MASK   (0xff)
 401
 402         /** Number of bytes in RX fifo */
 403         const ioport32_t rx_fifo_lvl;
 404 #define AMDM37x_UART_RX_FIFO_LVL_MASK   (0xff)
 405
 406         /** Number of bytes in TX fifo */
 407         const ioport32_t tx_fifo_lvl;
 408 #define AMDM37x_UART_TX_FIFO_LVL_MASK   (0xff)
 409
 410         /** RX/TX empty interrupts */
 411         ioport32_t ier2;
 412 #define AMDM37x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 0)
 413 #define AMDM37x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 1)
 414
 415         /** RX/TX empty status */
 416         ioport32_t isr2;
 417 #define AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG  (1 << 0)
 418 #define AMDM37x_UART_ISR2_TX_FIFO_EMPTY_FLAG  (1 << 1)
 419
 420         uint32_t padd2_[3];
 421
 422         /** Mode definition register 3 */
 423         ioport32_t mdr3;
 424 #define AMDM37x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG   (1 << 0)
 425 } amdm37x_uart_regs_t;
 426
 427 #endif
 428
 429 /**
 430  * @}
 431  */