kernel/arch/amd64/src/pm.c

   1 /*
   2  * Copyright (c) 2008 Jakub Jermar
   3  * Copyright (c) 2005-2006 Ondrej Palkovsky
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  *
  10  * - Redistributions of source code must retain the above copyright
  11  *   notice, this list of conditions and the following disclaimer.
  12  * - Redistributions in binary form must reproduce the above copyright
  13  *   notice, this list of conditions and the following disclaimer in the
  14  *   documentation and/or other materials provided with the distribution.
  15  * - The name of the author may not be used to endorse or promote products
  16  *   derived from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /** @addtogroup kernel_amd64
  31  * @{
  32  */
  33 /** @file
  34  */
  35
  36 #include <arch.h>
  37 #include <arch/pm.h>
  38 #include <arch/asm.h>
  39 #include <mm/as.h>
  40 #include <mm/frame.h>
  41 #include <memw.h>
  42 #include <stdlib.h>
  43
  44 /*
  45  * There is no segmentation in long mode so we set up flat mode. In this
  46  * mode, we use, for each privilege level, two segments spanning the
  47  * whole memory. One is for code and one is for data.
  48  */
  49
  50 descriptor_t gdt[GDT_ITEMS] = {
  51         [NULL_DES] = {
  52                 0
  53         },
  54         [KTEXT_DES] = {
  55                 .limit_0_15 = 0xffffU,
  56                 .limit_16_19 = 0xfU,
  57                 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
  58                 .longmode = 1,
  59                 .granularity = 1
  60         },
  61         [KDATA_DES] = {
  62                 .limit_0_15 = 0xffffU,
  63                 .limit_16_19 = 0xfU,
  64                 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
  65                 .granularity = 1
  66         },
  67         [UDATA_DES] = {
  68                 .limit_0_15 = 0xffffU,
  69                 .limit_16_19 = 0xfU,
  70                 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
  71                 .special = 1,
  72                 .granularity = 1
  73         },
  74         [UTEXT_DES] = {
  75                 .limit_0_15 = 0xffffU,
  76                 .limit_16_19 = 0xfU,
  77                 .access = AR_PRESENT | AR_CODE | DPL_USER,
  78                 .longmode = 1,
  79                 .granularity = 1
  80         },
  81         [KTEXT32_DES] = {
  82                 .limit_0_15 = 0xffffU,
  83                 .limit_16_19 = 0xfU,
  84                 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
  85                 .special = 1,
  86                 .granularity = 1
  87         },
  88         /*
  89          * TSS descriptor - set up will be completed later,
  90          * on AMD64 it is 64-bit - 2 items in the table
  91          */
  92         [TSS_DES] = {
  93                 0
  94         },
  95         [TSS_DES + 1] = {
  96                 0
  97         },
  98         /* VESA Init descriptor */
  99 #ifdef CONFIG_FB
 100         [VESA_INIT_CODE_DES] = {
 101                 .limit_0_15 = 0xffff,
 102                 .limit_16_19 = 0xf,
 103                 .base_16_23 = VESA_INIT_SEGMENT >> 12,
 104                 .access = AR_PRESENT | AR_CODE | AR_READABLE | DPL_KERNEL
 105         },
 106         [VESA_INIT_DATA_DES] = {
 107                 .limit_0_15 = 0xffff,
 108                 .limit_16_19 = 0xf,
 109                 .base_16_23 = VESA_INIT_SEGMENT >> 12,
 110                 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL
 111         }
 112 #endif
 113 };
 114
 115 idescriptor_t idt[IDT_ITEMS];
 116
 117 ptr_16_64_t gdtr = {
 118         .limit = sizeof(gdt),
 119         .base = (uint64_t) gdt
 120 };
 121 ptr_16_64_t idtr = {
 122         .limit = sizeof(idt),
 123         .base = (uint64_t) idt
 124 };
 125
 126 static tss_t tss;
 127 tss_t *tss_p = NULL;
 128
 129 void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
 130 {
 131         tss_descriptor_t *td = (tss_descriptor_t *) d;
 132
 133         td->base_0_15 = base & 0xffffU;
 134         td->base_16_23 = ((base) >> 16) & 0xffU;
 135         td->base_24_31 = ((base) >> 24) & 0xffU;
 136         td->base_32_63 = ((base) >> 32);
 137 }
 138
 139 void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
 140 {
 141         tss_descriptor_t *td = (tss_descriptor_t *) d;
 142
 143         td->limit_0_15 = limit & 0xffffU;
 144         td->limit_16_19 = (limit >> 16) & 0x0fU;
 145 }
 146
 147 void idt_setoffset(idescriptor_t *d, uintptr_t offset)
 148 {
 149         /*
 150          * Offset is a linear address.
 151          */
 152         d->offset_0_15 = offset & 0xffffU;
 153         d->offset_16_31 = (offset >> 16) & 0xffffU;
 154         d->offset_32_63 = offset >> 32;
 155 }
 156
 157 void tss_initialize(tss_t *t)
 158 {
 159         memsetb(t, sizeof(tss_t), 0);
 160 }
 161
 162 /*
 163  * This function takes care of proper setup of IDT and IDTR.
 164  */
 165 void idt_init(void)
 166 {
 167         idescriptor_t *d;
 168
 169         for (unsigned i = 0; i < IDT_ITEMS; i++) {
 170                 d = &idt[i];
 171
 172                 d->unused = 0;
 173                 d->selector = GDT_SELECTOR(KTEXT_DES);
 174
 175                 d->present = 1;
 176                 d->type = AR_INTERRUPT;  /* masking interrupt */
 177
 178                 d->dpl = PL_KERNEL;
 179                 d->ist = 0;
 180         }
 181
 182         d = &idt[0];
 183         idt_setoffset(d++, (uintptr_t) &int_0);
 184         idt_setoffset(d++, (uintptr_t) &int_1);
 185         idt_setoffset(d++, (uintptr_t) &int_2);
 186         idt_setoffset(d++, (uintptr_t) &int_3);
 187         idt_setoffset(d++, (uintptr_t) &int_4);
 188         idt_setoffset(d++, (uintptr_t) &int_5);
 189         idt_setoffset(d++, (uintptr_t) &int_6);
 190         idt_setoffset(d++, (uintptr_t) &int_7);
 191         idt_setoffset(d++, (uintptr_t) &int_8);
 192         idt_setoffset(d++, (uintptr_t) &int_9);
 193         idt_setoffset(d++, (uintptr_t) &int_10);
 194         idt_setoffset(d++, (uintptr_t) &int_11);
 195         idt_setoffset(d++, (uintptr_t) &int_12);
 196         idt_setoffset(d++, (uintptr_t) &int_13);
 197         idt_setoffset(d++, (uintptr_t) &int_14);
 198         idt_setoffset(d++, (uintptr_t) &int_15);
 199         idt_setoffset(d++, (uintptr_t) &int_16);
 200         idt_setoffset(d++, (uintptr_t) &int_17);
 201         idt_setoffset(d++, (uintptr_t) &int_18);
 202         idt_setoffset(d++, (uintptr_t) &int_19);
 203         idt_setoffset(d++, (uintptr_t) &int_20);
 204         idt_setoffset(d++, (uintptr_t) &int_21);
 205         idt_setoffset(d++, (uintptr_t) &int_22);
 206         idt_setoffset(d++, (uintptr_t) &int_23);
 207         idt_setoffset(d++, (uintptr_t) &int_24);
 208         idt_setoffset(d++, (uintptr_t) &int_25);
 209         idt_setoffset(d++, (uintptr_t) &int_26);
 210         idt_setoffset(d++, (uintptr_t) &int_27);
 211         idt_setoffset(d++, (uintptr_t) &int_28);
 212         idt_setoffset(d++, (uintptr_t) &int_29);
 213         idt_setoffset(d++, (uintptr_t) &int_30);
 214         idt_setoffset(d++, (uintptr_t) &int_31);
 215         idt_setoffset(d++, (uintptr_t) &int_32);
 216         idt_setoffset(d++, (uintptr_t) &int_33);
 217         idt_setoffset(d++, (uintptr_t) &int_34);
 218         idt_setoffset(d++, (uintptr_t) &int_35);
 219         idt_setoffset(d++, (uintptr_t) &int_36);
 220         idt_setoffset(d++, (uintptr_t) &int_37);
 221         idt_setoffset(d++, (uintptr_t) &int_38);
 222         idt_setoffset(d++, (uintptr_t) &int_39);
 223         idt_setoffset(d++, (uintptr_t) &int_40);
 224         idt_setoffset(d++, (uintptr_t) &int_41);
 225         idt_setoffset(d++, (uintptr_t) &int_42);
 226         idt_setoffset(d++, (uintptr_t) &int_43);
 227         idt_setoffset(d++, (uintptr_t) &int_44);
 228         idt_setoffset(d++, (uintptr_t) &int_45);
 229         idt_setoffset(d++, (uintptr_t) &int_46);
 230         idt_setoffset(d++, (uintptr_t) &int_47);
 231         idt_setoffset(d++, (uintptr_t) &int_48);
 232         idt_setoffset(d++, (uintptr_t) &int_49);
 233         idt_setoffset(d++, (uintptr_t) &int_50);
 234         idt_setoffset(d++, (uintptr_t) &int_51);
 235         idt_setoffset(d++, (uintptr_t) &int_52);
 236         idt_setoffset(d++, (uintptr_t) &int_53);
 237         idt_setoffset(d++, (uintptr_t) &int_54);
 238         idt_setoffset(d++, (uintptr_t) &int_55);
 239         idt_setoffset(d++, (uintptr_t) &int_56);
 240         idt_setoffset(d++, (uintptr_t) &int_57);
 241         idt_setoffset(d++, (uintptr_t) &int_58);
 242         idt_setoffset(d++, (uintptr_t) &int_59);
 243         idt_setoffset(d++, (uintptr_t) &int_60);
 244         idt_setoffset(d++, (uintptr_t) &int_61);
 245         idt_setoffset(d++, (uintptr_t) &int_62);
 246         idt_setoffset(d++, (uintptr_t) &int_63);
 247 }
 248
 249 /** Initialize segmentation - code/data/idt tables
 250  *
 251  */
 252 void pm_init(void)
 253 {
 254         descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
 255         tss_descriptor_t *tss_desc;
 256
 257         /*
 258          * Each CPU has its private GDT and TSS.
 259          * All CPUs share one IDT.
 260          */
 261
 262         if (config.cpu_active == 1) {
 263                 idt_init();
 264                 /*
 265                  * NOTE: bootstrap CPU has statically allocated TSS, because
 266                  * the heap hasn't been initialized so far.
 267                  */
 268                 tss_p = &tss;
 269         } else {
 270                 /*
 271                  * We are going to use malloc, which may return
 272                  * non boot-mapped pointer, initialize the CR3 register
 273                  * ahead of page_init
 274                  */
 275                 write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
 276
 277                 tss_p = (tss_t *) malloc(sizeof(tss_t));
 278                 if (!tss_p)
 279                         panic("Cannot allocate TSS.");
 280         }
 281
 282         tss_initialize(tss_p);
 283
 284         tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
 285         tss_desc->present = 1;
 286         tss_desc->type = AR_TSS;
 287         tss_desc->dpl = PL_KERNEL;
 288
 289         gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
 290         gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
 291
 292         gdtr_load(&gdtr);
 293         idtr_load(&idtr);
 294         /*
 295          * As of this moment, the current CPU has its own GDT pointing
 296          * to its own TSS. We just need to load the TR register.
 297          */
 298         tr_load(GDT_SELECTOR(TSS_DES));
 299 }
 300
 301 /** @}
 302  */