1 ## General configuration directives
5 @ "amd64" AMD64/Intel EM64T
8 @ "ppc32" PowerPC 32-bit
9 @ "ppc64" PowerPC 64-bit
10 @ "sparc64" Sun UltraSPARC
14 @ "cross" Cross-compiler
16 ! [ARCH=ia32] IA32_COMPILER (choice)
17 % [ARCH=ia32] SAVEAS IA32_COMPILER COMPILER
20 @ "cross" Cross-compiler
22 ! [ARCH=amd64] AMD64_COMPILER (choice)
23 % [ARCH=amd64] SAVEAS AMD64_COMPILER COMPILER
26 @ "cross" Cross-compiler
28 ! [(ARCH!=amd64)&(ARCH!=ia32)] OTHER_COMPILER (choice)
29 % [(ARCH!=amd64)&(ARCH!=ia32)] SAVEAS OTHER_COMPILER COMPILER
33 @ "pentium4" Pentium 4
34 @ "pentium3" Pentium 3
35 @ "athlon-xp" Athlon XP
36 @ "athlon-mp" Athlon MP
38 ! [ARCH=ia32] IA32_CPU (choice)
41 @ "msim" MSIM Simulator
42 @ "simics" Virtutech Simics simulator
43 @ "lgxemul" GXEmul Little Endian
44 @ "bgxemul" GXEmul Big Endian
46 ! [ARCH=mips32] MIPS_MACHINE (choice)
49 ! [(ARCH=mips32&MIPS_MACHINE=lgxemul)|(ARCH=mips32&MIPS_MACHINE=bgxemul)] CONFIG_FB (y/n)
52 ! [ARCH=ia32|ARCH=amd64] CONFIG_SMP (y/n)
54 # Improved support for hyperthreading
55 ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_HT (y/n)
57 # Simics BIOS AP boot fix
58 ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_SIMICS_FIX (y/n)
60 # Lazy FPU context switching
61 ! [(ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics)|ARCH=amd64|ARCH=ia32|ARCH=ia64] CONFIG_FPU_LAZY (y/n)
64 ! [ARCH=ppc32] CONFIG_POWEROFF (y/n)
66 ## Debugging configuration directives
68 # General debuging and assert checking
71 # Deadlock detection support for spinlocks
72 ! [CONFIG_DEBUG=y&CONFIG_SMP=y] CONFIG_DEBUG_SPINLOCK (y/n)
74 # Watchpoint on rewriting AS with zero
75 ! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=ia32)] CONFIG_DEBUG_AS_WATCHPOINT (y/n)
77 # Save all interrupt registers
78 ! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=mips32|ARCH=ia32)] CONFIG_DEBUG_ALLREGS (y/n)
80 ## Run-time configuration directives
84 @ "atomic/atomic1" Test of atomic operations.
85 @ "btree/btree1" B-tree test.
86 @ "synch/rwlock1" Read write test 1
87 @ "synch/rwlock2" Read write test 2
88 @ "synch/rwlock3" Read write test 3
89 @ "synch/rwlock4" Read write test 4
90 @ "synch/rwlock5" Read write test 5
91 @ "synch/semaphore1" Semaphore test 1
92 @ "synch/semaphore2" Sempahore test 2
93 @ [ARCH=ia32|ARCH=amd64|ARCH=ia64] "fpu/fpu1" Intel fpu test 1
94 @ [ARCH=ia32|ARCH=amd64] "fpu/sse1" Intel Sse test 1
95 @ [ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics] "fpu/mips1" Mips FPU test 1
96 @ "print/print1" Printf test 1
97 @ "thread/thread1" Thread test 1
98 @ "mm/mapping1" Mapping test 1
99 @ "mm/falloc1" Frame Allocation test 1
100 @ "mm/falloc2" Frame Allocation test 2
101 @ "mm/slab1" SLAB test1 - No CPU-cache
102 @ "mm/slab2" SLAB test2 - SMP CPU cache
103 @ "fault/fault1" Write to NULL (maybe page fault)
104 @ [ARCH=ia64] "mm/purge1" Itanium TLB purge test
105 @ [ARCH=mips32] "debug/mips1" Mips breakpoint-debug test
106 ! CONFIG_TEST (choice)