Fix cases of undefined behavior found by ubsan.
[helenos.git] / uspace / drv / bus / usb / xhci / endpoint.c
blob3f8d34d12a4cc1db37ff4b65e106af01ebb58950
1 /*
2 * Copyright (c) 2018 Petr Manek, Ondrej Hlavaty, Michal Staruch, Jan Hrach
3 * All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 /** @addtogroup drvusbxhci
30 * @{
32 /** @file
33 * @brief The host controller endpoint management.
36 #include <usb/host/endpoint.h>
37 #include <usb/descriptor.h>
39 #include <errno.h>
40 #include <macros.h>
41 #include <str_error.h>
43 #include "hc.h"
44 #include "bus.h"
45 #include "commands.h"
46 #include "device.h"
47 #include "endpoint.h"
48 #include "streams.h"
50 static errno_t alloc_transfer_ds(xhci_endpoint_t *);
52 /**
53 * Initialize new XHCI endpoint.
54 * @param[in] xhci_ep Allocated XHCI endpoint to initialize.
55 * @param[in] dev Device, to which the endpoint belongs.
56 * @param[in] desc USB endpoint descriptor carrying configuration data.
58 * @return Error code.
60 static errno_t xhci_endpoint_init(xhci_endpoint_t *xhci_ep, device_t *dev,
61 const usb_endpoint_descriptors_t *desc)
63 errno_t rc;
64 assert(xhci_ep);
66 endpoint_t *ep = &xhci_ep->base;
68 endpoint_init(ep, dev, desc);
70 fibril_mutex_initialize(&xhci_ep->guard);
72 xhci_ep->max_burst = desc->companion.max_burst + 1;
74 if (ep->transfer_type == USB_TRANSFER_BULK)
75 xhci_ep->max_streams = 1 << (USB_SSC_MAX_STREAMS(desc->companion));
76 else
77 xhci_ep->max_streams = 1;
79 if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS)
80 xhci_ep->mult = USB_SSC_MULT(desc->companion) + 1;
81 else
82 xhci_ep->mult = 1;
85 * In USB 3, the semantics of wMaxPacketSize changed. Now the number of
86 * packets per service interval is determined from max_burst and mult.
88 if (dev->speed >= USB_SPEED_SUPER) {
89 ep->packets_per_uframe = xhci_ep->max_burst * xhci_ep->mult;
90 if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS ||
91 ep->transfer_type == USB_TRANSFER_INTERRUPT) {
92 ep->max_transfer_size = ep->max_packet_size * ep->packets_per_uframe;
96 xhci_ep->interval = desc->endpoint.poll_interval;
99 * Only Low/Full speed interrupt endpoints have interval as a linear field,
100 * others have 2-based log of it.
102 if (dev->speed >= USB_SPEED_HIGH ||
103 ep->transfer_type != USB_TRANSFER_INTERRUPT) {
105 if (xhci_ep->interval > 0)
106 xhci_ep->interval = 1 << (xhci_ep->interval - 1);
109 /* Full speed devices have interval in frames */
110 if (dev->speed <= USB_SPEED_FULL) {
111 xhci_ep->interval *= 8;
114 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS)
115 isoch_init(xhci_ep, desc);
117 if ((rc = alloc_transfer_ds(xhci_ep)))
118 goto err;
120 unsigned flags = -1U;
122 /* Some xHCs can handle 64-bit addresses */
123 xhci_bus_t *bus = bus_to_xhci_bus(ep->device->bus);
124 if (bus->hc->ac64)
125 flags &= ~DMA_POLICY_4GiB;
127 /* xHCI works best if it can fit 65k transfers in one TRB */
128 ep->transfer_buffer_policy = dma_policy_create(flags, 1 << 16);
130 /* But actualy can do full scatter-gather. */
131 ep->required_transfer_buffer_policy = dma_policy_create(flags, PAGE_SIZE);
133 return EOK;
135 err:
136 return rc;
140 * Create a new xHCI endpoint structure.
142 * Bus callback.
144 endpoint_t *xhci_endpoint_create(device_t *dev,
145 const usb_endpoint_descriptors_t *desc)
147 const usb_transfer_type_t type = USB_ED_GET_TRANSFER_TYPE(desc->endpoint);
149 xhci_endpoint_t *ep = calloc(1, sizeof(xhci_endpoint_t) +
150 (type == USB_TRANSFER_ISOCHRONOUS) * sizeof(*ep->isoch));
151 if (!ep)
152 return NULL;
154 if (xhci_endpoint_init(ep, dev, desc)) {
155 free(ep);
156 return NULL;
159 return &ep->base;
163 * Finalize XHCI endpoint.
164 * @param[in] xhci_ep XHCI endpoint to finalize.
166 static void xhci_endpoint_fini(xhci_endpoint_t *xhci_ep)
168 assert(xhci_ep);
170 xhci_endpoint_free_transfer_ds(xhci_ep);
172 // TODO: Something missed?
176 * Destroy given xHCI endpoint structure.
178 * Bus callback.
180 void xhci_endpoint_destroy(endpoint_t *ep)
182 xhci_endpoint_t *xhci_ep = xhci_endpoint_get(ep);
184 xhci_endpoint_fini(xhci_ep);
185 free(xhci_ep);
190 * Register an andpoint to the xHC.
192 * Bus callback.
194 errno_t xhci_endpoint_register(endpoint_t *ep_base)
196 errno_t err;
197 xhci_endpoint_t *ep = xhci_endpoint_get(ep_base);
199 if (ep_base->endpoint != 0 && (err = hc_add_endpoint(ep)))
200 return err;
202 endpoint_set_online(ep_base, &ep->guard);
203 return EOK;
207 * Abort a transfer on an endpoint.
209 static void endpoint_abort(endpoint_t *ep)
211 xhci_device_t *dev = xhci_device_get(ep->device);
212 xhci_endpoint_t *xhci_ep = xhci_endpoint_get(ep);
214 /* This function can only abort endpoints without streams. */
215 assert(xhci_ep->primary_stream_data_array == NULL);
217 fibril_mutex_lock(&xhci_ep->guard);
219 endpoint_set_offline_locked(ep);
221 if (!ep->active_batch) {
222 fibril_mutex_unlock(&xhci_ep->guard);
223 return;
226 /* First, offer the batch a short chance to be finished. */
227 endpoint_wait_timeout_locked(ep, 10000);
229 if (!ep->active_batch) {
230 fibril_mutex_unlock(&xhci_ep->guard);
231 return;
234 usb_transfer_batch_t *const batch = ep->active_batch;
236 const errno_t err = hc_stop_endpoint(xhci_ep);
237 if (err) {
238 usb_log_error("Failed to stop endpoint %u of device "
239 XHCI_DEV_FMT ": %s", ep->endpoint, XHCI_DEV_ARGS(*dev),
240 str_error(err));
243 fibril_mutex_unlock(&xhci_ep->guard);
245 batch->error = EINTR;
246 batch->transferred_size = 0;
247 usb_transfer_batch_finish(batch);
248 return;
252 * Unregister an endpoint. If the device is still available, inform the xHC
253 * about it.
255 * Bus callback.
257 void xhci_endpoint_unregister(endpoint_t *ep_base)
259 errno_t err;
260 xhci_endpoint_t *ep = xhci_endpoint_get(ep_base);
261 xhci_device_t *dev = xhci_device_get(ep_base->device);
263 endpoint_abort(ep_base);
265 /* If device slot is still available, drop the endpoint. */
266 if (ep_base->endpoint != 0 && dev->slot_id) {
268 if ((err = hc_drop_endpoint(ep))) {
269 usb_log_error("Failed to drop endpoint " XHCI_EP_FMT ": %s",
270 XHCI_EP_ARGS(*ep), str_error(err));
272 } else {
273 usb_log_debug("Not going to drop endpoint " XHCI_EP_FMT " because"
274 " the slot has already been disabled.", XHCI_EP_ARGS(*ep));
279 * Determine the type of a XHCI endpoint.
280 * @param[in] ep XHCI endpoint to query.
282 * @return EP_TYPE_[CONTROL|ISOCH|BULK|INTERRUPT]_[IN|OUT]
284 int xhci_endpoint_type(xhci_endpoint_t *ep)
286 const bool in = ep->base.direction == USB_DIRECTION_IN;
288 switch (ep->base.transfer_type) {
289 case USB_TRANSFER_CONTROL:
290 return EP_TYPE_CONTROL;
292 case USB_TRANSFER_ISOCHRONOUS:
293 return in ? EP_TYPE_ISOCH_IN :
294 EP_TYPE_ISOCH_OUT;
296 case USB_TRANSFER_BULK:
297 return in ? EP_TYPE_BULK_IN :
298 EP_TYPE_BULK_OUT;
300 case USB_TRANSFER_INTERRUPT:
301 return in ? EP_TYPE_INTERRUPT_IN :
302 EP_TYPE_INTERRUPT_OUT;
305 return EP_TYPE_INVALID;
309 * Allocate transfer data structures for XHCI endpoint not using streams.
310 * @param[in] xhci_ep XHCI endpoint to allocate data structures for.
312 * @return Error code.
314 static errno_t alloc_transfer_ds(xhci_endpoint_t *xhci_ep)
316 /* Can't use XHCI_EP_FMT because the endpoint may not have device. */
317 usb_log_debug("Allocating main transfer ring for endpoint " XHCI_EP_FMT,
318 XHCI_EP_ARGS(*xhci_ep));
320 xhci_ep->primary_stream_data_array = NULL;
321 xhci_ep->primary_stream_data_size = 0;
323 errno_t err;
324 if ((err = xhci_trb_ring_init(&xhci_ep->ring, 0))) {
325 return err;
328 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
329 if ((err = isoch_alloc_transfers(xhci_ep))) {
330 xhci_trb_ring_fini(&xhci_ep->ring);
331 return err;
335 return EOK;
339 * Free transfer data structures for XHCI endpoint.
340 * @param[in] xhci_ep XHCI endpoint to free data structures for.
342 void xhci_endpoint_free_transfer_ds(xhci_endpoint_t *xhci_ep)
344 if (xhci_ep->primary_stream_data_size) {
345 xhci_stream_free_ds(xhci_ep);
346 } else {
347 usb_log_debug("Freeing main transfer ring of endpoint " XHCI_EP_FMT,
348 XHCI_EP_ARGS(*xhci_ep));
349 xhci_trb_ring_fini(&xhci_ep->ring);
352 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS)
353 isoch_fini(xhci_ep);
356 xhci_trb_ring_t *xhci_endpoint_get_ring(xhci_endpoint_t *ep, uint32_t stream_id)
358 if (ep->primary_stream_data_size == 0)
359 return stream_id == 0 ? &ep->ring : NULL;
361 xhci_stream_data_t *stream_data = xhci_get_stream_ctx_data(ep, stream_id);
362 if (stream_data == NULL) {
363 usb_log_warning("No transfer ring was found for stream %u.", stream_id);
364 return NULL;
367 return &stream_data->ring;
371 * Configure endpoint context of a control endpoint.
372 * @param[in] ep XHCI control endpoint.
373 * @param[in] ctx Endpoint context to configure.
375 static void setup_control_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
377 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
378 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
379 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
380 XHCI_EP_MULT_SET(*ctx, ep->mult - 1);
381 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
382 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
383 XHCI_EP_DCS_SET(*ctx, 1);
387 * Configure endpoint context of a bulk endpoint.
388 * @param[in] ep XHCI bulk endpoint.
389 * @param[in] ctx Endpoint context to configure.
391 static void setup_bulk_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
393 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
394 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
395 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
396 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
398 XHCI_EP_MAX_P_STREAMS_SET(*ctx, 0);
399 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
400 XHCI_EP_DCS_SET(*ctx, 1);
404 * Configure endpoint context of a isochronous endpoint.
405 * @param[in] ep XHCI isochronous endpoint.
406 * @param[in] ctx Endpoint context to configure.
408 static void setup_isoch_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
410 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
411 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
412 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
413 XHCI_EP_MULT_SET(*ctx, ep->mult - 1);
414 XHCI_EP_ERROR_COUNT_SET(*ctx, 0);
415 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
416 XHCI_EP_DCS_SET(*ctx, 1);
417 XHCI_EP_INTERVAL_SET(*ctx, fnzb32(ep->interval) % 32);
419 XHCI_EP_MAX_ESIT_PAYLOAD_LO_SET(*ctx, ep->isoch->max_size & 0xFFFF);
420 XHCI_EP_MAX_ESIT_PAYLOAD_HI_SET(*ctx, (ep->isoch->max_size >> 16) & 0xFF);
424 * Configure endpoint context of a interrupt endpoint.
425 * @param[in] ep XHCI interrupt endpoint.
426 * @param[in] ctx Endpoint context to configure.
428 static void setup_interrupt_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
430 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
431 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
432 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
433 XHCI_EP_MULT_SET(*ctx, 0);
434 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
435 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
436 XHCI_EP_DCS_SET(*ctx, 1);
437 XHCI_EP_INTERVAL_SET(*ctx, fnzb32(ep->interval) % 32);
438 // TODO: max ESIT payload
441 /** Type of endpoint context configuration function. */
442 typedef void (*setup_ep_ctx_helper)(xhci_endpoint_t *, xhci_ep_ctx_t *);
445 * Static array, which maps USB endpoint types to their respective endpoint
446 * context configuration functions.
448 static const setup_ep_ctx_helper setup_ep_ctx_helpers[] = {
449 [USB_TRANSFER_CONTROL] = setup_control_ep_ctx,
450 [USB_TRANSFER_ISOCHRONOUS] = setup_isoch_ep_ctx,
451 [USB_TRANSFER_BULK] = setup_bulk_ep_ctx,
452 [USB_TRANSFER_INTERRUPT] = setup_interrupt_ep_ctx,
455 /** Configure endpoint context of XHCI endpoint.
456 * @param[in] ep Associated XHCI endpoint.
457 * @param[in] ep_ctx Endpoint context to configure.
459 void xhci_setup_endpoint_context(xhci_endpoint_t *ep, xhci_ep_ctx_t *ep_ctx)
461 assert(ep);
462 assert(ep_ctx);
464 usb_transfer_type_t tt = ep->base.transfer_type;
466 memset(ep_ctx, 0, sizeof(*ep_ctx));
467 setup_ep_ctx_helpers[tt](ep, ep_ctx);
471 * Clear endpoint halt condition by resetting the endpoint and skipping the
472 * offending transfer.
474 errno_t xhci_endpoint_clear_halt(xhci_endpoint_t *ep, uint32_t stream_id)
476 errno_t err;
478 if ((err = hc_reset_endpoint(ep)))
479 return err;
481 if ((err = hc_reset_ring(ep, stream_id)))
482 return err;
484 return EOK;
488 * @}