kernel/arch/sparc64/src/mm/tsb.c

   1 /*
   2  * Copyright (C) 2006 Jakub Jermar
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * - Redistributions of source code must retain the above copyright
  10  *   notice, this list of conditions and the following disclaimer.
  11  * - Redistributions in binary form must reproduce the above copyright
  12  *   notice, this list of conditions and the following disclaimer in the
  13  *   documentation and/or other materials provided with the distribution.
  14  * - The name of the author may not be used to endorse or promote products
  15  *   derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @addtogroup sparc64mm
  30  * @{
  31  */
  32 /** @file
  33  */
  34
  35 #include <arch/mm/tsb.h>
  36 #include <arch/mm/tlb.h>
  37 #include <arch/barrier.h>
  38 #include <mm/as.h>
  39 #include <arch/types.h>
  40 #include <typedefs.h>
  41 #include <macros.h>
  42 #include <debug.h>
  43
  44 #define TSB_INDEX_MASK          ((1 << (21 + 1 + TSB_SIZE - PAGE_WIDTH)) - 1)
  45
  46 /** Invalidate portion of TSB.
  47  *
  48  * We assume that the address space is already locked. Note that respective
  49  * portions of both TSBs are invalidated at a time.
  50  *
  51  * @param as Address space.
  52  * @param page First page to invalidate in TSB.
  53  * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
  54  *      whole TSB.
  55  */
  56 void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
  57 {
  58         index_t i0, i;
  59         count_t cnt;
  60
  61         ASSERT(as->arch.itsb && as->arch.dtsb);
  62
  63         i0 = (page >> PAGE_WIDTH) & TSB_INDEX_MASK;
  64         cnt = min(pages, ITSB_ENTRY_COUNT);
  65
  66         for (i = 0; i < cnt; i++) {
  67                 as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
  68                         true;
  69                 as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
  70                         true;
  71         }
  72 }
  73
  74 /** Copy software PTE to ITSB.
  75  *
  76  * @param t Software PTE.
  77  */
  78 void itsb_pte_copy(pte_t *t)
  79 {
  80         as_t *as;
  81         tsb_entry_t *tsb;
  82
  83         as = t->as;
  84         tsb = &as->arch.itsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK];
  85
  86         /*
  87          * We use write barriers to make sure that the TSB load
  88          * won't use inconsistent data or that the fault will
  89          * be repeated.
  90          */
  91
  92         tsb->tag.invalid = true;        /* invalidate the entry
  93                                          * (tag target has this
  94                                          * set to 0) */
  95
  96         write_barrier();
  97
  98         tsb->tag.context = as->asid;
  99         tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
 100         tsb->data.value = 0;
 101         tsb->data.size = PAGESIZE_8K;
 102         tsb->data.pfn = t->frame >> FRAME_WIDTH;
 103         tsb->data.cp = t->c;
 104         tsb->data.p = t->k;             /* p as privileged */
 105         tsb->data.v = t->p;
 106
 107         write_barrier();
 108
 109         tsb->tag.invalid = false;       /* mark the entry as valid */
 110 }
 111
 112 /** Copy software PTE to DTSB.
 113  *
 114  * @param t Software PTE.
 115  * @param ro If true, the mapping is copied read-only.
 116  */
 117 void dtsb_pte_copy(pte_t *t, bool ro)
 118 {
 119         as_t *as;
 120         tsb_entry_t *tsb;
 121
 122         as = t->as;
 123         tsb = &as->arch.dtsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK];
 124
 125         /*
 126          * We use write barriers to make sure that the TSB load
 127          * won't use inconsistent data or that the fault will
 128          * be repeated.
 129          */
 130
 131         tsb->tag.invalid = true;        /* invalidate the entry
 132                                          * (tag target has this
 133                                          * set to 0) */
 134
 135         write_barrier();
 136
 137         tsb->tag.context = as->asid;
 138         tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
 139         tsb->data.value = 0;
 140         tsb->data.size = PAGESIZE_8K;
 141         tsb->data.pfn = t->frame >> FRAME_WIDTH;
 142         tsb->data.cp = t->c;
 143 #ifdef CONFIG_VIRT_IDX_DCACHE
 144         tsb->data.cv = t->c;
 145 #endif /* CONFIG_VIRT_IDX_DCACHE */
 146         tsb->data.p = t->k;             /* p as privileged */
 147         tsb->data.w = ro ? false : t->w;
 148         tsb->data.v = t->p;
 149
 150         write_barrier();
 151
 152         tsb->tag.invalid = true;        /* mark the entry as valid */
 153 }
 154
 155 /** @}
 156  */