kernel/arch/sparc64/src/mm/tsb.c

   1 /*
   2  * Copyright (C) 2006 Jakub Jermar
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * - Redistributions of source code must retain the above copyright
  10  *   notice, this list of conditions and the following disclaimer.
  11  * - Redistributions in binary form must reproduce the above copyright
  12  *   notice, this list of conditions and the following disclaimer in the
  13  *   documentation and/or other materials provided with the distribution.
  14  * - The name of the author may not be used to endorse or promote products
  15  *   derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @addtogroup sparc64mm
  30  * @{
  31  */
  32 /** @file
  33  */
  34
  35 #include <arch/mm/tsb.h>
  36 #include <arch/mm/tlb.h>
  37 #include <arch/barrier.h>
  38 #include <mm/as.h>
  39 #include <arch/types.h>
  40 #include <typedefs.h>
  41 #include <macros.h>
  42 #include <debug.h>
  43
  44 #define TSB_INDEX_MASK          ((1<<(21+1+TSB_SIZE-PAGE_WIDTH))-1)
  45
  46 /** Invalidate portion of TSB.
  47  *
  48  * We assume that the address space is already locked.
  49  * Note that respective portions of both TSBs
  50  * are invalidated at a time.
  51  *
  52  * @param as Address space.
  53  * @param page First page to invalidate in TSB.
  54  * @param pages Number of pages to invalidate.
  55  *              Value of (count_t) -1 means the whole TSB.
  56  */
  57 void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
  58 {
  59         index_t i0, i;
  60         count_t cnt;
  61
  62         ASSERT(as->arch.itsb && as->arch.dtsb);
  63
  64         i0 = (page >> PAGE_WIDTH) & TSB_INDEX_MASK;
  65         cnt = min(pages, ITSB_ENTRY_COUNT);
  66
  67         for (i = 0; i < cnt; i++) {
  68                 as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT-1)].tag.invalid = true;
  69                 as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT-1)].tag.invalid = true;
  70         }
  71 }
  72
  73 /** Copy software PTE to ITSB.
  74  *
  75  * @param t Software PTE.
  76  */
  77 void itsb_pte_copy(pte_t *t)
  78 {
  79         as_t *as;
  80         tsb_entry_t *tsb;
  81
  82         as = t->as;
  83         tsb = &as->arch.itsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK];
  84
  85         /*
  86          * We use write barriers to make sure that the TSB load
  87          * won't use inconsistent data or that the fault will
  88          * be repeated.
  89          */
  90
  91         tsb->tag.invalid = true;        /* invalidate the entry
  92                                          * (tag target has this
  93                                          * set to 0) */
  94
  95         write_barrier();
  96
  97         tsb->tag.context = as->asid;
  98         tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
  99         tsb->data.value = 0;
 100         tsb->data.size = PAGESIZE_8K;
 101         tsb->data.pfn = t->frame >> FRAME_WIDTH;
 102         tsb->data.cp = t->c;
 103 #ifdef CONFIG_VIRT_IDX_CACHE
 104         tsb->data.cv = t->c;
 105 #endif /* CONFIG_VIRT_IDX_CACHE */
 106         tsb->data.p = t->k;             /* p as privileged */
 107         tsb->data.v = t->p;
 108
 109         write_barrier();
 110
 111         tsb->tag.invalid = false;       /* mark the entry as valid */
 112 }
 113
 114 /** Copy software PTE to DTSB.
 115  *
 116  * @param t Software PTE.
 117  * @param ro If true, the mapping is copied read-only.
 118  */
 119 void dtsb_pte_copy(pte_t *t, bool ro)
 120 {
 121         as_t *as;
 122         tsb_entry_t *tsb;
 123
 124         as = t->as;
 125         tsb = &as->arch.dtsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK];
 126
 127         /*
 128          * We use write barriers to make sure that the TSB load
 129          * won't use inconsistent data or that the fault will
 130          * be repeated.
 131          */
 132
 133         tsb->tag.invalid = true;        /* invalidate the entry
 134                                          * (tag target has this
 135                                          * set to 0) */
 136
 137         write_barrier();
 138
 139         tsb->tag.context = as->asid;
 140         tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
 141         tsb->data.value = 0;
 142         tsb->data.size = PAGESIZE_8K;
 143         tsb->data.pfn = t->frame >> FRAME_WIDTH;
 144         tsb->data.cp = t->c;
 145 #ifdef CONFIG_VIRT_IDX_CACHE
 146         tsb->data.cv = t->c;
 147 #endif /* CONFIG_VIRT_IDX_CACHE */
 148         tsb->data.p = t->k;             /* p as privileged */
 149         tsb->data.w = ro ? false : t->w;
 150         tsb->data.v = t->p;
 151
 152         write_barrier();
 153
 154         tsb->tag.invalid = true;        /* mark the entry as valid */
 155 }
 156
 157 /** @}
 158  */