gnu/packages/patches/ath9k-htc-firmware-gcc.patch

   1 This GCC patch is from the ath9k-htc-firmware repository (version 1.3.2).
   2 Not applying it (apparently) leads to miscompiled firmware, and loading it
   3 fails with a "Target is unresponsive" message from the 'ath9k_htc' module.
   4
   5 From c7162b8a3db42e7faf47606d3aa3dd61e64aea17 Mon Sep 17 00:00:00 2001
   6 From: Sujith Manoharan <c_manoha@qca.qualcomm.com>
   7 Date: Mon, 7 Jan 2013 16:06:28 +0530
   8 Subject: [PATCH] gcc: AR9271/AR7010 config
   9
  10 Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
  11 ---
  12  include/xtensa-config.h | 36 +++++++++++++++++-------------------
  13  1 file changed, 17 insertions(+), 19 deletions(-)
  14
  15 diff --git a/include/xtensa-config.h b/include/xtensa-config.h
  16 index 30f4f41..fe9b051 100644
  17 --- a/include/xtensa-config.h
  18 +++ b/include/xtensa-config.h
  19 @@ -44,10 +44,7 @@
  20  #define XCHAL_HAVE_L32R                        1
  21
  22  #undef XSHAL_USE_ABSOLUTE_LITERALS
  23 -#define XSHAL_USE_ABSOLUTE_LITERALS    0
  24 -
  25 -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
  26 -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
  27 +#define XSHAL_USE_ABSOLUTE_LITERALS    1
  28
  29  #undef XCHAL_HAVE_MAC16
  30  #define XCHAL_HAVE_MAC16               0
  31 @@ -59,10 +56,10 @@
  32  #define XCHAL_HAVE_MUL32               1
  33
  34  #undef XCHAL_HAVE_MUL32_HIGH
  35 -#define XCHAL_HAVE_MUL32_HIGH          0
  36 +#define XCHAL_HAVE_MUL32_HIGH          1
  37
  38  #undef XCHAL_HAVE_DIV32
  39 -#define XCHAL_HAVE_DIV32               1
  40 +#define XCHAL_HAVE_DIV32               0
  41
  42  #undef XCHAL_HAVE_NSA
  43  #define XCHAL_HAVE_NSA                 1
  44 @@ -103,8 +100,6 @@
  45  #undef XCHAL_HAVE_FP_RSQRT
  46  #define XCHAL_HAVE_FP_RSQRT            0
  47
  48 -#undef XCHAL_HAVE_DFP_accel
  49 -#define XCHAL_HAVE_DFP_accel                   0
  50  #undef XCHAL_HAVE_WINDOWED
  51  #define XCHAL_HAVE_WINDOWED            1
  52
  53 @@ -119,32 +114,32 @@
  54
  55
  56  #undef XCHAL_ICACHE_SIZE
  57 -#define XCHAL_ICACHE_SIZE              16384
  58 +#define XCHAL_ICACHE_SIZE              0
  59
  60  #undef XCHAL_DCACHE_SIZE
  61 -#define XCHAL_DCACHE_SIZE              16384
  62 +#define XCHAL_DCACHE_SIZE              0
  63
  64  #undef XCHAL_ICACHE_LINESIZE
  65 -#define XCHAL_ICACHE_LINESIZE          32
  66 +#define XCHAL_ICACHE_LINESIZE          16
  67
  68  #undef XCHAL_DCACHE_LINESIZE
  69 -#define XCHAL_DCACHE_LINESIZE          32
  70 +#define XCHAL_DCACHE_LINESIZE          16
  71
  72  #undef XCHAL_ICACHE_LINEWIDTH
  73 -#define XCHAL_ICACHE_LINEWIDTH         5
  74 +#define XCHAL_ICACHE_LINEWIDTH         4
  75
  76  #undef XCHAL_DCACHE_LINEWIDTH
  77 -#define XCHAL_DCACHE_LINEWIDTH         5
  78 +#define XCHAL_DCACHE_LINEWIDTH         4
  79
  80  #undef XCHAL_DCACHE_IS_WRITEBACK
  81 -#define XCHAL_DCACHE_IS_WRITEBACK      1
  82 +#define XCHAL_DCACHE_IS_WRITEBACK      0
  83
  84
  85  #undef XCHAL_HAVE_MMU
  86  #define XCHAL_HAVE_MMU                 1
  87
  88  #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
  89 -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE    12
  90 +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE    29
  91
  92
  93  #undef XCHAL_HAVE_DEBUG
  94 @@ -157,8 +152,11 @@
  95  #define XCHAL_NUM_DBREAK               2
  96
  97  #undef XCHAL_DEBUGLEVEL
  98 -#define XCHAL_DEBUGLEVEL               6
  99 +#define XCHAL_DEBUGLEVEL               4
 100 +
 101
 102 +#undef XCHAL_EXCM_LEVEL
 103 +#define XCHAL_EXCM_LEVEL                3
 104
 105  #undef XCHAL_MAX_INSTRUCTION_SIZE
 106  #define XCHAL_MAX_INSTRUCTION_SIZE     3
 107 --
 108 1.8.1
 109