src/gromacs/ewald/pme_gpu_constants.h

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  35 /*! \internal \file
  36  * \brief This file defines the PME GPU compile-time constants/macros,
  37  * used both in device and host code.
  38  *
  39  * As OpenCL C is not aware of constexpr, most of this file is
  40  * forwarded to the OpenCL kernel compilation as defines with same
  41  * names, for the sake of code similarity.
  42  *
  43  * \todo The values are currently common to both CUDA and OpenCL
  44  * implementations, but should be reconsidered when we tune the OpenCL
  45  * implementation. See Redmine #2528.
  46  *
  47  * \author Aleksei Iupinov <a.yupinov@gmail.com>
  48  * \ingroup module_ewald
  49  */
  50
  51 #ifndef GMX_EWALD_PME_GPU_CONSTANTS_H
  52 #define GMX_EWALD_PME_GPU_CONSTANTS_H
  53
  54 #include "config.h"
  55
  56 #if GMX_GPU == GMX_GPU_CUDA
  57 #include "gromacs/gpu_utils/cuda_arch_utils.cuh" // for warp_size
  58 #endif
  59
  60 /* General settings for PME GPU behaviour */
  61
  62 /*! \brief
  63  * false: The atom data GPU buffers are sized precisely according to the number of atoms.
  64  *        (Except GPU spline data layout which is regardless intertwined for 2 atoms per warp).
  65  *        The atom index checks in the spread/gather code potentially hinder the performance.
  66  * true:  The atom data GPU buffers are padded with zeroes so that the possible number of atoms
  67  *        fitting in is divisible by c_pmeAtomDataAlignment.
  68  *        The atom index checks are not performed. There should be a performance win, but how big is it, remains to be seen.
  69  *        Additional cudaMemsetAsync calls are done occasionally (only charges/coordinates; spline data is always recalculated now).
  70  * \todo Estimate performance differences
  71  */
  72 constexpr bool c_usePadding = true;
  73
  74 /*! \brief
  75  * false: Atoms with zero charges are processed by PME. Could introduce some overhead.
  76  * true:  Atoms with zero charges are not processed by PME. Adds branching to the spread/gather.
  77  *        Could be good for performance in specific systems with lots of neutral atoms.
  78  * \todo Estimate performance differences.
  79  */
  80 constexpr bool c_skipNeutralAtoms = false;
  81
  82 /*! \brief
  83  * Number of PME solve output floating point numbers.
  84  * 6 for symmetric virial matrix + 1 for reciprocal energy.
  85  */
  86 constexpr int c_virialAndEnergyCount = 7;
  87
  88
  89 /* Macros concerning the data layout */
  90
  91 /*
  92     Here is a current memory layout for the theta/dtheta B-spline float parameter arrays.
  93     This is the data in global memory used both by spreading and gathering kernels (with same scheduling).
  94     This example has PME order 4 and 2 particles per warp/data chunk.
  95     Each particle has 16 threads assigned to it, each thread works on 4 non-sequential global grid contributions.
  96
  97     ----------------------------------------------------------------------------
  98     particles 0, 1                                        | particles 2, 3     | ...
  99     ----------------------------------------------------------------------------
 100     order index 0           | index 1 | index 2 | index 3 | order index 0 .....
 101     ----------------------------------------------------------------------------
 102     tx0 tx1 ty0 ty1 tz0 tz1 | ..........
 103     ----------------------------------------------------------------------------
 104
 105     Each data chunk for a single warp is 24 floats. This goes both for theta and dtheta.
 106     24 = 2 particles per warp * order 4 * 3 dimensions. 48 floats (1.5 warp size) per warp in total.
 107     I have also tried intertwining theta and theta in a single array (they are used in pairs in gathering stage anyway)
 108     and it didn't seem to make a performance difference.
 109
 110     The spline indexing is isolated in the 2 inline functions:
 111     getSplineParamIndexBase() return a base shared memory index corresponding to the atom in the block;
 112     getSplineParamIndex() consumes its results and adds offsets for dimension and spline value index.
 113
 114     The corresponding defines follow.
 115  */
 116
 117 /*! \brief PME order parameter
 118  *
 119  *  Note that the GPU code, unlike the CPU, only supports order 4.
 120  */
 121 constexpr int c_pmeGpuOrder = 4;
 122
 123 /*! \brief
 124  * The number of GPU threads used for computing spread/gather contributions of a single atom as function of the PME order.
 125  * The assumption is currently that any thread processes only a single atom's contributions.
 126  * TODO: this assumption leads to minimum execution width of 16. See Redmine #2516
 127  */
 128 constexpr int c_pmeSpreadGatherThreadsPerAtom  = c_pmeGpuOrder*c_pmeGpuOrder;
 129
 130 //! Number of threads per atom when order threads are used
 131 constexpr int c_pmeSpreadGatherThreadsPerAtom4ThPerAtom = c_pmeGpuOrder;
 132
 133 /*! \brief Minimum execution width of the PME spread and gather kernels.
 134  *
 135  * Due to the one thread per atom and order=4 implementation constraints, order^2 threads
 136  * should execute without synchronization needed. See c_pmeSpreadGatherThreadsPerAtom
 137  */
 138 constexpr int c_pmeSpreadGatherMinWarpSize  = c_pmeSpreadGatherThreadsPerAtom;
 139
 140 //! Minimum warp size if order threads pera atom are used instead of order^2
 141 constexpr int c_pmeSpreadGatherMinWarpSize4ThPerAtom = c_pmeSpreadGatherThreadsPerAtom4ThPerAtom;
 142
 143 /*! \brief
 144  * Atom data alignment (in terms of number of atoms).
 145  * This is the least common multiple of number of atoms processed by
 146  * a single block/workgroup of the spread and gather kernels.
 147  * If the GPU atom data buffers are padded (c_usePadding == true),
 148  * Then the numbers of atoms which would fit in the padded GPU buffers have to be divisible by this.
 149  * There are debug asserts for this divisibility in pme_gpu_spread() and pme_gpu_gather().
 150  */
 151 constexpr int c_pmeAtomDataAlignment = 64;
 152
 153 /*
 154  * The execution widths for PME GPU kernels, used both on host and device for correct scheduling.
 155  * TODO: those were tuned for CUDA with assumption of warp size 32; specialize those for OpenCL
 156  * (Redmine #2528).
 157  * As noted below, these are very approximate maximum sizes; in run time we might have to use
 158  * smaller block/workgroup sizes, depending on device capabilities.
 159  */
 160
 161 //! Spreading max block width in warps picked among powers of 2 (2, 4, 8, 16) for max. occupancy and min. runtime in most cases
 162 constexpr int c_spreadMaxWarpsPerBlock = 8;
 163
 164 //! Solving kernel max block width in warps picked among powers of 2 (2, 4, 8, 16) for max. occupancy and min. runtime
 165 //! (560Ti (CC2.1), 660Ti (CC3.0) and 750 (CC5.0)))
 166 constexpr int c_solveMaxWarpsPerBlock = 8;
 167
 168 //! Gathering max block width in warps - picked empirically among 2, 4, 8, 16 for max. occupancy and min. runtime
 169 constexpr int c_gatherMaxWarpsPerBlock = 4;
 170
 171
 172 #if GMX_GPU == GMX_GPU_CUDA
 173
 174 /* All the guys below are dependent on warp_size and should ideally be removed from the host-side code,
 175  * as we have to do that for OpenCL already.
 176  * They also express maximum desired block/workgroup sizes, while both with CUDA and OpenCL we have to treat
 177  * the device runtime limitations gracefully as well.
 178  */
 179
 180 /*! \brief
 181  * The number of atoms processed by a single warp in spread/gather.
 182  * This macro depends on the templated order parameter (2 atoms per warp for order 4 and warp_size of 32).
 183  * It is mostly used for spline data layout tweaked for coalesced access.
 184  */
 185 constexpr int c_pmeSpreadGatherAtomsPerWarp  = (warp_size / c_pmeSpreadGatherThreadsPerAtom);
 186
 187 //! number of atoms per warp when order threads are used per atom
 188 constexpr int c_pmeSpreadGatherAtomsPerWarp4ThPerAtom = (warp_size / c_pmeSpreadGatherThreadsPerAtom4ThPerAtom);
 189
 190 //! Spreading max block size in threads
 191 constexpr int c_spreadMaxThreadsPerBlock = c_spreadMaxWarpsPerBlock * warp_size;
 192
 193 //! Solving kernel max block size in threads
 194 constexpr int c_solveMaxThreadsPerBlock = (c_solveMaxWarpsPerBlock * warp_size);
 195
 196 //! Gathering max block size in threads
 197 constexpr int c_gatherMaxThreadsPerBlock = c_gatherMaxWarpsPerBlock * warp_size;
 198 //! Gathering min blocks per CUDA multiprocessor
 199 constexpr int c_gatherMinBlocksPerMP = GMX_CUDA_MAX_THREADS_PER_MP / c_gatherMaxThreadsPerBlock;
 200
 201 #endif // GMX_GPU == GMX_GPU_CUDA
 202
 203 #endif