PowerPC: Optimized isinf/isinff for POWER8
commit1cd3b05dda2dab30cb7658193cb1af8f594f52f3
authorAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Thu, 27 Feb 2014 15:45:41 +0000 (27 09:45 -0600)
committerAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Mon, 3 Mar 2014 16:44:39 +0000 (3 10:44 -0600)
tree1730879cbd5ba5f7679c797486250f23f0f9dd6d
parent65c8daedb68b74eae860f91dca226215cd80e348
PowerPC: Optimized isinf/isinff for POWER8

This patch add a optimized isinf/isinff implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.

Backport of 4393fc119c34e97519b9b7a4fc94066b283be452
ChangeLog
sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinf-power8.S [copied from sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c with 60% similarity]
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinf.c
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c
sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S [copied from sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinf.c with 53% similarity]
sysdeps/powerpc/powerpc64/power8/fpu/s_isinff.S [new file with mode: 0644]