PowerPC: Optimized isinf/isinff for POWER8
commit4393fc119c34e97519b9b7a4fc94066b283be452
authorAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Thu, 27 Feb 2014 15:45:41 +0000 (27 09:45 -0600)
committerAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Thu, 27 Feb 2014 18:58:33 +0000 (27 12:58 -0600)
treedffac0629930499b0f88886fca4f1b094ef74fa5
parent487972aea52004f604c2878c8c9d3e77670f2c32
PowerPC: Optimized isinf/isinff for POWER8

This patch add a optimized isinf/isinff implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.
ChangeLog
sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinf-power8.S [copied from sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c with 60% similarity]
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinf.c
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c
sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S [copied from sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinf.c with 53% similarity]
sysdeps/powerpc/powerpc64/power8/fpu/s_isinff.S [new file with mode: 0644]