sysdeps/s390/fpu/fraiseexcpt.c

   1 /* Raise given exceptions.
   2    Copyright (C) 2000-2016 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4    Contributed by Denis Joseph Barrow (djbarrow@de.ibm.com) and
   5    Martin Schwidefsky (schwidefsky@de.ibm.com).
   6
   7    The GNU C Library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2.1 of the License, or (at your option) any later version.
  11
  12    The GNU C Library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with the GNU C Library; if not, see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 #include <fenv_libc.h>
  22 #include <float.h>
  23 #include <math.h>
  24
  25
  26 static __inline__ void
  27 fexceptdiv (float d, float e)
  28 {
  29   __asm__ __volatile__ ("debr %0,%1" : : "f" (d), "f" (e) );
  30 }
  31
  32 static __inline__ void
  33 fexceptadd (float d, float e)
  34 {
  35   __asm__ __volatile__ ("aebr %0,%1" : : "f" (d), "f" (e) );
  36 }
  37
  38 #ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
  39 static __inline__ void
  40 fexceptround (double e)
  41 {
  42   float d;
  43   /* Load rounded from double to float with M3 = round toward 0, M4 = Suppress
  44      IEEE-inexact exception.
  45      In case of e=0x1p128 and the overflow-mask bit is zero, only the
  46      IEEE-overflow flag is set. If overflow-mask bit is one, DXC field is set to
  47      0x20 "IEEE overflow, exact".
  48      In case of e=0x1p-150 and the underflow-mask bit is zero, only the
  49      IEEE-underflow flag is set. If underflow-mask bit is one, DXC field is set
  50      to 0x10 "IEEE underflow, exact".
  51      This instruction is available with a zarch machine >= z196.  */
  52   __asm__ __volatile__ ("ledbra %0,5,%1,4" : "=f" (d) : "f" (e) );
  53 }
  54 #endif
  55
  56 int
  57 __feraiseexcept (int excepts)
  58 {
  59   /* Raise exceptions represented by EXPECTS.  But we must raise only
  60      one signal at a time.  It is important that if the overflow/underflow
  61      exception and the inexact exception are given at the same time,
  62      the overflow/underflow exception follows the inexact exception.  */
  63
  64   /* First: invalid exception.  */
  65   if (FE_INVALID & excepts)
  66     fexceptdiv (0.0, 0.0);
  67
  68   /* Next: division by zero.  */
  69   if (FE_DIVBYZERO & excepts)
  70     fexceptdiv (1.0, 0.0);
  71
  72   /* Next: overflow.  */
  73   if (FE_OVERFLOW & excepts)
  74     {
  75 #ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
  76       fexceptround (0x1p128);
  77 #else
  78       /* If overflow-mask bit is zero, both IEEE-overflow and IEEE-inexact flags
  79          are set.  If overflow-mask bit is one, DXC field is set to 0x2C "IEEE
  80          overflow, inexact and incremented".  */
  81       fexceptadd (FLT_MAX, 1.0e32);
  82 #endif
  83     }
  84
  85   /* Next: underflow.  */
  86   if (FE_UNDERFLOW & excepts)
  87     {
  88 #ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
  89       fexceptround (0x1p-150);
  90 #else
  91       /* If underflow-mask bit is zero, both IEEE-underflow and IEEE-inexact
  92          flags are set.  If underflow-mask bit is one, DXC field is set to 0x1C
  93          "IEEE underflow, inexact and incremented".  */
  94       fexceptdiv (FLT_MIN, 3.0);
  95 #endif
  96     }
  97
  98   /* Last: inexact.  */
  99   if (FE_INEXACT & excepts)
 100     fexceptdiv (2.0, 3.0);
 101
 102   /* Success.  */
 103   return 0;
 104 }
 105 libm_hidden_def (__feraiseexcept)
 106 weak_alias (__feraiseexcept, feraiseexcept)
 107 libm_hidden_weak (feraiseexcept)