sysdeps/unix/sysv/linux/i386/sysconf.c

   1 /* Get file-specific information about a file.  Linux version.
   2    Copyright (C) 2003, 2004, 2006, 2007, 2009, 2011 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.  */
  19
  20 #include <assert.h>
  21 #include <stdbool.h>
  22 #include <stdlib.h>
  23 #include <unistd.h>
  24 #include <hp-timing.h>
  25
  26 static long int linux_sysconf (int name);
  27
  28
  29 static long int __attribute__ ((noinline))
  30 handle_i486 (int name)
  31 {
  32   /* The processor only has a unified level 1 cache of 8k.  */
  33   switch (name)
  34     {
  35     case _SC_LEVEL1_ICACHE_SIZE:
  36     case _SC_LEVEL1_DCACHE_SIZE:
  37       return 8 * 1024;
  38
  39     case _SC_LEVEL1_ICACHE_ASSOC:
  40     case _SC_LEVEL1_DCACHE_ASSOC:
  41       // XXX Anybody know this?
  42       return 0;
  43
  44     case _SC_LEVEL1_ICACHE_LINESIZE:
  45     case _SC_LEVEL1_DCACHE_LINESIZE:
  46       // XXX Anybody know for sure?
  47       return 16;
  48
  49     case _SC_LEVEL2_CACHE_SIZE:
  50     case _SC_LEVEL2_CACHE_ASSOC:
  51     case _SC_LEVEL2_CACHE_LINESIZE:
  52     case _SC_LEVEL3_CACHE_SIZE:
  53     case _SC_LEVEL3_CACHE_ASSOC:
  54     case _SC_LEVEL3_CACHE_LINESIZE:
  55     case _SC_LEVEL4_CACHE_SIZE:
  56     case _SC_LEVEL4_CACHE_ASSOC:
  57       /* Not available.  */
  58       break;
  59
  60     default:
  61       assert (! "cannot happen");
  62     }
  63
  64   return -1;
  65 }
  66
  67
  68 static const struct intel_02_cache_info
  69 {
  70   unsigned char idx;
  71   unsigned char assoc;
  72   unsigned char linesize;
  73   unsigned char rel_name;
  74   unsigned int size;
  75 } intel_02_known [] =
  76   {
  77 #define M(sc) ((sc) - _SC_LEVEL1_ICACHE_SIZE)
  78     { 0x06,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),    8192 },
  79     { 0x08,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),   16384 },
  80     { 0x09,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),   32768 },
  81     { 0x0a,  2, 32, M(_SC_LEVEL1_DCACHE_SIZE),    8192 },
  82     { 0x0c,  4, 32, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
  83     { 0x0d,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
  84     { 0x21,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
  85     { 0x22,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),   524288 },
  86     { 0x23,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
  87     { 0x25,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
  88     { 0x29,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
  89     { 0x2c,  8, 64, M(_SC_LEVEL1_DCACHE_SIZE),   32768 },
  90     { 0x30,  8, 64, M(_SC_LEVEL1_ICACHE_SIZE),   32768 },
  91     { 0x39,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
  92     { 0x3a,  6, 64, M(_SC_LEVEL2_CACHE_SIZE),   196608 },
  93     { 0x3b,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
  94     { 0x3c,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
  95     { 0x3d,  6, 64, M(_SC_LEVEL2_CACHE_SIZE),   393216 },
  96     { 0x3e,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
  97     { 0x3f,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
  98     { 0x41,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
  99     { 0x42,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
 100     { 0x43,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
 101     { 0x44,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
 102     { 0x45,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
 103     { 0x46,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
 104     { 0x47,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
 105     { 0x48, 12, 64, M(_SC_LEVEL2_CACHE_SIZE),  3145728 },
 106     { 0x49, 16, 64, M(_SC_LEVEL2_CACHE_SIZE),  4194304 },
 107     { 0x4a, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  6291456 },
 108     { 0x4b, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
 109     { 0x4c, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
 110     { 0x4d, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 16777216 },
 111     { 0x4e, 24, 64, M(_SC_LEVEL2_CACHE_SIZE),  6291456 },
 112     { 0x60,  8, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
 113     { 0x66,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),    8192 },
 114     { 0x67,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
 115     { 0x68,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   32768 },
 116     { 0x78,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
 117     { 0x79,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
 118     { 0x7a,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
 119     { 0x7b,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
 120     { 0x7c,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
 121     { 0x7d,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
 122     { 0x7f,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
 123     { 0x82,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
 124     { 0x83,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
 125     { 0x84,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
 126     { 0x85,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
 127     { 0x86,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
 128     { 0x87,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
 129     { 0xd0,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),   524288 },
 130     { 0xd1,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
 131     { 0xd2,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
 132     { 0xd6,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
 133     { 0xd7,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
 134     { 0xd8,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
 135     { 0xdc, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
 136     { 0xdd, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
 137     { 0xde, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
 138     { 0xe2, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
 139     { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
 140     { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
 141     { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
 142     { 0xeb, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 18874368 },
 143     { 0xec, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 25165824 },
 144   };
 145 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
 146
 147
 148 static int
 149 intel_02_known_compare (const void *p1, const void *p2)
 150 {
 151   const struct intel_02_cache_info *i1;
 152   const struct intel_02_cache_info *i2;
 153
 154   i1 = (const struct intel_02_cache_info *) p1;
 155   i2 = (const struct intel_02_cache_info *) p2;
 156
 157   if (i1->idx == i2->idx)
 158     return 0;
 159
 160   return i1->idx < i2->idx ? -1 : 1;
 161 }
 162
 163
 164 static long int
 165 __attribute__ ((noinline))
 166 intel_check_word (int name, unsigned int value, bool *has_level_2,
 167                   bool *no_level_2_or_3)
 168 {
 169   if ((value & 0x80000000) != 0)
 170     /* The register value is reserved.  */
 171     return 0;
 172
 173   /* Fold the name.  The _SC_ constants are always in the order SIZE,
 174      ASSOC, LINESIZE.  */
 175   int folded_rel_name = (M(name) / 3) * 3;
 176
 177   while (value != 0)
 178     {
 179       unsigned int byte = value & 0xff;
 180
 181       if (byte == 0x40)
 182         {
 183           *no_level_2_or_3 = true;
 184
 185           if (folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
 186             /* No need to look further.  */
 187             break;
 188         }
 189       else if (byte == 0xff)
 190         {
 191           /* CPUID leaf 0x4 contains all the information.  We need to
 192              iterate over it.  */
 193           unsigned int eax;
 194           unsigned int ebx;
 195           unsigned int ecx;
 196           unsigned int edx;
 197
 198           unsigned int round = 0;
 199           while (1)
 200             {
 201               asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 202                             : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 203                             : "0" (4), "2" (round));
 204
 205               enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f;
 206               if (type == null)
 207                 /* That was the end.  */
 208                 break;
 209
 210               unsigned int level = (eax >> 5) & 0x7;
 211
 212               if ((level == 1 && type == data
 213                    && folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE))
 214                   || (level == 1 && type == inst
 215                       && folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE))
 216                   || (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE))
 217                   || (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
 218                   || (level == 4 && folded_rel_name == M(_SC_LEVEL4_CACHE_SIZE)))
 219                 {
 220                   unsigned int offset = M(name) - folded_rel_name;
 221
 222                   if (offset == 0)
 223                     /* Cache size.  */
 224                     return (((ebx >> 22) + 1)
 225                             * (((ebx >> 12) & 0x3ff) + 1)
 226                             * ((ebx & 0xfff) + 1)
 227                             * (ecx + 1));
 228                   if (offset == 1)
 229                     return (ebx >> 22) + 1;
 230
 231                   assert (offset == 2);
 232                   return (ebx & 0xfff) + 1;
 233                 }
 234
 235               ++round;
 236             }
 237           /* There is no other cache information anywhere else.  */
 238           break;
 239         }
 240       else
 241         {
 242           if (byte == 0x49 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
 243             {
 244               /* Intel reused this value.  For family 15, model 6 it
 245                  specifies the 3rd level cache.  Otherwise the 2nd
 246                  level cache.  */
 247               unsigned int eax;
 248               unsigned int ebx;
 249               unsigned int ecx;
 250               unsigned int edx;
 251               asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 252                             : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 253                             : "0" (1));
 254
 255               unsigned int family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
 256               unsigned int model = ((((eax >>16) & 0xf) << 4)
 257                                     + ((eax >> 4) & 0xf));
 258               if (family == 15 && model == 6)
 259                 {
 260                   /* The level 3 cache is encoded for this model like
 261                      the level 2 cache is for other models.  Pretend
 262                      the caller asked for the level 2 cache.  */
 263                   name = (_SC_LEVEL2_CACHE_SIZE
 264                           + (name - _SC_LEVEL3_CACHE_SIZE));
 265                   folded_rel_name = M(_SC_LEVEL2_CACHE_SIZE);
 266                 }
 267             }
 268
 269           struct intel_02_cache_info *found;
 270           struct intel_02_cache_info search;
 271
 272           search.idx = byte;
 273           found = bsearch (&search, intel_02_known, nintel_02_known,
 274                            sizeof (intel_02_known[0]), intel_02_known_compare);
 275           if (found != NULL)
 276             {
 277               if (found->rel_name == folded_rel_name)
 278                 {
 279                   unsigned int offset = M(name) - folded_rel_name;
 280
 281                   if (offset == 0)
 282                     /* Cache size.  */
 283                     return found->size;
 284                   if (offset == 1)
 285                     return found->assoc;
 286
 287                   assert (offset == 2);
 288                   return found->linesize;
 289                 }
 290
 291               if (found->rel_name == M(_SC_LEVEL2_CACHE_SIZE))
 292                 *has_level_2 = true;
 293             }
 294         }
 295
 296       /* Next byte for the next round.  */
 297       value >>= 8;
 298     }
 299
 300   /* Nothing found.  */
 301   return 0;
 302 }
 303
 304
 305 static long int  __attribute__ ((noinline))
 306 handle_intel (int name, unsigned int maxidx)
 307 {
 308   if (maxidx < 2)
 309     {
 310       // XXX Do such processors exist?  When we know we can fill in some
 311       // values.
 312       return 0;
 313     }
 314
 315   /* OK, we can use the CPUID instruction to get all info about the
 316      caches.  */
 317   unsigned int cnt = 0;
 318   unsigned int max = 1;
 319   long int result = 0;
 320   bool no_level_2_or_3 = false;
 321   bool has_level_2 = false;
 322   while (cnt++ < max)
 323     {
 324       unsigned int eax;
 325       unsigned int ebx;
 326       unsigned int ecx;
 327       unsigned int edx;
 328       asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 329                     : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 330                     : "0" (2));
 331
 332       /* The low byte of EAX in the first round contain the number of
 333          rounds we have to make.  At least one, the one we are already
 334          doing.  */
 335       if (cnt == 1)
 336         {
 337           max = eax & 0xff;
 338           eax &= 0xffffff00;
 339         }
 340
 341       /* Process the individual registers' value.  */
 342       result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
 343       if (result != 0)
 344         return result;
 345
 346       result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
 347       if (result != 0)
 348         return result;
 349
 350       result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
 351       if (result != 0)
 352         return result;
 353
 354       result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
 355       if (result != 0)
 356         return result;
 357     }
 358
 359   if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
 360       && no_level_2_or_3)
 361     return -1;
 362
 363   return 0;
 364 }
 365
 366
 367 static long int __attribute__ ((noinline))
 368 handle_amd (int name)
 369 {
 370   unsigned int eax;
 371   unsigned int ebx;
 372   unsigned int ecx;
 373   unsigned int edx;
 374   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 375                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 376                 : "0" (0x80000000));
 377
 378   if (name >= _SC_LEVEL3_CACHE_SIZE)
 379     return 0;
 380
 381   unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
 382   if (eax < fn)
 383     return 0;
 384
 385   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 386                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 387                 : "0" (fn));
 388
 389   if (name < _SC_LEVEL1_DCACHE_SIZE)
 390     {
 391       name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
 392       ecx = edx;
 393     }
 394
 395   switch (name)
 396     {
 397     case _SC_LEVEL1_DCACHE_SIZE:
 398       return (ecx >> 14) & 0x3fc00;
 399     case _SC_LEVEL1_DCACHE_ASSOC:
 400       ecx >>= 16;
 401       if ((ecx & 0xff) == 0xff)
 402         /* Fully associative.  */
 403         return (ecx << 2) & 0x3fc00;
 404       return ecx & 0xff;
 405     case _SC_LEVEL1_DCACHE_LINESIZE:
 406       return ecx & 0xff;
 407     case _SC_LEVEL2_CACHE_SIZE:
 408       return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
 409     case _SC_LEVEL2_CACHE_ASSOC:
 410       ecx >>= 12;
 411       switch (ecx & 0xf)
 412         {
 413         case 0:
 414         case 1:
 415         case 2:
 416         case 4:
 417           return ecx & 0xf;
 418         case 6:
 419           return 8;
 420         case 8:
 421           return 16;
 422         case 0xf:
 423           return (ecx << 6) & 0x3fffc00;
 424         default:
 425           return 0;
 426         }
 427     case _SC_LEVEL2_CACHE_LINESIZE:
 428       return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
 429     default:
 430       assert (! "cannot happen");
 431     }
 432   return -1;
 433 }
 434
 435
 436 static int
 437 i386_i486_test (void)
 438 {
 439   int eflags;
 440   int ac;
 441   asm volatile ("pushfl;\n\t"
 442                 "popl %0;\n\t"
 443                 "movl $0x240000, %1;\n\t"
 444                 "xorl %0, %1;\n\t"
 445                 "pushl %1;\n\t"
 446                 "popfl;\n\t"
 447                 "pushfl;\n\t"
 448                 "popl %1;\n\t"
 449                 "xorl %0, %1;\n\t"
 450                 "pushl %0;\n\t"
 451                 "popfl"
 452                 : "=r" (eflags), "=r" (ac));
 453
 454   return ac;
 455 }
 456
 457
 458 /* Get the value of the system variable NAME.  */
 459 long int
 460 __sysconf (int name)
 461 {
 462   /* All the remainder, except the cache information, is handled in
 463      the generic code.  */
 464   if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
 465     return linux_sysconf (name);
 466
 467   /* Recognize i386 and compatible.  These don't have any cache on
 468      board.  */
 469   int ac = i386_i486_test ();
 470
 471   if (ac == 0)
 472     /* This is an i386.  */
 473     // XXX Is this true for all brands?
 474     return -1;
 475
 476   /* Detect i486, the last Intel processor without CPUID.  */
 477   if ((ac & (1 << 21)) == 0)
 478     {
 479       /* No CPUID.  */
 480       // XXX Fill in info about other brands.  For now only Intel.
 481       return handle_i486 (name);
 482     }
 483
 484   /* Find out what brand of processor.  */
 485   unsigned int eax;
 486   unsigned int ebx;
 487   unsigned int ecx;
 488   unsigned int edx;
 489   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 490                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 491                 : "0" (0));
 492
 493   /* This spells out "GenuineIntel".  */
 494   if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
 495     return handle_intel (name, eax);
 496
 497   /* This spells out "AuthenticAMD".  */
 498   if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
 499     return handle_amd (name);
 500
 501   // XXX Fill in more vendors.
 502
 503   /* CPU not known, we have no information.  */
 504   return 0;
 505 }
 506
 507 /* Now the generic Linux version.  */
 508 #undef __sysconf
 509 #define __sysconf static linux_sysconf
 510 #include "../sysconf.c"