1 #define _FP_W_TYPE_SIZE 64
2 #define _FP_W_TYPE unsigned long
3 #define _FP_WS_TYPE signed long
4 #define _FP_I_TYPE long
6 #define __FP_CLZ(r, x) \
8 __asm__("bsrq %1,%0" : "=r"(r) : "g"(x) : "cc"); \
12 #define _FP_NANFRAC_S _FP_QNANBIT_S
13 #define _FP_NANFRAC_D _FP_QNANBIT_D, 0
14 #define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0
15 #define _FP_NANSIGN_S 1
16 #define _FP_NANSIGN_D 1
17 #define _FP_NANSIGN_Q 1
19 #define _FP_KEEPNANFRACP 1
20 /* Here is something Intel misdesigned: the specs don't define
21 the case where we have two NaNs with same mantissas, but
22 different sign. Different operations pick up different NaNs.
24 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
26 if (_FP_FRAC_GT_##wc(X, Y) \
27 || (_FP_FRAC_EQ_##wc(X,Y) && (OP == '+' || OP == '*'))) \
30 _FP_FRAC_COPY_##wc(R,X); \
35 _FP_FRAC_COPY_##wc(R,Y); \
40 #define FP_EX_INVALID (1 << 0)
41 #define FP_EX_DENORM (1 << 1)
42 #define FP_EX_DIVZERO (1 << 2)
43 #define FP_EX_OVERFLOW (1 << 3)
44 #define FP_EX_UNDERFLOW (1 << 4)
45 #define FP_EX_INEXACT (1 << 5)
47 #define FP_RND_NEAREST 0