sysdeps/unix/sysv/linux/x86_64/sysconf.c

   1 /* Get file-specific information about a file.  Linux version.
   2    Copyright (C) 2003, 2004, 2006 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.  */
  19
  20 #include <assert.h>
  21 #include <stdbool.h>
  22 #include <stdlib.h>
  23 #include <unistd.h>
  24
  25
  26 static long int linux_sysconf (int name);
  27
  28
  29 static const struct intel_02_cache_info
  30 {
  31   unsigned int idx;
  32   int name;
  33   long int size;
  34   long int assoc;
  35   long int linesize;
  36 } intel_02_known[] =
  37   {
  38     { 0x06, _SC_LEVEL1_ICACHE_SIZE, 8192, 4, 32 },
  39     { 0x08, _SC_LEVEL1_ICACHE_SIZE, 16384, 4, 32 },
  40     { 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 },
  41     { 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 },
  42     { 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
  43     { 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
  44     { 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
  45     { 0x29, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
  46     { 0x2c, _SC_LEVEL1_DCACHE_SIZE, 32768, 8, 64 },
  47     { 0x30, _SC_LEVEL1_ICACHE_SIZE, 32768, 8, 64 },
  48     { 0x39, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 64 },
  49     { 0x3a, _SC_LEVEL2_CACHE_SIZE, 196608, 6, 64 },
  50     { 0x3b, _SC_LEVEL2_CACHE_SIZE, 131072, 2, 64 },
  51     { 0x3c, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 64 },
  52     { 0x3d, _SC_LEVEL2_CACHE_SIZE, 393216, 6, 64 },
  53     { 0x3e, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
  54     { 0x41, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 32 },
  55     { 0x42, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 32 },
  56     { 0x43, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 32 },
  57     { 0x44, _SC_LEVEL2_CACHE_SIZE, 1048576, 4, 32 },
  58     { 0x45, _SC_LEVEL2_CACHE_SIZE, 2097152, 4, 32 },
  59     { 0x46, _SC_LEVEL3_CACHE_SIZE, 4194304, 4, 64 },
  60     { 0x47, _SC_LEVEL3_CACHE_SIZE, 8388608, 8, 64 },
  61     { 0x49, _SC_LEVEL3_CACHE_SIZE, 4194304, 16, 64 },
  62     { 0x4a, _SC_LEVEL3_CACHE_SIZE, 6291456, 12, 64 },
  63     { 0x4b, _SC_LEVEL3_CACHE_SIZE, 8388608, 16, 64 },
  64     { 0x4c, _SC_LEVEL3_CACHE_SIZE, 12582912, 12, 64 },
  65     { 0x4d, _SC_LEVEL3_CACHE_SIZE, 16777216, 16, 64 },
  66     { 0x60, _SC_LEVEL1_DCACHE_SIZE, 16384, 8, 64 },
  67     { 0x66, _SC_LEVEL1_DCACHE_SIZE, 8192, 4, 64 },
  68     { 0x67, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
  69     { 0x68, _SC_LEVEL1_DCACHE_SIZE, 32768, 4, 64 },
  70     { 0x78, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
  71     { 0x79, _SC_LEVEL2_CACHE_SIZE, 131072, 8, 64 },
  72     { 0x7a, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
  73     { 0x7b, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 64 },
  74     { 0x7c, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
  75     { 0x7d, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 64 },
  76     { 0x7f, _SC_LEVEL2_CACHE_SIZE, 524288, 2, 64 },
  77     { 0x82, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 32 },
  78     { 0x83, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 32 },
  79     { 0x84, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 32 },
  80     { 0x85, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 32 },
  81     { 0x86, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
  82     { 0x87, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
  83   };
  84 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
  85
  86
  87 static int
  88 intel_02_known_compare (const void *p1, const void *p2)
  89 {
  90   const struct intel_02_cache_info *i1;
  91   const struct intel_02_cache_info *i2;
  92
  93   i1 = (const struct intel_02_cache_info *) p1;
  94   i2 = (const struct intel_02_cache_info *) p2;
  95
  96   if (i1->idx == i2->idx)
  97     return 0;
  98
  99   return i1->idx < i2->idx ? -1 : 1;
 100 }
 101
 102
 103 static long int
 104 intel_check_word (int name, unsigned int value, bool *has_level_2,
 105                   bool *no_level_2_or_3)
 106 {
 107   if ((value & 0x80000000) != 0)
 108     /* The register value is reserved.  */
 109     return 0;
 110
 111   /* Fold the name.  The _SC_ constants are always in the order SIZE,
 112      ASSOC, LINESIZE.  */
 113   int folded_name = (_SC_LEVEL1_ICACHE_SIZE
 114                      + ((name - _SC_LEVEL1_ICACHE_SIZE) / 3) * 3);
 115
 116   while (value != 0)
 117     {
 118       unsigned int byte = value & 0xff;
 119
 120       if (byte == 0x40)
 121         {
 122           *no_level_2_or_3 = true;
 123
 124           if (folded_name == _SC_LEVEL3_CACHE_SIZE)
 125             /* No need to look further.  */
 126             break;
 127         }
 128       else
 129         {
 130           struct intel_02_cache_info *found;
 131           struct intel_02_cache_info search;
 132
 133           search.idx = byte;
 134           found = bsearch (&search, intel_02_known, nintel_02_known,
 135                            sizeof (intel_02_known[0]), intel_02_known_compare);
 136           if (found != NULL)
 137             {
 138               if (found->name == folded_name)
 139                 {
 140                   unsigned int offset = name - folded_name;
 141
 142                   if (offset == 0)
 143                     /* Cache size.  */
 144                     return found->size;
 145                   if (offset == 1)
 146                     return found->assoc;
 147
 148                   assert (offset == 2);
 149                   return found->linesize;
 150                 }
 151
 152               if (found->name == _SC_LEVEL2_CACHE_SIZE)
 153                 *has_level_2 = true;
 154             }
 155         }
 156
 157       /* Next byte for the next round.  */
 158       value >>= 8;
 159     }
 160
 161   /* Nothing found.  */
 162   return 0;
 163 }
 164
 165
 166 static long int __attribute__ ((noinline))
 167 handle_intel (int name, unsigned int maxidx)
 168 {
 169   assert (maxidx >= 2);
 170
 171   /* OK, we can use the CPUID instruction to get all info about the
 172      caches.  */
 173   unsigned int cnt = 0;
 174   unsigned int max = 1;
 175   long int result = 0;
 176   bool no_level_2_or_3 = false;
 177   bool has_level_2 = false;
 178   while (cnt++ < max)
 179     {
 180       unsigned int eax;
 181       unsigned int ebx;
 182       unsigned int ecx;
 183       unsigned int edx;
 184       asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 185                     : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 186                     : "0" (2));
 187
 188       /* The low byte of EAX in the first round contain the number of
 189          rounds we have to make.  At least one, the one we are already
 190          doing.  */
 191       if (cnt == 1)
 192         {
 193           max = eax & 0xff;
 194           eax &= 0xffffff00;
 195         }
 196
 197       /* Process the individual registers' value.  */
 198       result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
 199       if (result != 0)
 200         return result;
 201
 202       result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
 203       if (result != 0)
 204         return result;
 205
 206       result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
 207       if (result != 0)
 208         return result;
 209
 210       result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
 211       if (result != 0)
 212         return result;
 213     }
 214
 215   if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
 216       && no_level_2_or_3)
 217     return -1;
 218
 219   return 0;
 220 }
 221
 222
 223 static long int __attribute__ ((noinline))
 224 handle_amd (int name)
 225 {
 226   unsigned int eax;
 227   unsigned int ebx;
 228   unsigned int ecx;
 229   unsigned int edx;
 230   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 231                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 232                 : "0" (0x80000000));
 233
 234   if (name >= _SC_LEVEL3_CACHE_SIZE)
 235     return 0;
 236
 237   unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
 238   if (eax < fn)
 239     return 0;
 240
 241   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 242                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 243                 : "0" (fn));
 244
 245   if (name < _SC_LEVEL1_DCACHE_SIZE)
 246     {
 247       name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
 248       ecx = edx;
 249     }
 250
 251   switch (name)
 252     {
 253     case _SC_LEVEL1_DCACHE_SIZE:
 254       return (ecx >> 14) & 0x3fc00;
 255     case _SC_LEVEL1_DCACHE_ASSOC:
 256       ecx >>= 16;
 257       if ((ecx & 0xff) == 0xff)
 258         /* Fully associative.  */
 259         return (ecx << 2) & 0x3fc00;
 260       return ecx & 0xff;
 261     case _SC_LEVEL1_DCACHE_LINESIZE:
 262       return ecx & 0xff;
 263     case _SC_LEVEL2_CACHE_SIZE:
 264       return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
 265     case _SC_LEVEL2_CACHE_ASSOC:
 266       ecx >>= 12;
 267       switch (ecx & 0xf)
 268         {
 269         case 0:
 270         case 1:
 271         case 2:
 272         case 4:
 273           return ecx & 0xf;
 274         case 6:
 275           return 8;
 276         case 8:
 277           return 16;
 278         case 0xf:
 279           return (ecx << 6) & 0x3fffc00;
 280         default:
 281           return 0;
 282         }
 283     case _SC_LEVEL2_CACHE_LINESIZE:
 284       return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
 285     default:
 286       assert (! "cannot happen");
 287     }
 288   return -1;
 289 }
 290
 291
 292 /* Get the value of the system variable NAME.  */
 293 long int
 294 __sysconf (int name)
 295 {
 296   /* We only handle the cache information here (for now).  */
 297   if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
 298     return linux_sysconf (name);
 299
 300   /* Find out what brand of processor.  */
 301   unsigned int eax;
 302   unsigned int ebx;
 303   unsigned int ecx;
 304   unsigned int edx;
 305   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 306                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 307                 : "0" (0));
 308
 309   /* This spells out "GenuineIntel".  */
 310   if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
 311     return handle_intel (name, eax);
 312
 313   /* This spells out "AuthenticAMD".  */
 314   if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
 315     return handle_amd (name);
 316
 317   // XXX Fill in more vendors.
 318
 319   /* CPU not known, we have no information.  */
 320   return 0;
 321 }
 322
 323 /* Now the generic Linux version.  */
 324 #undef __sysconf
 325 #define __sysconf static linux_sysconf
 326 #include "../sysconf.c"