aarch64/fpu: Add vector variants of erf
[glibc.git] / sysdeps / aarch64 / fpu / test-float-advsimd-wrappers.c
blob33ae92878f774ac3d422f0f5bd3795b1783eb941
1 /* Scalar wrappers for single-precision Advanced SIMD vector math functions.
3 Copyright (C) 2023-2024 Free Software Foundation, Inc.
4 This file is part of the GNU C Library.
6 The GNU C Library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 The GNU C Library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with the GNU C Library; if not, see
18 <https://www.gnu.org/licenses/>. */
20 #include <arm_neon.h>
22 #include "test-float-advsimd.h"
24 #define VEC_TYPE float32x4_t
26 VPCS_VECTOR_WRAPPER (acosf_advsimd, _ZGVnN4v_acosf)
27 VPCS_VECTOR_WRAPPER (asinf_advsimd, _ZGVnN4v_asinf)
28 VPCS_VECTOR_WRAPPER (atanf_advsimd, _ZGVnN4v_atanf)
29 VPCS_VECTOR_WRAPPER_ff (atan2f_advsimd, _ZGVnN4vv_atan2f)
30 VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf)
31 VPCS_VECTOR_WRAPPER (erff_advsimd, _ZGVnN4v_erff)
32 VPCS_VECTOR_WRAPPER (expf_advsimd, _ZGVnN4v_expf)
33 VPCS_VECTOR_WRAPPER (exp10f_advsimd, _ZGVnN4v_exp10f)
34 VPCS_VECTOR_WRAPPER (exp2f_advsimd, _ZGVnN4v_exp2f)
35 VPCS_VECTOR_WRAPPER (expm1f_advsimd, _ZGVnN4v_expm1f)
36 VPCS_VECTOR_WRAPPER (logf_advsimd, _ZGVnN4v_logf)
37 VPCS_VECTOR_WRAPPER (log10f_advsimd, _ZGVnN4v_log10f)
38 VPCS_VECTOR_WRAPPER (log1pf_advsimd, _ZGVnN4v_log1pf)
39 VPCS_VECTOR_WRAPPER (log2f_advsimd, _ZGVnN4v_log2f)
40 VPCS_VECTOR_WRAPPER (sinf_advsimd, _ZGVnN4v_sinf)
41 VPCS_VECTOR_WRAPPER (tanf_advsimd, _ZGVnN4v_tanf)