sysdeps/powerpc/bits/fenv.h

   1 /* Copyright (C) 1997-2014 Free Software Foundation, Inc.
   2    This file is part of the GNU C Library.
   3
   4    The GNU C Library is free software; you can redistribute it and/or
   5    modify it under the terms of the GNU Lesser General Public
   6    License as published by the Free Software Foundation; either
   7    version 2.1 of the License, or (at your option) any later version.
   8
   9    The GNU C Library is distributed in the hope that it will be useful,
  10    but WITHOUT ANY WARRANTY; without even the implied warranty of
  11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12    Lesser General Public License for more details.
  13
  14    You should have received a copy of the GNU Lesser General Public
  15    License along with the GNU C Library; if not, see
  16    <http://www.gnu.org/licenses/>.  */
  17
  18 #ifndef _FENV_H
  19 # error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
  20 #endif
  21
  22
  23 /* Define bits representing the exception.  We use the bit positions of
  24    the appropriate bits in the FPSCR...  */
  25 enum
  26   {
  27     FE_INEXACT =
  28 #define FE_INEXACT      (1 << (31 - 6))
  29       FE_INEXACT,
  30     FE_DIVBYZERO =
  31 #define FE_DIVBYZERO    (1 << (31 - 5))
  32       FE_DIVBYZERO,
  33     FE_UNDERFLOW =
  34 #define FE_UNDERFLOW    (1 << (31 - 4))
  35       FE_UNDERFLOW,
  36     FE_OVERFLOW =
  37 #define FE_OVERFLOW     (1 << (31 - 3))
  38       FE_OVERFLOW,
  39
  40     /* ... except for FE_INVALID, for which we use bit 31. FE_INVALID
  41        actually corresponds to bits 7 through 12 and 21 through 23
  42        in the FPSCR, but we can't use that because the current draft
  43        says that it must be a power of 2.  Instead we use bit 2 which
  44        is the summary bit for all the FE_INVALID exceptions, which
  45        kind of makes sense.  */
  46     FE_INVALID =
  47 #define FE_INVALID      (1 << (31 - 2))
  48       FE_INVALID,
  49
  50 #ifdef __USE_GNU
  51     /* Breakdown of the FE_INVALID bits. Setting FE_INVALID on an
  52        input to a routine is equivalent to setting all of these bits;
  53        FE_INVALID will be set on output from a routine iff one of
  54        these bits is set.  Note, though, that you can't disable or
  55        enable these exceptions individually.  */
  56
  57     /* Operation with a sNaN.  */
  58     FE_INVALID_SNAN =
  59 # define FE_INVALID_SNAN        (1 << (31 - 7))
  60       FE_INVALID_SNAN,
  61
  62     /* Inf - Inf */
  63     FE_INVALID_ISI =
  64 # define FE_INVALID_ISI (1 << (31 - 8))
  65       FE_INVALID_ISI,
  66
  67     /* Inf / Inf */
  68     FE_INVALID_IDI =
  69 # define FE_INVALID_IDI (1 << (31 - 9))
  70       FE_INVALID_IDI,
  71
  72     /* 0 / 0 */
  73     FE_INVALID_ZDZ =
  74 # define FE_INVALID_ZDZ (1 << (31 - 10))
  75       FE_INVALID_ZDZ,
  76
  77     /* Inf * 0 */
  78     FE_INVALID_IMZ =
  79 # define FE_INVALID_IMZ (1 << (31 - 11))
  80       FE_INVALID_IMZ,
  81
  82     /* Comparison with a NaN.  */
  83     FE_INVALID_COMPARE =
  84 # define FE_INVALID_COMPARE     (1 << (31 - 12))
  85       FE_INVALID_COMPARE,
  86
  87     /* Invalid operation flag for software (not set by hardware).  */
  88     /* Note that some chips don't have this implemented, presumably
  89        because no-one expected anyone to write software for them %-).  */
  90     FE_INVALID_SOFTWARE =
  91 # define FE_INVALID_SOFTWARE    (1 << (31 - 21))
  92       FE_INVALID_SOFTWARE,
  93
  94     /* Square root of negative number (including -Inf).  */
  95     /* Note that some chips don't have this implemented.  */
  96     FE_INVALID_SQRT =
  97 # define FE_INVALID_SQRT        (1 << (31 - 22))
  98       FE_INVALID_SQRT,
  99
 100     /* Conversion-to-integer of a NaN or a number too large or too small.  */
 101     FE_INVALID_INTEGER_CONVERSION =
 102 # define FE_INVALID_INTEGER_CONVERSION  (1 << (31 - 23))
 103       FE_INVALID_INTEGER_CONVERSION
 104
 105 # define FE_ALL_INVALID \
 106         (FE_INVALID_SNAN | FE_INVALID_ISI | FE_INVALID_IDI | FE_INVALID_ZDZ \
 107          | FE_INVALID_IMZ | FE_INVALID_COMPARE | FE_INVALID_SOFTWARE \
 108          | FE_INVALID_SQRT | FE_INVALID_INTEGER_CONVERSION)
 109 #endif
 110   };
 111
 112 #define FE_ALL_EXCEPT \
 113         (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
 114
 115 /* PowerPC chips support all of the four defined rounding modes.  We
 116    use the bit pattern in the FPSCR as the values for the
 117    appropriate macros.  */
 118 enum
 119   {
 120     FE_TONEAREST =
 121 #define FE_TONEAREST    0
 122       FE_TONEAREST,
 123     FE_TOWARDZERO =
 124 #define FE_TOWARDZERO   1
 125       FE_TOWARDZERO,
 126     FE_UPWARD =
 127 #define FE_UPWARD       2
 128       FE_UPWARD,
 129     FE_DOWNWARD =
 130 #define FE_DOWNWARD     3
 131       FE_DOWNWARD
 132   };
 133
 134 /* Type representing exception flags.  */
 135 typedef unsigned int fexcept_t;
 136
 137 /* Type representing floating-point environment.  We leave it as 'double'
 138    for efficiency reasons (rather than writing it to a 32-bit integer). */
 139 typedef double fenv_t;
 140
 141 /* If the default argument is used we use this value.  */
 142 extern const fenv_t __fe_dfl_env;
 143 #define FE_DFL_ENV      (&__fe_dfl_env)
 144
 145 #ifdef __USE_GNU
 146 /* Floating-point environment where all exceptions are enabled.  Note that
 147    this is not sufficient to give you SIGFPE.  */
 148 extern const fenv_t __fe_enabled_env;
 149 # define FE_ENABLED_ENV (&__fe_enabled_env)
 150
 151 /* Floating-point environment with (processor-dependent) non-IEEE floating
 152    point.  */
 153 extern const fenv_t __fe_nonieee_env;
 154 # define FE_NONIEEE_ENV (&__fe_nonieee_env)
 155
 156 /* Floating-point environment with all exceptions enabled.  Note that
 157    just evaluating this value does not change the processor exception mode.
 158    Passing this mask to fesetenv will result in a prctl syscall to change
 159    the MSR FE0/FE1 bits to "Precise Mode".  On some processors this will
 160    result in slower floating point execution.  This will last until an
 161    fenv or exception mask is installed that disables all FP exceptions.  */
 162 # define FE_NOMASK_ENV  FE_ENABLED_ENV
 163
 164 /* Floating-point environment with all exceptions disabled.  Note that
 165    just evaluating this value does not change the processor exception mode.
 166    Passing this mask to fesetenv will result in a prctl syscall to change
 167    the MSR FE0/FE1 bits to "Ignore Exceptions Mode".  On most processors
 168    this allows the fastest possible floating point execution.*/
 169 # define FE_MASK_ENV    FE_DFL_ENV
 170
 171 #endif