1 @node Platform, Contributors, Maintenance, Top
2 @c %MENU% Describe all platform-specific facilities provided
3 @appendix Platform-specific facilities
5 @Theglibc{} can provide machine-specific functionality.
8 * PowerPC:: Facilities Specific to the PowerPC Architecture
9 * RISC-V:: Facilities Specific to the RISC-V Architecture
10 * X86:: Facilities Specific to the X86 Architecture
14 @appendixsec PowerPC-specific Facilities
16 Facilities specific to PowerPC that are not specific to a particular
17 operating system are declared in @file{sys/platform/ppc.h}.
19 @deftypefun {uint64_t} __ppc_get_timebase (void)
20 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
21 Read the current value of the Time Base Register.
23 The @dfn{Time Base Register} is a 64-bit register that stores a monotonically
24 incremented value updated at a system-dependent frequency that may be
25 different from the processor frequency. More information is available in
26 @cite{Power ISA 2.06b - Book II - Section 5.2}.
28 @code{__ppc_get_timebase} uses the processor's time base facility directly
29 without requiring assistance from the operating system, so it is very
33 @deftypefun {uint64_t} __ppc_get_timebase_freq (void)
34 @safety{@prelim{}@mtunsafe{@mtuinit{}}@asunsafe{@asucorrupt{:init}}@acunsafe{@acucorrupt{:init}}}
35 @c __ppc_get_timebase_freq=__get_timebase_freq @mtuinit @acsfd
36 @c __get_clockfreq @mtuinit @asucorrupt:init @acucorrupt:init @acsfd
37 @c the initialization of the static timebase_freq is not exactly
38 @c safe, because hp_timing_t cannot be atomically set up.
39 @c syscall:get_tbfreq ok
45 Read the current frequency at which the Time Base Register is updated.
47 This frequency is not related to the processor clock or the bus clock.
48 It is also possible that this frequency is not constant. More information is
49 available in @cite{Power ISA 2.06b - Book II - Section 5.2}.
52 The following functions provide hints about the usage of resources that are
53 shared with other processors. They can be used, for example, if a program
54 waiting on a lock intends to divert the shared resources to be used by other
55 processors. More information is available in @cite{Power ISA 2.06b - Book II -
58 @deftypefun {void} __ppc_yield (void)
59 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
60 Provide a hint that performance will probably be improved if shared resources
61 dedicated to the executing processor are released for use by other processors.
64 @deftypefun {void} __ppc_mdoio (void)
65 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
66 Provide a hint that performance will probably be improved if shared resources
67 dedicated to the executing processor are released until all outstanding storage
68 accesses to caching-inhibited storage have been completed.
71 @deftypefun {void} __ppc_mdoom (void)
72 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
73 Provide a hint that performance will probably be improved if shared resources
74 dedicated to the executing processor are released until all outstanding storage
75 accesses to cacheable storage for which the data is not in the cache have been
79 @deftypefun {void} __ppc_set_ppr_med (void)
80 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
81 Set the Program Priority Register to medium value (default).
83 The @dfn{Program Priority Register} (PPR) is a 64-bit register that controls
84 the program's priority. By adjusting the PPR value the programmer may
85 improve system throughput by causing the system resources to be used
86 more efficiently, especially in contention situations.
87 The three unprivileged states available are covered by the functions
88 @code{__ppc_set_ppr_med} (medium -- default), @code{__ppc_set_ppc_low} (low)
89 and @code{__ppc_set_ppc_med_low} (medium low). More information
90 available in @cite{Power ISA 2.06b - Book II - Section 3.1}.
93 @deftypefun {void} __ppc_set_ppr_low (void)
94 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
95 Set the Program Priority Register to low value.
98 @deftypefun {void} __ppc_set_ppr_med_low (void)
99 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
100 Set the Program Priority Register to medium low value.
103 Power ISA 2.07 extends the priorities that can be set to the Program Priority
104 Register (PPR). The following functions implement the new priority levels:
105 very low and medium high.
107 @deftypefun {void} __ppc_set_ppr_very_low (void)
108 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
109 Set the Program Priority Register to very low value.
112 @deftypefun {void} __ppc_set_ppr_med_high (void)
113 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
114 Set the Program Priority Register to medium high value. The medium high
115 priority is privileged and may only be set during certain time intervals by
116 problem-state programs. If the program priority is medium high when the time
117 interval expires or if an attempt is made to set the priority to medium high
118 when it is not allowed, the priority is set to medium.
122 @appendixsec RISC-V-specific Facilities
124 Cache management facilities specific to RISC-V systems that implement the Linux
125 ABI are declared in @file{sys/cachectl.h}.
127 @deftypefun {void} __riscv_flush_icache (void *@var{start}, void *@var{end}, unsigned long int @var{flags})
128 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
129 Enforce ordering between stores and instruction cache fetches. The range of
130 addresses over which ordering is enforced is specified by @var{start} and
131 @var{end}. The @var{flags} argument controls the extent of this ordering, with
132 the default behavior (a @var{flags} value of 0) being to enforce the fence on
133 all threads in the current process. Setting the
134 @code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing
135 ordering on only the current thread is necessary. All other flag bits are
140 @appendixsec X86-specific Facilities
142 Facilities specific to X86 that are not specific to a particular
143 operating system are declared in @file{sys/platform/x86.h}.
145 @deftypefun {const struct cpuid_feature *} __x86_get_cpuid_feature_leaf (unsigned int @var{leaf})
146 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
147 Return a pointer to x86 CPU feature structure used by query macros for x86
148 CPU feature @var{leaf}.
151 @deftypefn Macro int CPU_FEATURE_PRESENT (@var{name})
152 This macro returns a nonzero value (true) if the processor has the feature
156 @deftypefn Macro int CPU_FEATURE_ACTIVE (@var{name})
157 This macro returns a nonzero value (true) if the processor has the feature
158 @var{name} and the feature is active. There may be other preconditions,
159 like sufficient stack space or further setup for AMX, which must be
160 satisfied before the feature can be used.
163 The supported processor features are:
168 @code{ACPI} -- Thermal Monitor and Software Controlled Clock Facilities.
171 @code{ADX} -- ADX instruction extensions.
174 @code{APIC} -- APIC On-Chip.
177 @code{AES} -- The AES instruction extensions.
180 @code{AESKLE} -- AES Key Locker instructions are enabled by OS.
183 @code{AMD_IBPB} -- Indirect branch predictor barrier (IBPB) for AMD cpus.
186 @code{AMD_IBRS} -- Indirect branch restricted speculation (IBPB) for AMD cpus.
189 @code{AMD_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus.
192 @code{AMD_STIBP} -- Single thread indirect branch predictors (STIBP) for AMD cpus.
195 @code{AMD_VIRT_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus (older systems).
198 @code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
201 @code{AMX_INT8} -- Tile computational operations on 8-bit numbers.
204 @code{AMX_TILE} -- Tile architecture.
207 @code{ARCH_CAPABILITIES} -- IA32_ARCH_CAPABILITIES MSR.
210 @code{AVX} -- The AVX instruction extensions.
213 @code{AVX2} -- The AVX2 instruction extensions.
216 @code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
219 @code{AVX512_4FMAPS} -- The AVX512_4FMAPS instruction extensions.
222 @code{AVX512_4VNNIW} -- The AVX512_4VNNIW instruction extensions.
225 @code{AVX512_BF16} -- The AVX512_BF16 instruction extensions.
228 @code{AVX512_BITALG} -- The AVX512_BITALG instruction extensions.
231 @code{AVX512_FP16} -- The AVX512_FP16 instruction extensions.
234 @code{AVX512_IFMA} -- The AVX512_IFMA instruction extensions.
237 @code{AVX512_VBMI} -- The AVX512_VBMI instruction extensions.
240 @code{AVX512_VBMI2} -- The AVX512_VBMI2 instruction extensions.
243 @code{AVX512_VNNI} -- The AVX512_VNNI instruction extensions.
246 @code{AVX512_VP2INTERSECT} -- The AVX512_VP2INTERSECT instruction
250 @code{AVX512_VPOPCNTDQ} -- The AVX512_VPOPCNTDQ instruction extensions.
253 @code{AVX512BW} -- The AVX512BW instruction extensions.
256 @code{AVX512CD} -- The AVX512CD instruction extensions.
259 @code{AVX512ER} -- The AVX512ER instruction extensions.
262 @code{AVX512DQ} -- The AVX512DQ instruction extensions.
265 @code{AVX512F} -- The AVX512F instruction extensions.
268 @code{AVX512PF} -- The AVX512PF instruction extensions.
271 @code{AVX512VL} -- The AVX512VL instruction extensions.
274 @code{BMI1} -- BMI1 instructions.
277 @code{BMI2} -- BMI2 instructions.
280 @code{BUS_LOCK_DETECT} -- Bus lock debug exceptions.
283 @code{CLDEMOTE} -- CLDEMOTE instruction.
286 @code{CLFLUSHOPT} -- CLFLUSHOPT instruction.
289 @code{CLFSH} -- CLFLUSH instruction.
292 @code{CLWB} -- CLWB instruction.
295 @code{CMOV} -- Conditional Move instructions.
298 @code{CMPXCHG16B} -- CMPXCHG16B instruction.
301 @code{CNXT_ID} -- L1 Context ID.
304 @code{CORE_CAPABILITIES} -- IA32_CORE_CAPABILITIES MSR.
307 @code{CX8} -- CMPXCHG8B instruction.
310 @code{DCA} -- Data prefetch from a memory mapped device.
313 @code{DE} -- Debugging Extensions.
316 @code{DEPR_FPU_CS_DS} -- Deprecates FPU CS and FPU DS values.
319 @code{DS} -- Debug Store.
322 @code{DS_CPL} -- CPL Qualified Debug Store.
325 @code{DTES64} -- 64-bit DS Area.
328 @code{EIST} -- Enhanced Intel SpeedStep technology.
331 @code{ENQCMD} -- Enqueue Stores instructions.
334 @code{ERMS} -- Enhanced REP MOVSB/STOSB.
337 @code{F16C} -- 16-bit floating-point conversion instructions.
340 @code{FMA} -- FMA extensions using YMM state.
343 @code{FMA4} -- FMA4 instruction extensions.
346 @code{FPU} -- X87 Floating Point Unit On-Chip.
349 @code{FSGSBASE} -- RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instructions.
352 @code{FSRCS} -- Fast Short REP CMP and SCA.
355 @code{FSRM} -- Fast Short REP MOV.
358 @code{FSRS} -- Fast Short REP STO.
361 @code{FXSR} -- FXSAVE and FXRSTOR instructions.
364 @code{FZLRM} -- Fast Zero-Length REP MOV.
367 @code{GFNI} -- GFNI instruction extensions.
370 @code{HLE} -- HLE instruction extensions.
373 @code{HTT} -- Max APIC IDs reserved field is Valid.
376 @code{HRESET} -- History reset.
379 @code{HYBRID} -- Hybrid processor.
382 @code{IBRS_IBPB} -- Indirect branch restricted speculation (IBRS) and
383 the indirect branch predictor barrier (IBPB).
386 @code{IBT} -- Intel Indirect Branch Tracking instruction extensions.
389 @code{INVARIANT_TSC} -- Invariant TSC.
392 @code{INVPCID} -- INVPCID instruction.
395 @code{KL} -- AES Key Locker instructions.
398 @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
401 @code{LA57} -- 57-bit linear addresses and five-level paging.
404 @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
407 @code{LAM} -- Linear Address Masking.
410 @code{LASS} -- Linear Address Space Separation.
413 @code{LBR} -- Architectural LBR.
416 @code{LM} -- Long mode.
419 @code{LWP} -- Lightweight profiling.
422 @code{LZCNT} -- LZCNT instruction.
425 @code{MCA} -- Machine Check Architecture.
428 @code{MCE} -- Machine Check Exception.
431 @code{MD_CLEAR} -- MD_CLEAR.
434 @code{MMX} -- Intel MMX Technology.
437 @code{MONITOR} -- MONITOR/MWAIT instructions.
440 @code{MOVBE} -- MOVBE instruction.
443 @code{MOVDIRI} -- MOVDIRI instruction.
446 @code{MOVDIR64B} -- MOVDIR64B instruction.
449 @code{MPX} -- Intel Memory Protection Extensions.
452 @code{MSR} -- Model Specific Registers RDMSR and WRMSR instructions.
455 @code{MTRR} -- Memory Type Range Registers.
458 @code{NX} -- No-execute page protection.
461 @code{OSPKE} -- OS has set CR4.PKE to enable protection keys.
464 @code{OSXSAVE} -- The OS has set CR4.OSXSAVE[bit 18] to enable
465 XSETBV/XGETBV instructions to access XCR0 and to support processor
466 extended state management using XSAVE/XRSTOR.
469 @code{PAE} -- Physical Address Extension.
472 @code{PAGE1GB} -- 1-GByte page.
475 @code{PAT} -- Page Attribute Table.
478 @code{PBE} -- Pending Break Enable.
481 @code{PCID} -- Process-context identifiers.
484 @code{PCLMULQDQ} -- PCLMULQDQ instruction.
487 @code{PCONFIG} -- PCONFIG instruction.
490 @code{PDCM} -- Perfmon and Debug Capability.
493 @code{PGE} -- Page Global Bit.
496 @code{PKS} -- Protection keys for supervisor-mode pages.
499 @code{PKU} -- Protection keys for user-mode pages.
502 @code{POPCNT} -- POPCNT instruction.
505 @code{PREFETCHW} -- PREFETCHW instruction.
508 @code{PREFETCHWT1} -- PREFETCHWT1 instruction.
511 @code{PSE} -- Page Size Extension.
514 @code{PSE_36} -- 36-Bit Page Size Extension.
517 @code{PSN} -- Processor Serial Number.
520 @code{PTWRITE} -- PTWRITE instruction.
523 @code{RAO_INT} -- RAO-INT instructions.
526 @code{RDPID} -- RDPID instruction.
529 @code{RDRAND} -- RDRAND instruction.
532 @code{RDSEED} -- RDSEED instruction.
535 @code{RDT_A} -- Intel Resource Director Technology (Intel RDT) Allocation
539 @code{RDT_M} -- Intel Resource Director Technology (Intel RDT) Monitoring
543 @code{RDTSCP} -- RDTSCP instruction.
546 @code{RTM} -- RTM instruction extensions.
549 @code{RTM_ALWAYS_ABORT} -- Transactions always abort, making RTM unusable.
552 @code{RTM_FORCE_ABORT} -- TSX_FORCE_ABORT MSR.
555 @code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug.
558 @code{SEP} -- SYSENTER and SYSEXIT instructions.
561 @code{SERIALIZE} -- SERIALIZE instruction.
564 @code{SGX} -- Intel Software Guard Extensions.
567 @code{SGX_KEYS} -- Attestation Services for SGX.
570 @code{SGX_LC} -- SGX Launch Configuration.
573 @code{SHA} -- SHA instruction extensions.
576 @code{SHSTK} -- Intel Shadow Stack instruction extensions.
579 @code{SMAP} -- Supervisor-Mode Access Prevention.
582 @code{SMEP} -- Supervisor-Mode Execution Prevention.
585 @code{SMX} -- Safer Mode Extensions.
588 @code{SS} -- Self Snoop.
591 @code{SSBD} -- Speculative Store Bypass Disable (SSBD).
594 @code{SSE} -- Streaming SIMD Extensions.
597 @code{SSE2} -- Streaming SIMD Extensions 2.
600 @code{SSE3} -- Streaming SIMD Extensions 3.
603 @code{SSE4_1} -- Streaming SIMD Extensions 4.1.
606 @code{SSE4_2} -- Streaming SIMD Extensions 4.2.
609 @code{SSE4A} -- SSE4A instruction extensions.
612 @code{SSSE3} -- Supplemental Streaming SIMD Extensions 3.
615 @code{STIBP} -- Single thread indirect branch predictors (STIBP).
618 @code{SVM} -- Secure Virtual Machine.
621 @code{SYSCALL_SYSRET} -- SYSCALL/SYSRET instructions.
624 @code{TBM} -- Trailing bit manipulation instructions.
627 @code{TM} -- Thermal Monitor.
630 @code{TM2} -- Thermal Monitor 2.
633 @code{TRACE} -- Intel Processor Trace.
636 @code{TSC} -- Time Stamp Counter. RDTSC instruction.
639 @code{TSC_ADJUST} -- IA32_TSC_ADJUST MSR.
642 @code{TSC_DEADLINE} -- Local APIC timer supports one-shot operation
643 using a TSC deadline value.
646 @code{TSXLDTRK} -- TSXLDTRK instructions.
649 @code{UINTR} -- User interrupts.
652 @code{UMIP} -- User-mode instruction prevention.
655 @code{VAES} -- VAES instruction extensions.
658 @code{VME} -- Virtual 8086 Mode Enhancements.
661 @code{VMX} -- Virtual Machine Extensions.
664 @code{VPCLMULQDQ} -- VPCLMULQDQ instruction.
667 @code{WAITPKG} -- WAITPKG instruction extensions.
670 @code{WBNOINVD} -- WBINVD/WBNOINVD instructions.
673 @code{WIDE_KL} -- AES wide Key Locker instructions.
676 @code{X2APIC} -- x2APIC.
679 @code{XFD} -- Extended Feature Disable (XFD).
682 @code{XGETBV_ECX_1} -- XGETBV with ECX = 1.
685 @code{XOP} -- XOP instruction extensions.
688 @code{XSAVE} -- The XSAVE/XRSTOR processor extended states feature, the
689 XSETBV/XGETBV instructions, and XCR0.
692 @code{XSAVEC} -- XSAVEC instruction.
695 @code{XSAVEOPT} -- XSAVEOPT instruction.
698 @code{XSAVES} -- XSAVES/XRSTORS instructions.
701 @code{XTPRUPDCTRL} -- xTPR Update Control.
705 You could query if a processor supports @code{AVX} with:
708 #include <sys/platform/x86.h>
713 return CPU_FEATURE_PRESENT (AVX);
717 and if @code{AVX} is active and may be used with:
720 #include <sys/platform/x86.h>
725 return CPU_FEATURE_ACTIVE (AVX);