sysdeps/aarch64/fpu/fpu_control.h

   1 /* Copyright (C) 1996-2014 Free Software Foundation, Inc.
   2
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public License as
   7    published by the Free Software Foundation; either version 2.1 of the
   8    License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, see
  17    <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef _AARCH64_FPU_CONTROL_H
  20 #define _AARCH64_FPU_CONTROL_H
  21
  22 /* Macros for accessing the FPCR and FPSR.  */
  23
  24 #define _FPU_GETCW(fpcr) \
  25   __asm__ __volatile__ ("mrs    %0, fpcr" : "=r" (fpcr))
  26
  27 #define _FPU_SETCW(fpcr)                                   \
  28   {                                                        \
  29     __asm__ __volatile__ ("msr  fpcr, %0" : : "r" (fpcr)); \
  30     __asm__ __volatile__ ("isb");                          \
  31   }
  32
  33 #define _FPU_GETFPSR(fpsr) \
  34   __asm__ __volatile__ ("mrs    %0, fpsr" : "=r" (fpsr))
  35
  36 #define _FPU_SETFPSR(fpsr) \
  37   __asm__ __volatile__ ("msr    fpsr, %0" : : "r" (fpsr))
  38
  39 /* Reserved bits should be preserved when modifying register
  40    contents. These two masks indicate which bits in each of FPCR and
  41    FPSR should not be changed.  */
  42
  43 #define _FPU_RESERVED           0xfe0fe0ff
  44 #define _FPU_FPSR_RESERVED      0x0fffffe0
  45
  46 #define _FPU_DEFAULT            0x00000000
  47 #define _FPU_FPSR_DEFAULT       0x00000000
  48
  49 /* Layout of FPCR and FPSR:
  50
  51    |       |       |       |       |       |       |       |
  52    0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0
  53    s s s s s                                       s     s s s s s
  54              c c c c c c c               c c c c c
  55    N Z C V Q A D F R R S S S L L L I U U I U O D I I U U I U O D I
  56            C H N Z M M T T B E E E D N N X F F Z O D N N X F F Z O
  57              P     O O R R Z N N N E K K E E E E E C K K C C C C C
  58                    D D I I P
  59                    E E D D
  60                        E E
  61  */
  62
  63 #define _FPU_FPCR_RM_MASK  0xc00000
  64
  65 #define _FPU_FPCR_MASK_IXE 0x1000
  66 #define _FPU_FPCR_MASK_UFE 0x0800
  67 #define _FPU_FPCR_MASK_OFE 0x0400
  68 #define _FPU_FPCR_MASK_DZE 0x0200
  69 #define _FPU_FPCR_MASK_IOE 0x0100
  70
  71 #define _FPU_FPCR_IEEE                       \
  72   (_FPU_DEFAULT  | _FPU_FPCR_MASK_IXE |      \
  73    _FPU_FPCR_MASK_UFE | _FPU_FPCR_MASK_OFE | \
  74    _FPU_FPCR_MASK_DZE | _FPU_FPCR_MASK_IOE)
  75
  76 #define _FPU_FPSR_IEEE 0
  77
  78 typedef unsigned int fpu_control_t;
  79 typedef unsigned int fpu_fpsr_t;
  80
  81 /* Default control word set at startup.  */
  82 extern fpu_control_t __fpu_control;
  83
  84 #endif