sysdeps/unix/sysv/linux/i386/sysconf.c

   1 /* Get file-specific information about a file.  Linux version.
   2    Copyright (C) 2003, 2004, 2006 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.  */
  19
  20 #include <assert.h>
  21 #include <stdbool.h>
  22 #include <stdlib.h>
  23 #include <unistd.h>
  24 #include <hp-timing.h>
  25
  26 static long int linux_sysconf (int name);
  27
  28
  29 static long int __attribute__ ((noinline))
  30 handle_i486 (int name)
  31 {
  32   /* The processor only has a unified level 1 cache of 8k.  */
  33   switch (name)
  34     {
  35     case _SC_LEVEL1_ICACHE_SIZE:
  36     case _SC_LEVEL1_DCACHE_SIZE:
  37       return 8 * 1024;
  38
  39     case _SC_LEVEL1_ICACHE_ASSOC:
  40     case _SC_LEVEL1_DCACHE_ASSOC:
  41       // XXX Anybody know this?
  42       return 0;
  43
  44     case _SC_LEVEL1_ICACHE_LINESIZE:
  45     case _SC_LEVEL1_DCACHE_LINESIZE:
  46       // XXX Anybody know for sure?
  47       return 16;
  48
  49     case _SC_LEVEL2_CACHE_SIZE:
  50     case _SC_LEVEL2_CACHE_ASSOC:
  51     case _SC_LEVEL2_CACHE_LINESIZE:
  52     case _SC_LEVEL3_CACHE_SIZE:
  53     case _SC_LEVEL3_CACHE_ASSOC:
  54     case _SC_LEVEL3_CACHE_LINESIZE:
  55     case _SC_LEVEL4_CACHE_SIZE:
  56     case _SC_LEVEL4_CACHE_ASSOC:
  57       /* Not available.  */
  58       break;
  59
  60     default:
  61       assert (! "cannot happen");
  62     }
  63
  64   return -1;
  65 }
  66
  67
  68 static const struct intel_02_cache_info
  69 {
  70   unsigned int idx;
  71   int name;
  72   long int size;
  73   long int assoc;
  74   long int linesize;
  75 } intel_02_known[] =
  76   {
  77     { 0x06, _SC_LEVEL1_ICACHE_SIZE, 8192, 4, 32 },
  78     { 0x08, _SC_LEVEL1_ICACHE_SIZE, 16384, 4, 32 },
  79     { 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 },
  80     { 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 },
  81     { 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
  82     { 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
  83     { 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
  84     { 0x29, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
  85     { 0x2c, _SC_LEVEL1_DCACHE_SIZE, 32768, 8, 64 },
  86     { 0x30, _SC_LEVEL1_ICACHE_SIZE, 32768, 8, 64 },
  87     { 0x39, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 64 },
  88     { 0x3a, _SC_LEVEL2_CACHE_SIZE, 196608, 6, 64 },
  89     { 0x3b, _SC_LEVEL2_CACHE_SIZE, 131072, 2, 64 },
  90     { 0x3c, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 64 },
  91     { 0x3d, _SC_LEVEL2_CACHE_SIZE, 393216, 6, 64 },
  92     { 0x3e, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
  93     { 0x41, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 32 },
  94     { 0x42, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 32 },
  95     { 0x43, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 32 },
  96     { 0x44, _SC_LEVEL2_CACHE_SIZE, 1048576, 4, 32 },
  97     { 0x45, _SC_LEVEL2_CACHE_SIZE, 2097152, 4, 32 },
  98     { 0x46, _SC_LEVEL3_CACHE_SIZE, 4194304, 4, 64 },
  99     { 0x47, _SC_LEVEL3_CACHE_SIZE, 8388608, 8, 64 },
 100     { 0x49, _SC_LEVEL3_CACHE_SIZE, 4194304, 16, 64 },
 101     { 0x4a, _SC_LEVEL3_CACHE_SIZE, 6291456, 12, 64 },
 102     { 0x4b, _SC_LEVEL3_CACHE_SIZE, 8388608, 16, 64 },
 103     { 0x4c, _SC_LEVEL3_CACHE_SIZE, 12582912, 12, 64 },
 104     { 0x4d, _SC_LEVEL3_CACHE_SIZE, 16777216, 16, 64 },
 105     { 0x60, _SC_LEVEL1_DCACHE_SIZE, 16384, 8, 64 },
 106     { 0x66, _SC_LEVEL1_DCACHE_SIZE, 8192, 4, 64 },
 107     { 0x67, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
 108     { 0x68, _SC_LEVEL1_DCACHE_SIZE, 32768, 4, 64 },
 109     { 0x78, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
 110     { 0x79, _SC_LEVEL2_CACHE_SIZE, 131072, 8, 64 },
 111     { 0x7a, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
 112     { 0x7b, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 64 },
 113     { 0x7c, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
 114     { 0x7d, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 64 },
 115     { 0x7f, _SC_LEVEL2_CACHE_SIZE, 524288, 2, 64 },
 116     { 0x82, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 32 },
 117     { 0x83, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 32 },
 118     { 0x84, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 32 },
 119     { 0x85, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 32 },
 120     { 0x86, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
 121     { 0x87, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
 122   };
 123 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
 124
 125
 126 static int
 127 intel_02_known_compare (const void *p1, const void *p2)
 128 {
 129   const struct intel_02_cache_info *i1;
 130   const struct intel_02_cache_info *i2;
 131
 132   i1 = (const struct intel_02_cache_info *) p1;
 133   i2 = (const struct intel_02_cache_info *) p2;
 134
 135   if (i1->idx == i2->idx)
 136     return 0;
 137
 138   return i1->idx < i2->idx ? -1 : 1;
 139 }
 140
 141
 142 static long int
 143 intel_check_word (int name, unsigned int value, bool *has_level_2,
 144                   bool *no_level_2_or_3)
 145 {
 146   if ((value & 0x80000000) != 0)
 147     /* The register value is reserved.  */
 148     return 0;
 149
 150   /* Fold the name.  The _SC_ constants are always in the order SIZE,
 151      ASSOC, LINESIZE.  */
 152   int folded_name = (_SC_LEVEL1_ICACHE_SIZE
 153                      + ((name - _SC_LEVEL1_ICACHE_SIZE) / 3) * 3);
 154
 155   while (value != 0)
 156     {
 157       unsigned int byte = value & 0xff;
 158
 159       if (byte == 0x40)
 160         {
 161           *no_level_2_or_3 = true;
 162
 163           if (folded_name == _SC_LEVEL3_CACHE_SIZE)
 164             /* No need to look further.  */
 165             break;
 166         }
 167       else
 168         {
 169           struct intel_02_cache_info *found;
 170           struct intel_02_cache_info search;
 171
 172           search.idx = byte;
 173           found = bsearch (&search, intel_02_known, nintel_02_known,
 174                            sizeof (intel_02_known[0]), intel_02_known_compare);
 175           if (found != NULL)
 176             {
 177               if (found->name == folded_name)
 178                 {
 179                   unsigned int offset = name - folded_name;
 180
 181                   if (offset == 0)
 182                     /* Cache size.  */
 183                     return found->size;
 184                   if (offset == 1)
 185                     return found->assoc;
 186
 187                   assert (offset == 2);
 188                   return found->linesize;
 189                 }
 190
 191               if (found->name == _SC_LEVEL2_CACHE_SIZE)
 192                 *has_level_2 = true;
 193             }
 194         }
 195
 196       /* Next byte for the next round.  */
 197       value >>= 8;
 198     }
 199
 200   /* Nothing found.  */
 201   return 0;
 202 }
 203
 204
 205 static long int  __attribute__ ((noinline))
 206 handle_intel (int name, unsigned int maxidx)
 207 {
 208   if (maxidx < 2)
 209     {
 210       // XXX Do such processors exist?  When we know we can fill in some
 211       // values.
 212       return 0;
 213     }
 214
 215   /* OK, we can use the CPUID instruction to get all info about the
 216      caches.  */
 217   unsigned int cnt = 0;
 218   unsigned int max = 1;
 219   long int result = 0;
 220   bool no_level_2_or_3 = false;
 221   bool has_level_2 = false;
 222   while (cnt++ < max)
 223     {
 224       unsigned int eax;
 225       unsigned int ebx;
 226       unsigned int ecx;
 227       unsigned int edx;
 228       asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 229                     : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 230                     : "0" (2));
 231
 232       /* The low byte of EAX in the first round contain the number of
 233          rounds we have to make.  At least one, the one we are already
 234          doing.  */
 235       if (cnt == 1)
 236         {
 237           max = eax & 0xff;
 238           eax &= 0xffffff00;
 239         }
 240
 241       /* Process the individual registers' value.  */
 242       result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
 243       if (result != 0)
 244         return result;
 245
 246       result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
 247       if (result != 0)
 248         return result;
 249
 250       result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
 251       if (result != 0)
 252         return result;
 253
 254       result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
 255       if (result != 0)
 256         return result;
 257     }
 258
 259   if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
 260       && no_level_2_or_3)
 261     return -1;
 262
 263   return 0;
 264 }
 265
 266
 267 static long int __attribute__ ((noinline))
 268 handle_amd (int name)
 269 {
 270   unsigned int eax;
 271   unsigned int ebx;
 272   unsigned int ecx;
 273   unsigned int edx;
 274   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 275                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 276                 : "0" (0x80000000));
 277
 278   if (name >= _SC_LEVEL3_CACHE_SIZE)
 279     return 0;
 280
 281   unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
 282   if (eax < fn)
 283     return 0;
 284
 285   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 286                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 287                 : "0" (fn));
 288
 289   if (name < _SC_LEVEL1_DCACHE_SIZE)
 290     {
 291       name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
 292       ecx = edx;
 293     }
 294
 295   switch (name)
 296     {
 297     case _SC_LEVEL1_DCACHE_SIZE:
 298       return (ecx >> 14) & 0x3fc00;
 299     case _SC_LEVEL1_DCACHE_ASSOC:
 300       ecx >>= 16;
 301       if ((ecx & 0xff) == 0xff)
 302         /* Fully associative.  */
 303         return (ecx << 2) & 0x3fc00;
 304       return ecx & 0xff;
 305     case _SC_LEVEL1_DCACHE_LINESIZE:
 306       return ecx & 0xff;
 307     case _SC_LEVEL2_CACHE_SIZE:
 308       return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
 309     case _SC_LEVEL2_CACHE_ASSOC:
 310       ecx >>= 12;
 311       switch (ecx & 0xf)
 312         {
 313         case 0:
 314         case 1:
 315         case 2:
 316         case 4:
 317           return ecx & 0xf;
 318         case 6:
 319           return 8;
 320         case 8:
 321           return 16;
 322         case 0xf:
 323           return (ecx << 6) & 0x3fffc00;
 324         default:
 325           return 0;
 326         }
 327     case _SC_LEVEL2_CACHE_LINESIZE:
 328       return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
 329     default:
 330       assert (! "cannot happen");
 331     }
 332   return -1;
 333 }
 334
 335
 336 static int
 337 i386_i486_test (void)
 338 {
 339   int eflags;
 340   int ac;
 341   asm volatile ("pushfl;\n\t"
 342                 "popl %0;\n\t"
 343                 "movl $0x240000, %1;\n\t"
 344                 "xorl %0, %1;\n\t"
 345                 "pushl %1;\n\t"
 346                 "popfl;\n\t"
 347                 "pushfl;\n\t"
 348                 "popl %1;\n\t"
 349                 "xorl %0, %1;\n\t"
 350                 "pushl %0;\n\t"
 351                 "popfl"
 352                 : "=r" (eflags), "=r" (ac));
 353
 354   return ac;
 355 }
 356
 357
 358 /* Get the value of the system variable NAME.  */
 359 long int
 360 __sysconf (int name)
 361 {
 362   /* All the remainder, except the cache information, is handled in
 363      the generic code.  */
 364   if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
 365     return linux_sysconf (name);
 366
 367   /* Recognize i386 and compatible.  These don't have any cache on
 368      board.  */
 369   int ac = i386_i486_test ();
 370
 371   if (ac == 0)
 372     /* This is an i386.  */
 373     // XXX Is this true for all brands?
 374     return -1;
 375
 376   /* Detect i486, the last Intel processor without CPUID.  */
 377   if ((ac & (1 << 21)) == 0)
 378     {
 379       /* No CPUID.  */
 380       // XXX Fill in info about other brands.  For now only Intel.
 381       return handle_i486 (name);
 382     }
 383
 384   /* Find out what brand of processor.  */
 385   unsigned int eax;
 386   unsigned int ebx;
 387   unsigned int ecx;
 388   unsigned int edx;
 389   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 390                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 391                 : "0" (0));
 392
 393   /* This spells out "GenuineIntel".  */
 394   if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
 395     return handle_intel (name, eax);
 396
 397   /* This spells out "AuthenticAMD".  */
 398   if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
 399     return handle_amd (name);
 400
 401   // XXX Fill in more vendors.
 402
 403   /* CPU not known, we have no information.  */
 404   return 0;
 405 }
 406
 407 /* Now the generic Linux version.  */
 408 #undef __sysconf
 409 #define __sysconf static linux_sysconf
 410 #include "../sysconf.c"