1 /* Copyright (C) 1992, 1996, 1997, 1998 Free Software Foundation, Inc.
2 This file is part of the GNU C Library.
3 Contributed by David Mosberger.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Library General Public License as
7 published by the Free Software Foundation; either version 2 of the
8 License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Library General Public License for more details.
15 You should have received a copy of the GNU Library General Public
16 License along with the GNU C Library; see the file COPYING.LIB. If not,
17 write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
20 /* I/O access is restricted to ISA port space (ports 0..65535).
21 Modern devices hopefully are sane enough not to put any performance
22 critical registers in i/o space.
24 On the first call to ioperm() or _sethae(), the entire (E)ISA port
25 space is mapped into the virtual address space at address io.base.
26 mprotect() calls are then used to enable/disable access to ports. Per
27 page, there are PAGE_SIZE>>IO_SHIFT I/O ports (e.g., 256 ports on a
28 Low Cost Alpha based system using 8KB pages).
30 Keep in mind that this code should be able to run in a 32bit address
31 space. It is therefore unreasonable to expect mmap'ing the entire
32 sparse address space would work (e.g., the Low Cost Alpha chip has an
33 I/O address space that's 512MB large!). */
43 #include <sys/types.h>
47 #include <asm/system.h>
49 #define PATH_ALPHA_SYSTYPE "/etc/alpha_systype"
50 #define PATH_CPUINFO "/proc/cpuinfo"
52 #define MAX_PORT 0x10000
53 #define vuip volatile unsigned int *
55 #define JENSEN_IO_BASE (0xfffffc0300000000UL)
56 #define JENSEN_SPARSE_MEM (0xfffffc0200000000UL)
58 /* With respect to the I/O architecture, APECS and LCA are identical,
59 so the following defines apply to LCA as well. */
60 #define APECS_IO_BASE (0xfffffc01c0000000UL)
61 #define APECS_SPARSE_MEM (0xfffffc0200000000UL)
62 #define APECS_DENSE_MEM (0xfffffc0300000000UL)
64 /* The same holds for CIA and PYXIS. */
65 #define CIA_IO_BASE (0xfffffc8580000000UL)
66 #define CIA_SPARSE_MEM (0xfffffc8000000000UL)
67 #define CIA_DENSE_MEM (0xfffffc8600000000UL)
69 /* SABLE is EV4, GAMMA is EV5 */
70 #define T2_IO_BASE (0xfffffc03a0000000UL)
71 #define T2_SPARSE_MEM (0xfffffc0200000000UL)
72 #define T2_DENSE_MEM (0xfffffc03c0000000UL)
74 #define GAMMA_IO_BASE (0xfffffc83a0000000UL)
75 #define GAMMA_SPARSE_MEM (0xfffffc8200000000UL)
76 #define GAMMA_DENSE_MEM (0xfffffc83c0000000UL)
78 /* these are for the RAWHIDE family */
79 #define MCPCIA_IO_BASE (0xfffffcf980000000UL)
80 #define MCPCIA_SPARSE_MEM (0xfffffcf800000000UL)
81 #define MCPCIA_DENSE_MEM (0xfffffcf900000000UL)
83 /* Tsunami has no SPARSE space */
84 /* NOTE: these are hardwired to PCI bus 0 addresses!!! */
85 /* Also, these are PHYSICAL, as/so there's no KSEG translation */
86 #define TSUNAMI_IO_BASE (0x00000801fc000000UL + 0xfffffc0000000000UL)
87 #define TSUNAMI_DENSE_MEM (0x0000080000000000UL + 0xfffffc0000000000UL)
90 IOSYS_UNKNOWN
, IOSYS_JENSEN
, IOSYS_APECS
, IOSYS_CIA
, IOSYS_T2
,
91 IOSYS_TSUNAMI
, IOSYS_MCPCIA
, IOSYS_GAMMA
, IOSYS_CPUDEP
94 static struct io_system
{
96 unsigned long int bus_memory_base
;
97 unsigned long int sparse_bus_mem_base
;
98 unsigned long int bus_io_base
;
99 } io_system
[] = { /* NOTE! must match iosys_t enumeration */
100 /* UNKNOWN */ {0, 0, 0, 0},
101 /* JENSEN */ {7, 0, JENSEN_SPARSE_MEM
, JENSEN_IO_BASE
},
102 /* APECS */ {5, APECS_DENSE_MEM
, APECS_SPARSE_MEM
, APECS_IO_BASE
},
103 /* CIA */ {5, CIA_DENSE_MEM
, CIA_SPARSE_MEM
, CIA_IO_BASE
},
104 /* T2 */ {5, T2_DENSE_MEM
, T2_SPARSE_MEM
, T2_IO_BASE
},
105 /* TSUNAMI */ {0, TSUNAMI_DENSE_MEM
, 0, TSUNAMI_IO_BASE
},
106 /* MCPCIA */ {5, MCPCIA_DENSE_MEM
, MCPCIA_SPARSE_MEM
, MCPCIA_IO_BASE
},
107 /* GAMMA */ {5, GAMMA_DENSE_MEM
, GAMMA_SPARSE_MEM
, GAMMA_IO_BASE
},
108 /* CPUDEP */ {0, 0, 0, 0},
111 static struct platform
{
115 {"Alcor", IOSYS_CIA
},
116 {"Avanti", IOSYS_APECS
},
118 {"Cabriolet", IOSYS_APECS
},
119 {"EB164", IOSYS_CIA
},
120 {"EB64+", IOSYS_APECS
},
121 {"EB66", IOSYS_APECS
},
122 {"EB66P", IOSYS_APECS
},
123 {"Jensen", IOSYS_JENSEN
},
124 {"Mikasa", IOSYS_CPUDEP
},
125 {"Noritake", IOSYS_CPUDEP
},
126 {"Noname", IOSYS_APECS
},
127 {"Sable", IOSYS_CPUDEP
},
128 {"Miata", IOSYS_CIA
},
129 {"Tsunami", IOSYS_TSUNAMI
},
130 {"Rawhide", IOSYS_MCPCIA
},
131 {"Ruffian", IOSYS_CIA
},
132 {"Takara", IOSYS_CIA
},
136 void (*sethae
)(unsigned long int addr
);
137 void (*outb
)(unsigned char b
, unsigned long int port
);
138 void (*outw
)(unsigned short b
, unsigned long int port
);
139 void (*outl
)(unsigned int b
, unsigned long int port
);
140 unsigned int (*inb
)(unsigned long int port
);
141 unsigned int (*inw
)(unsigned long int port
);
142 unsigned int (*inl
)(unsigned long int port
);
147 unsigned long int cache
;
148 unsigned long int * reg
;
150 unsigned long int base
;
151 struct ioswtch
* swp
;
152 unsigned long int bus_memory_base
;
153 unsigned long int sparse_bus_memory_base
;
154 unsigned long int io_base
;
159 extern void __sethae (unsigned long int); /* we can't use asm/io.h */
162 static inline unsigned long int
163 port_to_cpu_addr (unsigned long int port
, iosys_t iosys
, int size
)
165 if (iosys
== IOSYS_JENSEN
)
166 return (port
<< 7) + ((size
- 1) << 5) + io
.base
;
167 else if (iosys
== IOSYS_TSUNAMI
)
168 return port
+ io
.base
;
170 return (port
<< 5) + ((size
- 1) << 3) + io
.base
;
175 inline_sethae (unsigned long int addr
, iosys_t iosys
)
177 if (iosys
== IOSYS_JENSEN
)
179 /* hae on the Jensen is bits 31:25 shifted right */
181 if (addr
!= io
.hae
.cache
)
189 unsigned long int msb
;
191 /* no need to set hae if msb is 0: */
192 msb
= addr
& 0xf8000000;
193 if (msb
&& msb
!= io
.hae
.cache
)
203 inline_outb (unsigned char b
, unsigned long int port
, iosys_t iosys
)
206 unsigned long int addr
= port_to_cpu_addr (port
, iosys
, 1);
208 inline_sethae (0, iosys
);
209 asm ("insbl %2,%1,%0" : "=r" (w
) : "ri" (port
& 0x3), "r" (b
));
216 inline_outw (unsigned short int b
, unsigned long int port
, iosys_t iosys
)
219 unsigned long int addr
= port_to_cpu_addr (port
, iosys
, 2);
221 inline_sethae (0, iosys
);
222 asm ("inswl %2,%1,%0" : "=r" (w
) : "ri" (port
& 0x3), "r" (b
));
229 inline_outl (unsigned int b
, unsigned long int port
, iosys_t iosys
)
231 unsigned long int addr
= port_to_cpu_addr (port
, iosys
, 4);
233 inline_sethae (0, iosys
);
239 static inline unsigned int
240 inline_inb (unsigned long int port
, iosys_t iosys
)
242 unsigned long int result
, addr
= port_to_cpu_addr (port
, iosys
, 1);
244 inline_sethae (0, iosys
);
245 result
= *(vuip
) addr
;
246 result
>>= (port
& 3) * 8;
247 return 0xffUL
& result
;
251 static inline unsigned int
252 inline_inw (unsigned long int port
, iosys_t iosys
)
254 unsigned long int result
, addr
= port_to_cpu_addr (port
, iosys
, 2);
256 inline_sethae (0, iosys
);
257 result
= *(vuip
) addr
;
258 result
>>= (port
& 3) * 8;
259 return 0xffffUL
& result
;
263 static inline unsigned int
264 inline_inl (unsigned long int port
, iosys_t iosys
)
266 unsigned long int addr
= port_to_cpu_addr (port
, iosys
, 4);
268 inline_sethae (0, iosys
);
273 * Now define the inline functions for CPUs supporting byte/word insns,
274 * and whose core logic supports I/O space accesses utilizing them.
276 * These routines could be used by MIATA, for example, because it has
277 * and EV56 plus PYXIS, but it currently uses SPARSE anyway.
279 * These routines are necessary for TSUNAMI/TYPHOON based platforms,
280 * which will have (at least) EV6.
284 inline_bwx_outb (unsigned char b
, unsigned long int port
, iosys_t iosys
)
286 unsigned long int addr
= port_to_cpu_addr (port
, iosys
, 4);
288 __asm__
__volatile__ ("stb %1,%0" : : "m"(*(unsigned char *)addr
), "r"(b
));
294 inline_bwx_outw (unsigned short int b
, unsigned long int port
, iosys_t iosys
)
296 unsigned long int addr
= port_to_cpu_addr (port
, iosys
, 4);
298 __asm__
__volatile__ ("stw %1,%0" : : "m"(*(unsigned short *)addr
), "r"(b
));
304 inline_bwx_outl (unsigned int b
, unsigned long int port
, iosys_t iosys
)
306 unsigned long int addr
= port_to_cpu_addr (port
, iosys
, 4);
313 static inline unsigned int
314 inline_bwx_inb (unsigned long int port
, iosys_t iosys
)
316 unsigned long int r
, addr
= port_to_cpu_addr (port
, iosys
, 1);
318 __asm__
__volatile__ ("ldbu %0,%1" : "=r"(r
) : "m"(*(unsigned char *)addr
));
323 static inline unsigned int
324 inline_bwx_inw (unsigned long int port
, iosys_t iosys
)
326 unsigned long int r
, addr
= port_to_cpu_addr (port
, iosys
, 1);
328 __asm__
__volatile__ ("ldwu %0,%1" : "=r"(r
) : "m"(*(unsigned short *)addr
));
333 static inline unsigned int
334 inline_bwx_inl (unsigned long int port
, iosys_t iosys
)
336 unsigned long int addr
= port_to_cpu_addr (port
, iosys
, 4);
342 #define DCL_SETHAE(name, iosys) \
344 name##_sethae (unsigned long int addr) \
346 inline_sethae (addr, IOSYS_##iosys); \
349 #define DCL_OUT(name, func, type, iosys) \
351 name##_##func (unsigned type b, unsigned long int addr) \
353 inline_##func (b, addr, IOSYS_##iosys); \
357 #define DCL_IN(name, func, iosys) \
358 static unsigned int \
359 name##_##func (unsigned long int addr) \
361 return inline_##func (addr, IOSYS_##iosys); \
364 #define DCL_SETHAE_IGNORE(name, iosys) \
366 name##_sethae (unsigned long int addr) \
371 #define DCL_OUT_BWX(name, func, type, iosys) \
373 name##_##func (unsigned type b, unsigned long int addr) \
375 inline_bwx_##func (b, addr, IOSYS_##iosys); \
379 #define DCL_IN_BWX(name, func, iosys) \
380 static unsigned int \
381 name##_##func (unsigned long int addr) \
383 return inline_bwx_##func (addr, IOSYS_##iosys); \
387 DCL_SETHAE(jensen
, JENSEN
)
388 DCL_OUT(jensen
, outb
, char, JENSEN
)
389 DCL_OUT(jensen
, outw
, short int, JENSEN
)
390 DCL_OUT(jensen
, outl
, int, JENSEN
)
391 DCL_IN(jensen
, inb
, JENSEN
)
392 DCL_IN(jensen
, inw
, JENSEN
)
393 DCL_IN(jensen
, inl
, JENSEN
)
395 /* The APECS functions are also used for CIA since they are
398 DCL_SETHAE(apecs
, APECS
)
399 DCL_OUT(apecs
, outb
, char, APECS
)
400 DCL_OUT(apecs
, outw
, short int, APECS
)
401 DCL_OUT(apecs
, outl
, int, APECS
)
402 DCL_IN(apecs
, inb
, APECS
)
403 DCL_IN(apecs
, inw
, APECS
)
404 DCL_IN(apecs
, inl
, APECS
)
406 DCL_SETHAE_IGNORE(tsunami
, TSUNAMI
)
407 DCL_OUT_BWX(tsunami
, outb
, char, TSUNAMI
)
408 DCL_OUT_BWX(tsunami
, outw
, short int, TSUNAMI
)
409 DCL_OUT_BWX(tsunami
, outl
, int, TSUNAMI
)
410 DCL_IN_BWX(tsunami
, inb
, TSUNAMI
)
411 DCL_IN_BWX(tsunami
, inw
, TSUNAMI
)
412 DCL_IN_BWX(tsunami
, inl
, TSUNAMI
)
414 static struct ioswtch ioswtch
[] = {
417 jensen_outb
, jensen_outw
, jensen_outl
,
418 jensen_inb
, jensen_inw
, jensen_inl
422 apecs_outb
, apecs_outw
, apecs_outl
,
423 apecs_inb
, apecs_inw
, apecs_inl
427 tsunami_outb
, tsunami_outw
, tsunami_outl
,
428 tsunami_inb
, tsunami_inw
, tsunami_inl
434 * Initialize I/O system. To determine what I/O system we're dealing
435 * with, we first try to read the value of symlink PATH_ALPHA_SYSTYPE,
436 * if that fails, we lookup the "system type" field in /proc/cpuinfo.
437 * If that fails as well, we give up.
439 * If the value received from PATH_ALPHA_SYSTYPE begins with a number,
440 * assume this is a previously unsupported system and the values encode,
441 * in order, "<io_base>,<hae_shift>,<dense_base>,<sparse_base>".
449 n
= readlink (PATH_ALPHA_SYSTYPE
, systype
, sizeof (systype
) - 1);
453 if (isdigit (systype
[0]))
455 if (sscanf (systype
, "%li,%i,%li,%li", &io
.io_base
, &io
.hae_shift
,
456 &io
.bus_memory_base
, &io
.sparse_bus_memory_base
) == 4)
458 io
.sys
= IOSYS_UNKNOWN
;
459 io
.swp
= &ioswtch
[1];
462 /* else we're likely going to fail with the system match below */
469 fp
= fopen (PATH_CPUINFO
, "r");
472 while ((n
= fscanf (fp
, "system type : %256[^\n]\n", systype
))
478 fgets (systype
, 256, fp
);
484 /* this can happen if the format of /proc/cpuinfo changes... */
486 "ioperm.init_iosys(): Unable to determine system type.\n"
487 "\t(May need " PATH_ALPHA_SYSTYPE
" symlink?)\n");
488 __set_errno (ENODEV
);
493 /* translate systype name into i/o system: */
494 for (i
= 0; i
< sizeof (platform
) / sizeof (platform
[0]); ++i
)
496 if (strcmp (platform
[i
].name
, systype
) == 0)
498 io
.sys
= platform
[i
].io_sys
;
499 /* some platforms can have either EV4 or EV5 CPUs */
500 if (io
.sys
== IOSYS_CPUDEP
)
504 fp
= fopen (PATH_CPUINFO
, "r");
507 while ((n
= fscanf (fp
, "cpu model : %256[^\n]\n", cputype
))
510 fgets (cputype
, 256, fp
);
514 if (strcmp (platform
[i
].name
, "Sable") == 0)
516 if (strncmp (cputype
, "EV4", 3) == 0)
518 else if (strncmp (cputype
, "EV5", 3) == 0)
519 io
.sys
= IOSYS_GAMMA
;
523 if (strncmp (cputype
, "EV4", 3) == 0)
524 io
.sys
= IOSYS_APECS
;
525 else if (strncmp (cputype
, "EV5", 3) == 0)
528 if (n
== EOF
|| io
.sys
== IOSYS_CPUDEP
)
530 /* This can happen if the format of /proc/cpuinfo changes.*/
531 fprintf (stderr
, "ioperm.init_iosys(): Unable to determine"
533 __set_errno (ENODEV
);
537 io
.hae_shift
= io_system
[io
.sys
].hae_shift
;
538 io
.bus_memory_base
= io_system
[io
.sys
].bus_memory_base
;
539 io
.sparse_bus_memory_base
= io_system
[io
.sys
].sparse_bus_mem_base
;
540 io
.io_base
= io_system
[io
.sys
].bus_io_base
;
542 if (io
.sys
== IOSYS_JENSEN
)
543 io
.swp
= &ioswtch
[0];
544 else if (io
.sys
== IOSYS_TSUNAMI
)
545 io
.swp
= &ioswtch
[2];
547 io
.swp
= &ioswtch
[1];
552 /* systype is not a know platform name... */
553 __set_errno (EINVAL
);
559 _ioperm (unsigned long int from
, unsigned long int num
, int turn_on
)
561 unsigned long int addr
, len
;
564 if (!io
.swp
&& init_iosys () < 0)
567 /* this test isn't as silly as it may look like; consider overflows! */
568 if (from
>= MAX_PORT
|| from
+ num
> MAX_PORT
)
570 __set_errno (EINVAL
);
580 io
.hae
.reg
= 0; /* not used in user-level */
582 if (io
.sys
!= IOSYS_TSUNAMI
)
583 __sethae (io
.hae
.cache
); /* synchronize with hw */
585 fd
= open ("/dev/mem", O_RDWR
);
589 addr
= port_to_cpu_addr (0, io
.sys
, 1);
590 len
= port_to_cpu_addr (MAX_PORT
, io
.sys
, 1) - addr
;
592 (unsigned long int) __mmap (0, len
, PROT_NONE
, MAP_SHARED
,
595 if ((long) io
.base
== -1)
598 prot
= PROT_READ
| PROT_WRITE
;
603 return 0; /* never was turned on... */
605 /* turnoff access to relevant pages: */
608 addr
= port_to_cpu_addr (from
, io
.sys
, 1);
610 len
= port_to_cpu_addr (from
+ num
, io
.sys
, 1) - addr
;
611 return mprotect ((void *) addr
, len
, prot
);
616 _iopl (unsigned int level
)
620 __set_errno (EINVAL
);
625 return _ioperm (0, MAX_PORT
, 1);
632 _sethae (unsigned long int addr
)
634 if (!io
.swp
&& init_iosys () < 0)
637 io
.swp
->sethae (addr
);
642 _outb (unsigned char b
, unsigned long int port
)
644 if (port
>= MAX_PORT
)
647 io
.swp
->outb (b
, port
);
652 _outw (unsigned short b
, unsigned long int port
)
654 if (port
>= MAX_PORT
)
657 io
.swp
->outw (b
, port
);
662 _outl (unsigned int b
, unsigned long int port
)
664 if (port
>= MAX_PORT
)
667 io
.swp
->outl (b
, port
);
672 _inb (unsigned long int port
)
674 return io
.swp
->inb (port
);
679 _inw (unsigned long int port
)
681 return io
.swp
->inw (port
);
686 _inl (unsigned long int port
)
688 return io
.swp
->inl (port
);
695 if (!io
.swp
&& init_iosys () < 0)
697 return io
.bus_memory_base
;
701 _bus_base_sparse(void)
703 if (!io
.swp
&& init_iosys () < 0)
705 return io
.sparse_bus_memory_base
;
711 if (!io
.swp
&& init_iosys () < 0)
716 weak_alias (_sethae
, sethae
);
717 weak_alias (_ioperm
, ioperm
);
718 weak_alias (_iopl
, iopl
);
719 weak_alias (_inb
, inb
);
720 weak_alias (_inw
, inw
);
721 weak_alias (_inl
, inl
);
722 weak_alias (_outb
, outb
);
723 weak_alias (_outw
, outw
);
724 weak_alias (_outl
, outl
);
725 weak_alias (_bus_base
, bus_base
);
726 weak_alias (_bus_base_sparse
, bus_base_sparse
);
727 weak_alias (_hae_shift
, hae_shift
);