sysdeps/arm/fpu_control.h

   1 /* FPU control word definitions.  ARM version.
   2    Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Library General Public License as
   7    published by the Free Software Foundation; either version 2 of the
   8    License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Library General Public License for more details.
  14
  15    You should have received a copy of the GNU Library General Public
  16    License along with the GNU C Library; see the file COPYING.LIB.  If not,
  17    write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  18    Boston, MA 02111-1307, USA.  */
  19
  20 #ifndef _FPU_CONTROL_H
  21 #define _FPU_CONTROL_H
  22
  23 /* We have a slight terminology confusion here.  On the ARM, the register
  24  * we're interested in is actually the FPU status word - the FPU control
  25  * word is something different (which is implementation-defined and only
  26  * accessible from supervisor mode.)
  27  *
  28  * The FPSR looks like this:
  29  *
  30  *     31-24        23-16          15-8              7-0
  31  * | system ID | trap enable | system control | exception flags |
  32  *
  33  * We ignore the system ID bits; for interest's sake they are:
  34  *
  35  *  0000        "old" FPE
  36  *  1000        FPPC hardware
  37  *  0001        FPE 400
  38  *  1001        FPA hardware
  39  *
  40  * The trap enable and exception flags are both structured like this:
  41  *
  42  *     7 - 5     4     3     2     1     0
  43  * | reserved | INX | UFL | OFL | DVZ | IVO |
  44  *
  45  * where a `1' bit in the enable byte means that the trap can occur, and
  46  * a `1' bit in the flags byte means the exception has occurred.
  47  *
  48  * The exceptions are:
  49  *
  50  *  IVO - invalid operation
  51  *  DVZ - divide by zero
  52  *  OFL - overflow
  53  *  UFL - underflow
  54  *  INX - inexact (do not use; implementations differ)
  55  *
  56  * The system control byte looks like this:
  57  *
  58  *     7-5      4    3    2    1    0
  59  * | reserved | AC | EP | SO | NE | ND |
  60  *
  61  * where the bits mean
  62  *
  63  *  ND - no denormalised numbers (force them all to zero)
  64  *  NE - enable NaN exceptions
  65  *  SO - synchronous operation
  66  *  EP - use expanded packed-decimal format
  67  *  AC - use alternate definition for C flag on compare operations
  68  */
  69
  70 #define _FPU_RESERVED 0xfff0e0f0  /* These bits are reserved.  */
  71
  72 /* The fdlibm code requires no interrupts for exceptions.  Don't
  73    change the rounding mode, it would break long double I/O!  */
  74 #define _FPU_DEFAULT  0x00000000 /* Default value.  */
  75
  76 /* Type of the control word.  */
  77 typedef unsigned int fpu_control_t;
  78
  79 /* Macros for accessing the hardware control word.  */
  80 #define _FPU_GETCW(cw) __asm__ ("rfs %0" : "=r" (cw))
  81 #define _FPU_SETCW(cw) __asm__ ("wfs %0" : : "r" (cw))
  82
  83 /* Default control word set at startup.  */
  84 extern fpu_control_t __fpu_control;
  85
  86 __BEGIN_DECLS
  87
  88 /* Called at startup.  It can be used to manipulate fpu control register.  */
  89 extern void __setfpucw __P ((fpu_control_t));
  90
  91 __END_DECLS
  92
  93 #endif /* _FPU_CONTROL_H */