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[glibc.git] / stdlib / longlong.h
blob540ede08ec23ab67874024098c3d439e1137aa98
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991,92,94,95,96,97,98,99,2000,2001 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, write to the Free
17 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
18 02111-1307 USA. */
19
20 /* You have to define the following before including this file:
21
22 UWtype -- An unsigned type, default type for operations (typically a "word")
23 UHWtype -- An unsigned type, at least half the size of UWtype.
24 UDWtype -- An unsigned type, at least twice as large a UWtype
25 W_TYPE_SIZE -- size in bits of UWtype
26
27 UQItype -- Unsigned 8 bit type.
28 SItype, USItype -- Signed and unsigned 32 bit types.
29 DItype, UDItype -- Signed and unsigned 64 bit types.
30
31 On a 32 bit machine UWtype should typically be USItype;
32 on a 64 bit machine, UWtype should typically be UDItype.
33 */
34
35 #define __BITS4 (W_TYPE_SIZE / 4)
36 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
37 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
38 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
39
40 #ifndef W_TYPE_SIZE
41 #define W_TYPE_SIZE 32
42 #define UWtype USItype
43 #define UHWtype USItype
44 #define UDWtype UDItype
45 #endif
46
47 /* Define auxiliary asm macros.
48
49 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
50 UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
51 word product in HIGH_PROD and LOW_PROD.
52
53 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
54 UDWtype product. This is just a variant of umul_ppmm.
55
56 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
57 denominator) divides a UDWtype, composed by the UWtype integers
58 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
59 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
60 than DENOMINATOR for correct operation. If, in addition, the most
61 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
62 UDIV_NEEDS_NORMALIZATION is defined to 1.
63
64 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
65 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
66 is rounded towards 0.
67
68 5) count_leading_zeros(count, x) counts the number of zero-bits from the
69 msb to the first non-zero bit in the UWtype X. This is the number of
70 steps X needs to be shifted left to set the msb. Undefined for X == 0,
71 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
72
73 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
74 from the least significant end.
75
76 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
77 high_addend_2, low_addend_2) adds two UWtype integers, composed by
78 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
79 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
80 (i.e. carry out) is not stored anywhere, and is lost.
81
82 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
83 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
84 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
85 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
86 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
87 and is lost.
88
89 If any of these macros are left undefined for a particular CPU,
90 C macros are used. */
91
92 /* The CPUs come in alphabetical order below.
93
94 Please add support for more CPUs here, or improve the current support
95 for the CPUs below!
96 (E.g. WE32100, IBM360.) */
97
98 #if defined (__GNUC__) && !defined (NO_ASM)
99
100 /* We sometimes need to clobber "cc" with gcc2, but that would not be
101 understood by gcc1. Use cpp to avoid major code duplication. */
102 #if __GNUC__ < 2
103 #define __CLOBBER_CC
104 #define __AND_CLOBBER_CC
105 #else /* __GNUC__ >= 2 */
106 #define __CLOBBER_CC : "cc"
107 #define __AND_CLOBBER_CC , "cc"
108 #endif /* __GNUC__ < 2 */
109
110 #if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
111 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
112 __asm__ ("add %1,%4,%5\n" \
113 "addc %0,%2,%3" \
114 : "=r" ((USItype) (sh)), \
115 "=&r" ((USItype) (sl)) \
116 : "%r" ((USItype) (ah)), \
117 "rI" ((USItype) (bh)), \
118 "%r" ((USItype) (al)), \
119 "rI" ((USItype) (bl)))
120 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
121 __asm__ ("sub %1,%4,%5\n" \
122 "subc %0,%2,%3" \
123 : "=r" ((USItype) (sh)), \
124 "=&r" ((USItype) (sl)) \
125 : "r" ((USItype) (ah)), \
126 "rI" ((USItype) (bh)), \
127 "r" ((USItype) (al)), \
128 "rI" ((USItype) (bl)))
129 #define umul_ppmm(xh, xl, m0, m1) \
130 do { \
131 USItype __m0 = (m0), __m1 = (m1); \
132 __asm__ ("multiplu %0,%1,%2" \
133 : "=r" ((USItype) (xl)) \
134 : "r" (__m0), \
135 "r" (__m1)); \
136 __asm__ ("multmu %0,%1,%2" \
137 : "=r" ((USItype) (xh)) \
138 : "r" (__m0), \
139 "r" (__m1)); \
140 } while (0)
141 #define udiv_qrnnd(q, r, n1, n0, d) \
142 __asm__ ("dividu %0,%3,%4" \
143 : "=r" ((USItype) (q)), \
144 "=q" ((USItype) (r)) \
145 : "1" ((USItype) (n1)), \
146 "r" ((USItype) (n0)), \
147 "r" ((USItype) (d)))
148 #define count_leading_zeros(count, x) \
149 __asm__ ("clz %0,%1" \
150 : "=r" ((USItype) (count)) \
151 : "r" ((USItype) (x)))
152 #define COUNT_LEADING_ZEROS_0 32
153 #endif /* __a29k__ */
154
155 #if defined (__alpha) && W_TYPE_SIZE == 64
156 #define umul_ppmm(ph, pl, m0, m1) \
157 do { \
158 UDItype __m0 = (m0), __m1 = (m1); \
159 __asm__ ("umulh %r1,%2,%0" \
160 : "=r" ((UDItype) ph) \
161 : "%rJ" (__m0), \
162 "rI" (__m1)); \
163 (pl) = __m0 * __m1; \
164 } while (0)
165 #define UMUL_TIME 46
166 #ifndef LONGLONG_STANDALONE
167 #define udiv_qrnnd(q, r, n1, n0, d) \
168 do { UDItype __r; \
169 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
170 (r) = __r; \
171 } while (0)
172 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
173 #define UDIV_TIME 220
174 #endif /* LONGLONG_STANDALONE */
175 #endif /* __alpha */
176
177 #if defined (__arc__) && W_TYPE_SIZE == 32
178 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
179 __asm__ ("add.f %1, %4, %5\n" \
180 "adc %0, %2, %3" \
181 : "=r" ((USItype) (sh)), \
182 "=&r" ((USItype) (sl)) \
183 : "%r" ((USItype) (ah)), \
184 "rIJ" ((USItype) (bh)), \
185 "%r" ((USItype) (al)), \
186 "rIJ" ((USItype) (bl)))
187 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
188 __asm__ ("sub.f %1, %4, %5\n" \
189 "sbc %0, %2, %3" \
190 : "=r" ((USItype) (sh)), \
191 "=&r" ((USItype) (sl)) \
192 : "r" ((USItype) (ah)), \
193 "rIJ" ((USItype) (bh)), \
194 "r" ((USItype) (al)), \
195 "rIJ" ((USItype) (bl)))
196 /* Call libgcc1 routine. */
197 #define umul_ppmm(w1, w0, u, v) \
198 do { \
199 DIunion __w; \
200 __w.ll = __umulsidi3 (u, v); \
201 w1 = __w.s.high; \
202 w0 = __w.s.low; \
203 } while (0)
204 #define __umulsidi3 __umulsidi3
205 UDItype __umulsidi3 (USItype, USItype);
206 #endif
207
208 #if defined (__arm__) && W_TYPE_SIZE == 32
209 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
210 __asm__ ("adds %1, %4, %5\n" \
211 "adc %0, %2, %3" \
212 : "=r" ((USItype) (sh)), \
213 "=&r" ((USItype) (sl)) \
214 : "%r" ((USItype) (ah)), \
215 "rI" ((USItype) (bh)), \
216 "%r" ((USItype) (al)), \
217 "rI" ((USItype) (bl)))
218 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
219 __asm__ ("subs %1, %4, %5\n" \
220 "sbc %0, %2, %3" \
221 : "=r" ((USItype) (sh)), \
222 "=&r" ((USItype) (sl)) \
223 : "r" ((USItype) (ah)), \
224 "rI" ((USItype) (bh)), \
225 "r" ((USItype) (al)), \
226 "rI" ((USItype) (bl)))
227 #define umul_ppmm(xh, xl, a, b) \
228 {register USItype __t0, __t1, __t2; \
229 __asm__ ("%@ Inlined umul_ppmm\n" \
230 "mov %2, %5, lsr #16\n" \
231 "mov %0, %6, lsr #16\n" \
232 "bic %3, %5, %2, lsl #16\n" \
233 "bic %4, %6, %0, lsl #16\n" \
234 "mul %1, %3, %4\n" \
235 "mul %4, %2, %4\n" \
236 "mul %3, %0, %3\n" \
237 "mul %0, %2, %0\n" \
238 "adds %3, %4, %3\n" \
239 "addcs %0, %0, #65536\n" \
240 "adds %1, %1, %3, lsl #16\n" \
241 "adc %0, %0, %3, lsr #16" \
242 : "=&r" ((USItype) (xh)), \
243 "=r" ((USItype) (xl)), \
244 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
245 : "r" ((USItype) (a)), \
246 "r" ((USItype) (b)));}
247 #define UMUL_TIME 20
248 #define UDIV_TIME 100
249 #endif /* __arm__ */
250
251 #if defined (__clipper__) && W_TYPE_SIZE == 32
252 #define umul_ppmm(w1, w0, u, v) \
253 ({union {UDItype __ll; \
254 struct {USItype __l, __h;} __i; \
255 } __xx; \
256 __asm__ ("mulwux %2,%0" \
257 : "=r" (__xx.__ll) \
258 : "%0" ((USItype) (u)), \
259 "r" ((USItype) (v))); \
260 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
261 #define smul_ppmm(w1, w0, u, v) \
262 ({union {DItype __ll; \
263 struct {SItype __l, __h;} __i; \
264 } __xx; \
265 __asm__ ("mulwx %2,%0" \
266 : "=r" (__xx.__ll) \
267 : "%0" ((SItype) (u)), \
268 "r" ((SItype) (v))); \
269 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
270 #define __umulsidi3(u, v) \
271 ({UDItype __w; \
272 __asm__ ("mulwux %2,%0" \
273 : "=r" (__w) \
274 : "%0" ((USItype) (u)), \
275 "r" ((USItype) (v))); \
276 __w; })
277 #endif /* __clipper__ */
278
279 #if defined (__gmicro__) && W_TYPE_SIZE == 32
280 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
281 __asm__ ("add.w %5,%1\n" \
282 "addx %3,%0" \
283 : "=g" ((USItype) (sh)), \
284 "=&g" ((USItype) (sl)) \
285 : "%0" ((USItype) (ah)), \
286 "g" ((USItype) (bh)), \
287 "%1" ((USItype) (al)), \
288 "g" ((USItype) (bl)))
289 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
290 __asm__ ("sub.w %5,%1\n" \
291 "subx %3,%0" \
292 : "=g" ((USItype) (sh)), \
293 "=&g" ((USItype) (sl)) \
294 : "0" ((USItype) (ah)), \
295 "g" ((USItype) (bh)), \
296 "1" ((USItype) (al)), \
297 "g" ((USItype) (bl)))
298 #define umul_ppmm(ph, pl, m0, m1) \
299 __asm__ ("mulx %3,%0,%1" \
300 : "=g" ((USItype) (ph)), \
301 "=r" ((USItype) (pl)) \
302 : "%0" ((USItype) (m0)), \
303 "g" ((USItype) (m1)))
304 #define udiv_qrnnd(q, r, nh, nl, d) \
305 __asm__ ("divx %4,%0,%1" \
306 : "=g" ((USItype) (q)), \
307 "=r" ((USItype) (r)) \
308 : "1" ((USItype) (nh)), \
309 "0" ((USItype) (nl)), \
310 "g" ((USItype) (d)))
311 #define count_leading_zeros(count, x) \
312 __asm__ ("bsch/1 %1,%0" \
313 : "=g" (count) \
314 : "g" ((USItype) (x)), \
315 "0" ((USItype) 0))
316 #endif
317
318 #if defined (__hppa) && W_TYPE_SIZE == 32
319 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
320 __asm__ ("add %4,%5,%1\n" \
321 "addc %2,%3,%0" \
322 : "=r" ((USItype) (sh)), \
323 "=&r" ((USItype) (sl)) \
324 : "%rM" ((USItype) (ah)), \
325 "rM" ((USItype) (bh)), \
326 "%rM" ((USItype) (al)), \
327 "rM" ((USItype) (bl)))
328 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
329 __asm__ ("sub %4,%5,%1\n" \
330 "subb %2,%3,%0" \
331 : "=r" ((USItype) (sh)), \
332 "=&r" ((USItype) (sl)) \
333 : "rM" ((USItype) (ah)), \
334 "rM" ((USItype) (bh)), \
335 "rM" ((USItype) (al)), \
336 "rM" ((USItype) (bl)))
337 #if defined (_PA_RISC1_1)
338 #define umul_ppmm(w1, w0, u, v) \
339 do { \
340 union \
341 { \
342 UDItype __f; \
343 struct {USItype __w1, __w0;} __w1w0; \
344 } __t; \
345 __asm__ ("xmpyu %1,%2,%0" \
346 : "=x" (__t.__f) \
347 : "x" ((USItype) (u)), \
348 "x" ((USItype) (v))); \
349 (w1) = __t.__w1w0.__w1; \
350 (w0) = __t.__w1w0.__w0; \
351 } while (0)
352 #define UMUL_TIME 8
353 #else
354 #define UMUL_TIME 30
355 #endif
356 #define UDIV_TIME 40
357 #define count_leading_zeros(count, x) \
358 do { \
359 USItype __tmp; \
360 __asm__ ( \
361 "ldi 1,%0\n" \
362 "extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
363 "extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n" \
364 "ldo 16(%0),%0 ; Yes. Perform add.\n" \
365 "extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
366 "extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n" \
367 "ldo 8(%0),%0 ; Yes. Perform add.\n" \
368 "extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
369 "extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n" \
370 "ldo 4(%0),%0 ; Yes. Perform add.\n" \
371 "extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
372 "extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n" \
373 "ldo 2(%0),%0 ; Yes. Perform add.\n" \
374 "extru %1,30,1,%1 ; Extract bit 1.\n" \
375 "sub %0,%1,%0 ; Subtract it." \
376 : "=r" (count), "=r" (__tmp) : "1" (x)); \
377 } while (0)
378 #endif
379
380 #if (defined (__i370__) || defined (__mvs__)) && W_TYPE_SIZE == 32
381 #define umul_ppmm(xh, xl, m0, m1) \
382 do { \
383 union {UDItype __ll; \
384 struct {USItype __h, __l;} __i; \
385 } __xx; \
386 USItype __m0 = (m0), __m1 = (m1); \
387 __asm__ ("mr %0,%3" \
388 : "=r" (__xx.__i.__h), \
389 "=r" (__xx.__i.__l) \
390 : "%1" (__m0), \
391 "r" (__m1)); \
392 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
393 (xh) += ((((SItype) __m0 >> 31) & __m1) \
394 + (((SItype) __m1 >> 31) & __m0)); \
395 } while (0)
396 #define smul_ppmm(xh, xl, m0, m1) \
397 do { \
398 union {DItype __ll; \
399 struct {USItype __h, __l;} __i; \
400 } __xx; \
401 __asm__ ("mr %0,%3" \
402 : "=r" (__xx.__i.__h), \
403 "=r" (__xx.__i.__l) \
404 : "%1" (m0), \
405 "r" (m1)); \
406 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
407 } while (0)
408 #define sdiv_qrnnd(q, r, n1, n0, d) \
409 do { \
410 union {DItype __ll; \
411 struct {USItype __h, __l;} __i; \
412 } __xx; \
413 __xx.__i.__h = n1; __xx.__i.__l = n0; \
414 __asm__ ("dr %0,%2" \
415 : "=r" (__xx.__ll) \
416 : "0" (__xx.__ll), "r" (d)); \
417 (q) = __xx.__i.__l; (r) = __xx.__i.__h; \
418 } while (0)
419 #endif
420
421 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
422 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
423 __asm__ ("addl %5,%1\n" \
424 "adcl %3,%0" \
425 : "=r" ((USItype) (sh)), \
426 "=&r" ((USItype) (sl)) \
427 : "%0" ((USItype) (ah)), \
428 "g" ((USItype) (bh)), \
429 "%1" ((USItype) (al)), \
430 "g" ((USItype) (bl)))
431 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
432 __asm__ ("subl %5,%1\n" \
433 "sbbl %3,%0" \
434 : "=r" ((USItype) (sh)), \
435 "=&r" ((USItype) (sl)) \
436 : "0" ((USItype) (ah)), \
437 "g" ((USItype) (bh)), \
438 "1" ((USItype) (al)), \
439 "g" ((USItype) (bl)))
440 #define umul_ppmm(w1, w0, u, v) \
441 __asm__ ("mull %3" \
442 : "=a" ((USItype) (w0)), \
443 "=d" ((USItype) (w1)) \
444 : "%0" ((USItype) (u)), \
445 "rm" ((USItype) (v)))
446 #define udiv_qrnnd(q, r, n1, n0, d) \
447 __asm__ ("divl %4" \
448 : "=a" ((USItype) (q)), \
449 "=d" ((USItype) (r)) \
450 : "0" ((USItype) (n0)), \
451 "1" ((USItype) (n1)), \
452 "rm" ((USItype) (d)))
453 #define count_leading_zeros(count, x) \
454 do { \
455 USItype __cbtmp; \
456 __asm__ ("bsrl %1,%0" \
457 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \
458 (count) = __cbtmp ^ 31; \
459 } while (0)
460 #define count_trailing_zeros(count, x) \
461 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
462 #define UMUL_TIME 40
463 #define UDIV_TIME 40
464 #endif /* 80x86 */
465
466 #if defined (__i860__) && W_TYPE_SIZE == 32
467 #if 0
468 /* Make sure these patterns really improve the code before
469 switching them on. */
470 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
471 do { \
472 union \
473 { \
474 DItype __ll; \
475 struct {USItype __l, __h;} __i; \
476 } __a, __b, __s; \
477 __a.__i.__l = (al); \
478 __a.__i.__h = (ah); \
479 __b.__i.__l = (bl); \
480 __b.__i.__h = (bh); \
481 __asm__ ("fiadd.dd %1,%2,%0" \
482 : "=f" (__s.__ll) \
483 : "%f" (__a.__ll), "f" (__b.__ll)); \
484 (sh) = __s.__i.__h; \
485 (sl) = __s.__i.__l; \
486 } while (0)
487 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
488 do { \
489 union \
490 { \
491 DItype __ll; \
492 struct {USItype __l, __h;} __i; \
493 } __a, __b, __s; \
494 __a.__i.__l = (al); \
495 __a.__i.__h = (ah); \
496 __b.__i.__l = (bl); \
497 __b.__i.__h = (bh); \
498 __asm__ ("fisub.dd %1,%2,%0" \
499 : "=f" (__s.__ll) \
500 : "%f" (__a.__ll), "f" (__b.__ll)); \
501 (sh) = __s.__i.__h; \
502 (sl) = __s.__i.__l; \
503 } while (0)
504 #endif
505 #endif /* __i860__ */
506
507 #if defined (__i960__) && W_TYPE_SIZE == 32
508 #define umul_ppmm(w1, w0, u, v) \
509 ({union {UDItype __ll; \
510 struct {USItype __l, __h;} __i; \
511 } __xx; \
512 __asm__ ("emul %2,%1,%0" \
513 : "=d" (__xx.__ll) \
514 : "%dI" ((USItype) (u)), \
515 "dI" ((USItype) (v))); \
516 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
517 #define __umulsidi3(u, v) \
518 ({UDItype __w; \
519 __asm__ ("emul %2,%1,%0" \
520 : "=d" (__w) \
521 : "%dI" ((USItype) (u)), \
522 "dI" ((USItype) (v))); \
523 __w; })
524 #endif /* __i960__ */
525
526 #if defined (__M32R__) && W_TYPE_SIZE == 32
527 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
528 /* The cmp clears the condition bit. */ \
529 __asm__ ("cmp %0,%0\n" \
530 "addx %%5,%1\n" \
531 "addx %%3,%0" \
532 : "=r" ((USItype) (sh)), \
533 "=&r" ((USItype) (sl)) \
534 : "%0" ((USItype) (ah)), \
535 "r" ((USItype) (bh)), \
536 "%1" ((USItype) (al)), \
537 "r" ((USItype) (bl)) \
538 : "cbit")
539 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
540 /* The cmp clears the condition bit. */ \
541 __asm__ ("cmp %0,%0\n" \
542 "subx %5,%1\n" \
543 "subx %3,%0" \
544 : "=r" ((USItype) (sh)), \
545 "=&r" ((USItype) (sl)) \
546 : "0" ((USItype) (ah)), \
547 "r" ((USItype) (bh)), \
548 "1" ((USItype) (al)), \
549 "r" ((USItype) (bl)) \
550 : "cbit")
551 #endif /* __M32R__ */
552
553 #if defined (__mc68000__) && W_TYPE_SIZE == 32
554 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
555 __asm__ ("add%.l %5,%1\n" \
556 "addx%.l %3,%0" \
557 : "=d" ((USItype) (sh)), \
558 "=&d" ((USItype) (sl)) \
559 : "%0" ((USItype) (ah)), \
560 "d" ((USItype) (bh)), \
561 "%1" ((USItype) (al)), \
562 "g" ((USItype) (bl)))
563 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
564 __asm__ ("sub%.l %5,%1\n" \
565 "subx%.l %3,%0" \
566 : "=d" ((USItype) (sh)), \
567 "=&d" ((USItype) (sl)) \
568 : "0" ((USItype) (ah)), \
569 "d" ((USItype) (bh)), \
570 "1" ((USItype) (al)), \
571 "g" ((USItype) (bl)))
572
573 /* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */
574 #if defined (__mc68020__) || defined(mc68020) \
575 || defined(__mc68030__) || defined(mc68030) \
576 || defined(__mc68040__) || defined(mc68040) \
577 || defined(__mcpu32__) || defined(mcpu32) \
578 || defined(__NeXT__)
579 #define umul_ppmm(w1, w0, u, v) \
580 __asm__ ("mulu%.l %3,%1:%0" \
581 : "=d" ((USItype) (w0)), \
582 "=d" ((USItype) (w1)) \
583 : "%0" ((USItype) (u)), \
584 "dmi" ((USItype) (v)))
585 #define UMUL_TIME 45
586 #define udiv_qrnnd(q, r, n1, n0, d) \
587 __asm__ ("divu%.l %4,%1:%0" \
588 : "=d" ((USItype) (q)), \
589 "=d" ((USItype) (r)) \
590 : "0" ((USItype) (n0)), \
591 "1" ((USItype) (n1)), \
592 "dmi" ((USItype) (d)))
593 #define UDIV_TIME 90
594 #define sdiv_qrnnd(q, r, n1, n0, d) \
595 __asm__ ("divs%.l %4,%1:%0" \
596 : "=d" ((USItype) (q)), \
597 "=d" ((USItype) (r)) \
598 : "0" ((USItype) (n0)), \
599 "1" ((USItype) (n1)), \
600 "dmi" ((USItype) (d)))
601
602 #else /* not mc68020 */
603 #if !defined(__mcf5200__)
604 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
605 #define umul_ppmm(xh, xl, a, b) \
606 __asm__ ("| Inlined umul_ppmm\n" \
607 " move%.l %2,%/d0\n" \
608 " move%.l %3,%/d1\n" \
609 " move%.l %/d0,%/d2\n" \
610 " swap %/d0\n" \
611 " move%.l %/d1,%/d3\n" \
612 " swap %/d1\n" \
613 " move%.w %/d2,%/d4\n" \
614 " mulu %/d3,%/d4\n" \
615 " mulu %/d1,%/d2\n" \
616 " mulu %/d0,%/d3\n" \
617 " mulu %/d0,%/d1\n" \
618 " move%.l %/d4,%/d0\n" \
619 " eor%.w %/d0,%/d0\n" \
620 " swap %/d0\n" \
621 " add%.l %/d0,%/d2\n" \
622 " add%.l %/d3,%/d2\n" \
623 " jcc 1f\n" \
624 " add%.l %#65536,%/d1\n" \
625 "1: swap %/d2\n" \
626 " moveq %#0,%/d0\n" \
627 " move%.w %/d2,%/d0\n" \
628 " move%.w %/d4,%/d2\n" \
629 " move%.l %/d2,%1\n" \
630 " add%.l %/d1,%/d0\n" \
631 " move%.l %/d0,%0" \
632 : "=g" ((USItype) (xh)), \
633 "=g" ((USItype) (xl)) \
634 : "g" ((USItype) (a)), \
635 "g" ((USItype) (b)) \
636 : "d0", "d1", "d2", "d3", "d4")
637 #define UMUL_TIME 100
638 #define UDIV_TIME 400
639 #endif /* not mcf5200 */
640 #endif /* not mc68020 */
641
642 /* The '020, '030, '040 and '060 have bitfield insns. */
643 #if defined (__mc68020__) || defined(mc68020) \
644 || defined(__mc68030__) || defined(mc68030) \
645 || defined(__mc68040__) || defined(mc68040) \
646 || defined(__mc68060__) || defined(mc68060) \
647 || defined(__NeXT__)
648 #define count_leading_zeros(count, x) \
649 __asm__ ("bfffo %1{%b2:%b2},%0" \
650 : "=d" ((USItype) (count)) \
651 : "od" ((USItype) (x)), "n" (0))
652 #endif
653 #endif /* mc68000 */
654
655 #if defined (__m88000__) && W_TYPE_SIZE == 32
656 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
657 __asm__ ("addu.co %1,%r4,%r5\n" \
658 "addu.ci %0,%r2,%r3" \
659 : "=r" ((USItype) (sh)), \
660 "=&r" ((USItype) (sl)) \
661 : "%rJ" ((USItype) (ah)), \
662 "rJ" ((USItype) (bh)), \
663 "%rJ" ((USItype) (al)), \
664 "rJ" ((USItype) (bl)))
665 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
666 __asm__ ("subu.co %1,%r4,%r5\n" \
667 "subu.ci %0,%r2,%r3" \
668 : "=r" ((USItype) (sh)), \
669 "=&r" ((USItype) (sl)) \
670 : "rJ" ((USItype) (ah)), \
671 "rJ" ((USItype) (bh)), \
672 "rJ" ((USItype) (al)), \
673 "rJ" ((USItype) (bl)))
674 #define count_leading_zeros(count, x) \
675 do { \
676 USItype __cbtmp; \
677 __asm__ ("ff1 %0,%1" \
678 : "=r" (__cbtmp) \
679 : "r" ((USItype) (x))); \
680 (count) = __cbtmp ^ 31; \
681 } while (0)
682 #define COUNT_LEADING_ZEROS_0 63 /* sic */
683 #if defined (__mc88110__)
684 #define umul_ppmm(wh, wl, u, v) \
685 do { \
686 union {UDItype __ll; \
687 struct {USItype __h, __l;} __i; \
688 } __xx; \
689 __asm__ ("mulu.d %0,%1,%2" \
690 : "=r" (__xx.__ll) \
691 : "r" ((USItype) (u)), \
692 "r" ((USItype) (v))); \
693 (wh) = __xx.__i.__h; \
694 (wl) = __xx.__i.__l; \
695 } while (0)
696 #define udiv_qrnnd(q, r, n1, n0, d) \
697 ({union {UDItype __ll; \
698 struct {USItype __h, __l;} __i; \
699 } __xx; \
700 USItype __q; \
701 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
702 __asm__ ("divu.d %0,%1,%2" \
703 : "=r" (__q) \
704 : "r" (__xx.__ll), \
705 "r" ((USItype) (d))); \
706 (r) = (n0) - __q * (d); (q) = __q; })
707 #define UMUL_TIME 5
708 #define UDIV_TIME 25
709 #else
710 #define UMUL_TIME 17
711 #define UDIV_TIME 150
712 #endif /* __mc88110__ */
713 #endif /* __m88000__ */
714
715 #if defined (__mips__) && W_TYPE_SIZE == 32
716 #define umul_ppmm(w1, w0, u, v) \
717 __asm__ ("multu %2,%3" \
718 : "=l" ((USItype) (w0)), \
719 "=h" ((USItype) (w1)) \
720 : "d" ((USItype) (u)), \
721 "d" ((USItype) (v)))
722 #define UMUL_TIME 10
723 #define UDIV_TIME 100
724 #endif /* __mips__ */
725
726 #if defined (__ns32000__) && W_TYPE_SIZE == 32
727 #define umul_ppmm(w1, w0, u, v) \
728 ({union {UDItype __ll; \
729 struct {USItype __l, __h;} __i; \
730 } __xx; \
731 __asm__ ("meid %2,%0" \
732 : "=g" (__xx.__ll) \
733 : "%0" ((USItype) (u)), \
734 "g" ((USItype) (v))); \
735 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
736 #define __umulsidi3(u, v) \
737 ({UDItype __w; \
738 __asm__ ("meid %2,%0" \
739 : "=g" (__w) \
740 : "%0" ((USItype) (u)), \
741 "g" ((USItype) (v))); \
742 __w; })
743 #define udiv_qrnnd(q, r, n1, n0, d) \
744 ({union {UDItype __ll; \
745 struct {USItype __l, __h;} __i; \
746 } __xx; \
747 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
748 __asm__ ("deid %2,%0" \
749 : "=g" (__xx.__ll) \
750 : "0" (__xx.__ll), \
751 "g" ((USItype) (d))); \
752 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
753 #define count_trailing_zeros(count,x) \
754 do {
755 __asm__ ("ffsd %2,%0" \
756 : "=r" ((USItype) (count)) \
757 : "0" ((USItype) 0), \
758 "r" ((USItype) (x))); \
759 } while (0)
760 #endif /* __ns32000__ */
761
762 #if (defined (_ARCH_PPC) || defined (_IBMR2)) && W_TYPE_SIZE == 32
763 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
764 do { \
765 if (__builtin_constant_p (bh) && (bh) == 0) \
766 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
767 : "=r" ((USItype) (sh)), \
768 "=&r" ((USItype) (sl)) \
769 : "%r" ((USItype) (ah)), \
770 "%r" ((USItype) (al)), \
771 "rI" ((USItype) (bl))); \
772 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
773 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
774 : "=r" ((USItype) (sh)), \
775 "=&r" ((USItype) (sl)) \
776 : "%r" ((USItype) (ah)), \
777 "%r" ((USItype) (al)), \
778 "rI" ((USItype) (bl))); \
779 else \
780 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
781 : "=r" ((USItype) (sh)), \
782 "=&r" ((USItype) (sl)) \
783 : "%r" ((USItype) (ah)), \
784 "r" ((USItype) (bh)), \
785 "%r" ((USItype) (al)), \
786 "rI" ((USItype) (bl))); \
787 } while (0)
788 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
789 do { \
790 if (__builtin_constant_p (ah) && (ah) == 0) \
791 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
792 : "=r" ((USItype) (sh)), \
793 "=&r" ((USItype) (sl)) \
794 : "r" ((USItype) (bh)), \
795 "rI" ((USItype) (al)), \
796 "r" ((USItype) (bl))); \
797 else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
798 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
799 : "=r" ((USItype) (sh)), \
800 "=&r" ((USItype) (sl)) \
801 : "r" ((USItype) (bh)), \
802 "rI" ((USItype) (al)), \
803 "r" ((USItype) (bl))); \
804 else if (__builtin_constant_p (bh) && (bh) == 0) \
805 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
806 : "=r" ((USItype) (sh)), \
807 "=&r" ((USItype) (sl)) \
808 : "r" ((USItype) (ah)), \
809 "rI" ((USItype) (al)), \
810 "r" ((USItype) (bl))); \
811 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
812 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
813 : "=r" ((USItype) (sh)), \
814 "=&r" ((USItype) (sl)) \
815 : "r" ((USItype) (ah)), \
816 "rI" ((USItype) (al)), \
817 "r" ((USItype) (bl))); \
818 else \
819 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
820 : "=r" ((USItype) (sh)), \
821 "=&r" ((USItype) (sl)) \
822 : "r" ((USItype) (ah)), \
823 "r" ((USItype) (bh)), \
824 "rI" ((USItype) (al)), \
825 "r" ((USItype) (bl))); \
826 } while (0)
827 #define count_leading_zeros(count, x) \
828 __asm__ ("{cntlz|cntlzw} %0,%1" \
829 : "=r" ((USItype) (count)) \
830 : "r" ((USItype) (x)))
831 #define COUNT_LEADING_ZEROS_0 32
832 #if defined (_ARCH_PPC)
833 #define umul_ppmm(ph, pl, m0, m1) \
834 do { \
835 USItype __m0 = (m0), __m1 = (m1); \
836 __asm__ ("mulhwu %0,%1,%2" \
837 : "=r" ((USItype) ph) \
838 : "%r" (__m0), \
839 "r" (__m1)); \
840 (pl) = __m0 * __m1; \
841 } while (0)
842 #define UMUL_TIME 15
843 #define smul_ppmm(ph, pl, m0, m1) \
844 do { \
845 SItype __m0 = (m0), __m1 = (m1); \
846 __asm__ ("mulhw %0,%1,%2" \
847 : "=r" ((SItype) ph) \
848 : "%r" (__m0), \
849 "r" (__m1)); \
850 (pl) = __m0 * __m1; \
851 } while (0)
852 #define SMUL_TIME 14
853 #define UDIV_TIME 120
854 #else
855 #define umul_ppmm(xh, xl, m0, m1) \
856 do { \
857 USItype __m0 = (m0), __m1 = (m1); \
858 __asm__ ("mul %0,%2,%3" \
859 : "=r" ((USItype) (xh)), \
860 "=q" ((USItype) (xl)) \
861 : "r" (__m0), \
862 "r" (__m1)); \
863 (xh) += ((((SItype) __m0 >> 31) & __m1) \
864 + (((SItype) __m1 >> 31) & __m0)); \
865 } while (0)
866 #define UMUL_TIME 8
867 #define smul_ppmm(xh, xl, m0, m1) \
868 __asm__ ("mul %0,%2,%3" \
869 : "=r" ((SItype) (xh)), \
870 "=q" ((SItype) (xl)) \
871 : "r" (m0), \
872 "r" (m1))
873 #define SMUL_TIME 4
874 #define sdiv_qrnnd(q, r, nh, nl, d) \
875 __asm__ ("div %0,%2,%4" \
876 : "=r" ((SItype) (q)), "=q" ((SItype) (r)) \
877 : "r" ((SItype) (nh)), "1" ((SItype) (nl)), "r" ((SItype) (d)))
878 #define UDIV_TIME 100
879 #endif
880 #endif /* Power architecture variants. */
881
882 #if defined (__pyr__) && W_TYPE_SIZE == 32
883 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
884 __asm__ ("addw %5,%1\n" \
885 "addwc %3,%0" \
886 : "=r" ((USItype) (sh)), \
887 "=&r" ((USItype) (sl)) \
888 : "%0" ((USItype) (ah)), \
889 "g" ((USItype) (bh)), \
890 "%1" ((USItype) (al)), \
891 "g" ((USItype) (bl)))
892 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
893 __asm__ ("subw %5,%1\n" \
894 "subwb %3,%0" \
895 : "=r" ((USItype) (sh)), \
896 "=&r" ((USItype) (sl)) \
897 : "0" ((USItype) (ah)), \
898 "g" ((USItype) (bh)), \
899 "1" ((USItype) (al)), \
900 "g" ((USItype) (bl)))
901 /* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP. */
902 #define umul_ppmm(w1, w0, u, v) \
903 ({union {UDItype __ll; \
904 struct {USItype __h, __l;} __i; \
905 } __xx; \
906 __asm__ ("movw %1,%R0\n" \
907 "uemul %2,%0" \
908 : "=&r" (__xx.__ll) \
909 : "g" ((USItype) (u)), \
910 "g" ((USItype) (v))); \
911 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
912 #endif /* __pyr__ */
913
914 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
915 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
916 __asm__ ("a %1,%5\n" \
917 "ae %0,%3" \
918 : "=r" ((USItype) (sh)), \
919 "=&r" ((USItype) (sl)) \
920 : "%0" ((USItype) (ah)), \
921 "r" ((USItype) (bh)), \
922 "%1" ((USItype) (al)), \
923 "r" ((USItype) (bl)))
924 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
925 __asm__ ("s %1,%5\n" \
926 "se %0,%3" \
927 : "=r" ((USItype) (sh)), \
928 "=&r" ((USItype) (sl)) \
929 : "0" ((USItype) (ah)), \
930 "r" ((USItype) (bh)), \
931 "1" ((USItype) (al)), \
932 "r" ((USItype) (bl)))
933 #define umul_ppmm(ph, pl, m0, m1) \
934 do { \
935 USItype __m0 = (m0), __m1 = (m1); \
936 __asm__ ( \
937 "s r2,r2\n" \
938 "mts r10,%2\n" \
939 "m r2,%3\n" \
940 "m r2,%3\n" \
941 "m r2,%3\n" \
942 "m r2,%3\n" \
943 "m r2,%3\n" \
944 "m r2,%3\n" \
945 "m r2,%3\n" \
946 "m r2,%3\n" \
947 "m r2,%3\n" \
948 "m r2,%3\n" \
949 "m r2,%3\n" \
950 "m r2,%3\n" \
951 "m r2,%3\n" \
952 "m r2,%3\n" \
953 "m r2,%3\n" \
954 "m r2,%3\n" \
955 "cas %0,r2,r0\n" \
956 "mfs r10,%1" \
957 : "=r" ((USItype) (ph)), \
958 "=r" ((USItype) (pl)) \
959 : "%r" (__m0), \
960 "r" (__m1) \
961 : "r2"); \
962 (ph) += ((((SItype) __m0 >> 31) & __m1) \
963 + (((SItype) __m1 >> 31) & __m0)); \
964 } while (0)
965 #define UMUL_TIME 20
966 #define UDIV_TIME 200
967 #define count_leading_zeros(count, x) \
968 do { \
969 if ((x) >= 0x10000) \
970 __asm__ ("clz %0,%1" \
971 : "=r" ((USItype) (count)) \
972 : "r" ((USItype) (x) >> 16)); \
973 else \
974 { \
975 __asm__ ("clz %0,%1" \
976 : "=r" ((USItype) (count)) \
977 : "r" ((USItype) (x))); \
978 (count) += 16; \
979 } \
980 } while (0)
981 #endif
982
983 #if defined (__sh2__) && W_TYPE_SIZE == 32
984 #define umul_ppmm(w1, w0, u, v) \
985 __asm__ ( \
986 "dmulu.l %2,%3\n" \
987 "sts macl,%1\n" \
988 "sts mach,%0" \
989 : "=r" ((USItype)(w1)), \
990 "=r" ((USItype)(w0)) \
991 : "r" ((USItype)(u)), \
992 "r" ((USItype)(v)) \
993 : "macl", "mach")
994 #define UMUL_TIME 5
995 #endif
996
997 #if defined (__sparc__) && !defined(__arch64__) \
998 && !defined(__sparcv9) && W_TYPE_SIZE == 32
999 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1000 __asm__ ("addcc %r4,%5,%1\n" \
1001 "addx %r2,%3,%0" \
1002 : "=r" ((USItype) (sh)), \
1003 "=&r" ((USItype) (sl)) \
1004 : "%rJ" ((USItype) (ah)), \
1005 "rI" ((USItype) (bh)), \
1006 "%rJ" ((USItype) (al)), \
1007 "rI" ((USItype) (bl)) \
1008 __CLOBBER_CC)
1009 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1010 __asm__ ("subcc %r4,%5,%1\n" \
1011 "subx %r2,%3,%0" \
1012 : "=r" ((USItype) (sh)), \
1013 "=&r" ((USItype) (sl)) \
1014 : "rJ" ((USItype) (ah)), \
1015 "rI" ((USItype) (bh)), \
1016 "rJ" ((USItype) (al)), \
1017 "rI" ((USItype) (bl)) \
1018 __CLOBBER_CC)
1019 #if defined (__sparc_v8__)
1020 #define umul_ppmm(w1, w0, u, v) \
1021 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1022 : "=r" ((USItype) (w1)), \
1023 "=r" ((USItype) (w0)) \
1024 : "r" ((USItype) (u)), \
1025 "r" ((USItype) (v)))
1026 #define udiv_qrnnd(q, r, n1, n0, d) \
1027 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
1028 : "=&r" ((USItype) (q)), \
1029 "=&r" ((USItype) (r)) \
1030 : "r" ((USItype) (n1)), \
1031 "r" ((USItype) (n0)), \
1032 "r" ((USItype) (d)))
1033 #else
1034 #if defined (__sparclite__)
1035 /* This has hardware multiply but not divide. It also has two additional
1036 instructions scan (ffs from high bit) and divscc. */
1037 #define umul_ppmm(w1, w0, u, v) \
1038 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1039 : "=r" ((USItype) (w1)), \
1040 "=r" ((USItype) (w0)) \
1041 : "r" ((USItype) (u)), \
1042 "r" ((USItype) (v)))
1043 #define udiv_qrnnd(q, r, n1, n0, d) \
1044 __asm__ ("! Inlined udiv_qrnnd\n" \
1045 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
1046 " tst %%g0\n" \
1047 " divscc %3,%4,%%g1\n" \
1048 " divscc %%g1,%4,%%g1\n" \
1049 " divscc %%g1,%4,%%g1\n" \
1050 " divscc %%g1,%4,%%g1\n" \
1051 " divscc %%g1,%4,%%g1\n" \
1052 " divscc %%g1,%4,%%g1\n" \
1053 " divscc %%g1,%4,%%g1\n" \
1054 " divscc %%g1,%4,%%g1\n" \
1055 " divscc %%g1,%4,%%g1\n" \
1056 " divscc %%g1,%4,%%g1\n" \
1057 " divscc %%g1,%4,%%g1\n" \
1058 " divscc %%g1,%4,%%g1\n" \
1059 " divscc %%g1,%4,%%g1\n" \
1060 " divscc %%g1,%4,%%g1\n" \
1061 " divscc %%g1,%4,%%g1\n" \
1062 " divscc %%g1,%4,%%g1\n" \
1063 " divscc %%g1,%4,%%g1\n" \
1064 " divscc %%g1,%4,%%g1\n" \
1065 " divscc %%g1,%4,%%g1\n" \
1066 " divscc %%g1,%4,%%g1\n" \
1067 " divscc %%g1,%4,%%g1\n" \
1068 " divscc %%g1,%4,%%g1\n" \
1069 " divscc %%g1,%4,%%g1\n" \
1070 " divscc %%g1,%4,%%g1\n" \
1071 " divscc %%g1,%4,%%g1\n" \
1072 " divscc %%g1,%4,%%g1\n" \
1073 " divscc %%g1,%4,%%g1\n" \
1074 " divscc %%g1,%4,%%g1\n" \
1075 " divscc %%g1,%4,%%g1\n" \
1076 " divscc %%g1,%4,%%g1\n" \
1077 " divscc %%g1,%4,%%g1\n" \
1078 " divscc %%g1,%4,%0\n" \
1079 " rd %%y,%1\n" \
1080 " bl,a 1f\n" \
1081 " add %1,%4,%1\n" \
1082 "1: ! End of inline udiv_qrnnd" \
1083 : "=r" ((USItype) (q)), \
1084 "=r" ((USItype) (r)) \
1085 : "r" ((USItype) (n1)), \
1086 "r" ((USItype) (n0)), \
1087 "rI" ((USItype) (d)) \
1088 : "g1" __AND_CLOBBER_CC)
1089 #define UDIV_TIME 37
1090 #define count_leading_zeros(count, x) \
1091 do { \
1092 __asm__ ("scan %1,1,%0" \
1093 : "=r" ((USItype) (count)) \
1094 : "r" ((USItype) (x))); \
1095 } while (0)
1096 /* Early sparclites return 63 for an argument of 0, but they warn that future
1097 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
1098 undefined. */
1099 #else
1100 /* SPARC without integer multiplication and divide instructions.
1101 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
1102 #define umul_ppmm(w1, w0, u, v) \
1103 __asm__ ("! Inlined umul_ppmm\n" \
1104 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
1105 " sra %3,31,%%o5 ! Don't move this insn\n" \
1106 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
1107 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1108 " mulscc %%g1,%3,%%g1\n" \
1109 " mulscc %%g1,%3,%%g1\n" \
1110 " mulscc %%g1,%3,%%g1\n" \
1111 " mulscc %%g1,%3,%%g1\n" \
1112 " mulscc %%g1,%3,%%g1\n" \
1113 " mulscc %%g1,%3,%%g1\n" \
1114 " mulscc %%g1,%3,%%g1\n" \
1115 " mulscc %%g1,%3,%%g1\n" \
1116 " mulscc %%g1,%3,%%g1\n" \
1117 " mulscc %%g1,%3,%%g1\n" \
1118 " mulscc %%g1,%3,%%g1\n" \
1119 " mulscc %%g1,%3,%%g1\n" \
1120 " mulscc %%g1,%3,%%g1\n" \
1121 " mulscc %%g1,%3,%%g1\n" \
1122 " mulscc %%g1,%3,%%g1\n" \
1123 " mulscc %%g1,%3,%%g1\n" \
1124 " mulscc %%g1,%3,%%g1\n" \
1125 " mulscc %%g1,%3,%%g1\n" \
1126 " mulscc %%g1,%3,%%g1\n" \
1127 " mulscc %%g1,%3,%%g1\n" \
1128 " mulscc %%g1,%3,%%g1\n" \
1129 " mulscc %%g1,%3,%%g1\n" \
1130 " mulscc %%g1,%3,%%g1\n" \
1131 " mulscc %%g1,%3,%%g1\n" \
1132 " mulscc %%g1,%3,%%g1\n" \
1133 " mulscc %%g1,%3,%%g1\n" \
1134 " mulscc %%g1,%3,%%g1\n" \
1135 " mulscc %%g1,%3,%%g1\n" \
1136 " mulscc %%g1,%3,%%g1\n" \
1137 " mulscc %%g1,%3,%%g1\n" \
1138 " mulscc %%g1,%3,%%g1\n" \
1139 " mulscc %%g1,%3,%%g1\n" \
1140 " mulscc %%g1,0,%%g1\n" \
1141 " add %%g1,%%o5,%0\n" \
1142 " rd %%y,%1" \
1143 : "=r" ((USItype) (w1)), \
1144 "=r" ((USItype) (w0)) \
1145 : "%rI" ((USItype) (u)), \
1146 "r" ((USItype) (v)) \
1147 : "g1", "o5" __AND_CLOBBER_CC)
1148 #define UMUL_TIME 39 /* 39 instructions */
1149 /* It's quite necessary to add this much assembler for the sparc.
1150 The default udiv_qrnnd (in C) is more than 10 times slower! */
1151 #define udiv_qrnnd(q, r, n1, n0, d) \
1152 __asm__ ("! Inlined udiv_qrnnd\n" \
1153 " mov 32,%%g1\n" \
1154 " subcc %1,%2,%%g0\n" \
1155 "1: bcs 5f\n" \
1156 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1157 " sub %1,%2,%1 ! this kills msb of n\n" \
1158 " addx %1,%1,%1 ! so this can't give carry\n" \
1159 " subcc %%g1,1,%%g1\n" \
1160 "2: bne 1b\n" \
1161 " subcc %1,%2,%%g0\n" \
1162 " bcs 3f\n" \
1163 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1164 " b 3f\n" \
1165 " sub %1,%2,%1 ! this kills msb of n\n" \
1166 "4: sub %1,%2,%1\n" \
1167 "5: addxcc %1,%1,%1\n" \
1168 " bcc 2b\n" \
1169 " subcc %%g1,1,%%g1\n" \
1170 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1171 " bne 4b\n" \
1172 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1173 " sub %1,%2,%1\n" \
1174 "3: xnor %0,0,%0\n" \
1175 " ! End of inline udiv_qrnnd" \
1176 : "=&r" ((USItype) (q)), \
1177 "=&r" ((USItype) (r)) \
1178 : "r" ((USItype) (d)), \
1179 "1" ((USItype) (n1)), \
1180 "0" ((USItype) (n0)) : "g1" __AND_CLOBBER_CC)
1181 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1182 #endif /* __sparclite__ */
1183 #endif /* __sparc_v8__ */
1184 #endif /* __sparc__ */
1185
1186 #if ((defined (__sparc__) && defined (__arch64__)) \
1187 || defined (__sparcv9)) && W_TYPE_SIZE == 64
1188 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1189 __asm__ ("addcc %r4,%5,%1\n" \
1190 "add %r2,%3,%0\n" \
1191 "bcs,a,pn %%xcc, 1f\n" \
1192 "add %0, 1, %0\n" \
1193 "1:" \
1194 : "=r" ((UDItype)(sh)), \
1195 "=&r" ((UDItype)(sl)) \
1196 : "%rJ" ((UDItype)(ah)), \
1197 "rI" ((UDItype)(bh)), \
1198 "%rJ" ((UDItype)(al)), \
1199 "rI" ((UDItype)(bl)) \
1200 __CLOBBER_CC)
1201
1202 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1203 __asm__ ("subcc %r4,%5,%1\n" \
1204 "sub %r2,%3,%0\n" \
1205 "bcs,a,pn %%xcc, 1f\n" \
1206 "sub %0, 1, %0\n" \
1207 "1:" \
1208 : "=r" ((UDItype)(sh)), \
1209 "=&r" ((UDItype)(sl)) \
1210 : "rJ" ((UDItype)(ah)), \
1211 "rI" ((UDItype)(bh)), \
1212 "rJ" ((UDItype)(al)), \
1213 "rI" ((UDItype)(bl)) \
1214 __CLOBBER_CC)
1215
1216 #define umul_ppmm(wh, wl, u, v) \
1217 do { \
1218 UDItype tmp1, tmp2, tmp3, tmp4; \
1219 __asm__ __volatile__ ( \
1220 "srl %7,0,%3\n" \
1221 "mulx %3,%6,%1\n" \
1222 "srlx %6,32,%2\n" \
1223 "mulx %2,%3,%4\n" \
1224 "sllx %4,32,%5\n" \
1225 "srl %6,0,%3\n" \
1226 "sub %1,%5,%5\n" \
1227 "srlx %5,32,%5\n" \
1228 "addcc %4,%5,%4\n" \
1229 "srlx %7,32,%5\n" \
1230 "mulx %3,%5,%3\n" \
1231 "mulx %2,%5,%5\n" \
1232 "sethi %%hi(0x80000000),%2\n" \
1233 "addcc %4,%3,%4\n" \
1234 "srlx %4,32,%4\n" \
1235 "add %2,%2,%2\n" \
1236 "movcc %%xcc,%%g0,%2\n" \
1237 "addcc %5,%4,%5\n" \
1238 "sllx %3,32,%3\n" \
1239 "add %1,%3,%1\n" \
1240 "add %5,%2,%0" \
1241 : "=r" ((UDItype)(wh)), \
1242 "=&r" ((UDItype)(wl)), \
1243 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1244 : "r" ((UDItype)(u)), \
1245 "r" ((UDItype)(v)) \
1246 __CLOBBER_CC); \
1247 } while (0)
1248 #define UMUL_TIME 96
1249 #define UDIV_TIME 230
1250 #endif /* sparc64 */
1251
1252 #if defined (__vax__) && W_TYPE_SIZE == 32
1253 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1254 __asm__ ("addl2 %5,%1\n" \
1255 "adwc %3,%0" \
1256 : "=g" ((USItype) (sh)), \
1257 "=&g" ((USItype) (sl)) \
1258 : "%0" ((USItype) (ah)), \
1259 "g" ((USItype) (bh)), \
1260 "%1" ((USItype) (al)), \
1261 "g" ((USItype) (bl)))
1262 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1263 __asm__ ("subl2 %5,%1\n" \
1264 "sbwc %3,%0" \
1265 : "=g" ((USItype) (sh)), \
1266 "=&g" ((USItype) (sl)) \
1267 : "0" ((USItype) (ah)), \
1268 "g" ((USItype) (bh)), \
1269 "1" ((USItype) (al)), \
1270 "g" ((USItype) (bl)))
1271 #define umul_ppmm(xh, xl, m0, m1) \
1272 do { \
1273 union { \
1274 UDItype __ll; \
1275 struct {USItype __l, __h;} __i; \
1276 } __xx; \
1277 USItype __m0 = (m0), __m1 = (m1); \
1278 __asm__ ("emul %1,%2,$0,%0" \
1279 : "=r" (__xx.__ll) \
1280 : "g" (__m0), \
1281 "g" (__m1)); \
1282 (xh) = __xx.__i.__h; \
1283 (xl) = __xx.__i.__l; \
1284 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1285 + (((SItype) __m1 >> 31) & __m0)); \
1286 } while (0)
1287 #define sdiv_qrnnd(q, r, n1, n0, d) \
1288 do { \
1289 union {DItype __ll; \
1290 struct {SItype __l, __h;} __i; \
1291 } __xx; \
1292 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1293 __asm__ ("ediv %3,%2,%0,%1" \
1294 : "=g" (q), "=g" (r) \
1295 : "g" (__xx.__ll), "g" (d)); \
1296 } while (0)
1297 #endif /* __vax__ */
1298
1299 #if defined (__z8000__) && W_TYPE_SIZE == 16
1300 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1301 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1302 : "=r" ((unsigned int)(sh)), \
1303 "=&r" ((unsigned int)(sl)) \
1304 : "%0" ((unsigned int)(ah)), \
1305 "r" ((unsigned int)(bh)), \
1306 "%1" ((unsigned int)(al)), \
1307 "rQR" ((unsigned int)(bl)))
1308 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1309 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1310 : "=r" ((unsigned int)(sh)), \
1311 "=&r" ((unsigned int)(sl)) \
1312 : "0" ((unsigned int)(ah)), \
1313 "r" ((unsigned int)(bh)), \
1314 "1" ((unsigned int)(al)), \
1315 "rQR" ((unsigned int)(bl)))
1316 #define umul_ppmm(xh, xl, m0, m1) \
1317 do { \
1318 union {long int __ll; \
1319 struct {unsigned int __h, __l;} __i; \
1320 } __xx; \
1321 unsigned int __m0 = (m0), __m1 = (m1); \
1322 __asm__ ("mult %S0,%H3" \
1323 : "=r" (__xx.__i.__h), \
1324 "=r" (__xx.__i.__l) \
1325 : "%1" (__m0), \
1326 "rQR" (__m1)); \
1327 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1328 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1329 + (((signed int) __m1 >> 15) & __m0)); \
1330 } while (0)
1331 #endif /* __z8000__ */
1332
1333 #endif /* __GNUC__ */
1334
1335 /* If this machine has no inline assembler, use C macros. */
1336
1337 #if !defined (add_ssaaaa)
1338 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1339 do { \
1340 UWtype __x; \
1341 __x = (al) + (bl); \
1342 (sh) = (ah) + (bh) + (__x < (al)); \
1343 (sl) = __x; \
1344 } while (0)
1345 #endif
1346
1347 #if !defined (sub_ddmmss)
1348 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1349 do { \
1350 UWtype __x; \
1351 __x = (al) - (bl); \
1352 (sh) = (ah) - (bh) - (__x > (al)); \
1353 (sl) = __x; \
1354 } while (0)
1355 #endif
1356
1357 #if !defined (umul_ppmm)
1358 #define umul_ppmm(w1, w0, u, v) \
1359 do { \
1360 UWtype __x0, __x1, __x2, __x3; \
1361 UHWtype __ul, __vl, __uh, __vh; \
1362 \
1363 __ul = __ll_lowpart (u); \
1364 __uh = __ll_highpart (u); \
1365 __vl = __ll_lowpart (v); \
1366 __vh = __ll_highpart (v); \
1367 \
1368 __x0 = (UWtype) __ul * __vl; \
1369 __x1 = (UWtype) __ul * __vh; \
1370 __x2 = (UWtype) __uh * __vl; \
1371 __x3 = (UWtype) __uh * __vh; \
1372 \
1373 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1374 __x1 += __x2; /* but this indeed can */ \
1375 if (__x1 < __x2) /* did we get it? */ \
1376 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1377 \
1378 (w1) = __x3 + __ll_highpart (__x1); \
1379 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1380 } while (0)
1381 #endif
1382
1383 #if !defined (__umulsidi3)
1384 #define __umulsidi3(u, v) \
1385 ({DIunion __w; \
1386 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1387 __w.ll; })
1388 #endif
1389
1390 /* Define this unconditionally, so it can be used for debugging. */
1391 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1392 do { \
1393 UWtype __d1, __d0, __q1, __q0; \
1394 UWtype __r1, __r0, __m; \
1395 __d1 = __ll_highpart (d); \
1396 __d0 = __ll_lowpart (d); \
1397 \
1398 __r1 = (n1) % __d1; \
1399 __q1 = (n1) / __d1; \
1400 __m = (UWtype) __q1 * __d0; \
1401 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1402 if (__r1 < __m) \
1403 { \
1404 __q1--, __r1 += (d); \
1405 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1406 if (__r1 < __m) \
1407 __q1--, __r1 += (d); \
1408 } \
1409 __r1 -= __m; \
1410 \
1411 __r0 = __r1 % __d1; \
1412 __q0 = __r1 / __d1; \
1413 __m = (UWtype) __q0 * __d0; \
1414 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1415 if (__r0 < __m) \
1416 { \
1417 __q0--, __r0 += (d); \
1418 if (__r0 >= (d)) \
1419 if (__r0 < __m) \
1420 __q0--, __r0 += (d); \
1421 } \
1422 __r0 -= __m; \
1423 \
1424 (q) = (UWtype) __q1 * __ll_B | __q0; \
1425 (r) = __r0; \
1426 } while (0)
1427
1428 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1429 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1430 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1431 #define udiv_qrnnd(q, r, nh, nl, d) \
1432 do { \
1433 USItype __r; \
1434 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1435 (r) = __r; \
1436 } while (0)
1437 #endif
1438
1439 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1440 #if !defined (udiv_qrnnd)
1441 #define UDIV_NEEDS_NORMALIZATION 1
1442 #define udiv_qrnnd __udiv_qrnnd_c
1443 #endif
1444
1445 #if !defined (count_leading_zeros)
1446 extern const UQItype __clz_tab[];
1447 #define count_leading_zeros(count, x) \
1448 do { \
1449 UWtype __xr = (x); \
1450 UWtype __a; \
1451 \
1452 if (W_TYPE_SIZE <= 32) \
1453 { \
1454 __a = __xr < ((UWtype)1<<2*__BITS4) \
1455 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1456 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1457 } \
1458 else \
1459 { \
1460 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1461 if (((__xr >> __a) & 0xff) != 0) \
1462 break; \
1463 } \
1464 \
1465 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1466 } while (0)
1467 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1468 #endif
1469
1470 #if !defined (count_trailing_zeros)
1471 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1472 defined in asm, but if it is not, the C version above is good enough. */
1473 #define count_trailing_zeros(count, x) \
1474 do { \
1475 UWtype __ctz_x = (x); \
1476 UWtype __ctz_c; \
1477 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1478 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1479 } while (0)
1480 #endif
1481
1482 #ifndef UDIV_NEEDS_NORMALIZATION
1483 #define UDIV_NEEDS_NORMALIZATION 0
1484 #endif
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