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[glibc.git] / sysdeps / unix / sysv / linux / i386 / sysconf.c
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1 /* Get file-specific information about a file. Linux version.
2 Copyright (C) 2003, 2004, 2006, 2007, 2009, 2011 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <http://www.gnu.org/licenses/>. */
19 #include <assert.h>
20 #include <stdbool.h>
21 #include <stdlib.h>
22 #include <unistd.h>
23 #include <hp-timing.h>
25 static long int linux_sysconf (int name);
28 static long int __attribute__ ((noinline))
29 handle_i486 (int name)
31 /* The processor only has a unified level 1 cache of 8k. */
32 switch (name)
34 case _SC_LEVEL1_ICACHE_SIZE:
35 case _SC_LEVEL1_DCACHE_SIZE:
36 return 8 * 1024;
38 case _SC_LEVEL1_ICACHE_ASSOC:
39 case _SC_LEVEL1_DCACHE_ASSOC:
40 // XXX Anybody know this?
41 return 0;
43 case _SC_LEVEL1_ICACHE_LINESIZE:
44 case _SC_LEVEL1_DCACHE_LINESIZE:
45 // XXX Anybody know for sure?
46 return 16;
48 case _SC_LEVEL2_CACHE_SIZE:
49 case _SC_LEVEL2_CACHE_ASSOC:
50 case _SC_LEVEL2_CACHE_LINESIZE:
51 case _SC_LEVEL3_CACHE_SIZE:
52 case _SC_LEVEL3_CACHE_ASSOC:
53 case _SC_LEVEL3_CACHE_LINESIZE:
54 case _SC_LEVEL4_CACHE_SIZE:
55 case _SC_LEVEL4_CACHE_ASSOC:
56 /* Not available. */
57 break;
59 default:
60 assert (! "cannot happen");
63 return -1;
67 static const struct intel_02_cache_info
69 unsigned char idx;
70 unsigned char assoc;
71 unsigned char linesize;
72 unsigned char rel_name;
73 unsigned int size;
74 } intel_02_known [] =
76 #define M(sc) ((sc) - _SC_LEVEL1_ICACHE_SIZE)
77 { 0x06, 4, 32, M(_SC_LEVEL1_ICACHE_SIZE), 8192 },
78 { 0x08, 4, 32, M(_SC_LEVEL1_ICACHE_SIZE), 16384 },
79 { 0x09, 4, 32, M(_SC_LEVEL1_ICACHE_SIZE), 32768 },
80 { 0x0a, 2, 32, M(_SC_LEVEL1_DCACHE_SIZE), 8192 },
81 { 0x0c, 4, 32, M(_SC_LEVEL1_DCACHE_SIZE), 16384 },
82 { 0x0d, 4, 64, M(_SC_LEVEL1_DCACHE_SIZE), 16384 },
83 { 0x21, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
84 { 0x22, 4, 64, M(_SC_LEVEL3_CACHE_SIZE), 524288 },
85 { 0x23, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 1048576 },
86 { 0x25, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
87 { 0x29, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
88 { 0x2c, 8, 64, M(_SC_LEVEL1_DCACHE_SIZE), 32768 },
89 { 0x30, 8, 64, M(_SC_LEVEL1_ICACHE_SIZE), 32768 },
90 { 0x39, 4, 64, M(_SC_LEVEL2_CACHE_SIZE), 131072 },
91 { 0x3a, 6, 64, M(_SC_LEVEL2_CACHE_SIZE), 196608 },
92 { 0x3b, 2, 64, M(_SC_LEVEL2_CACHE_SIZE), 131072 },
93 { 0x3c, 4, 64, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
94 { 0x3d, 6, 64, M(_SC_LEVEL2_CACHE_SIZE), 393216 },
95 { 0x3e, 4, 64, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
96 { 0x3f, 2, 64, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
97 { 0x41, 4, 32, M(_SC_LEVEL2_CACHE_SIZE), 131072 },
98 { 0x42, 4, 32, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
99 { 0x43, 4, 32, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
100 { 0x44, 4, 32, M(_SC_LEVEL2_CACHE_SIZE), 1048576 },
101 { 0x45, 4, 32, M(_SC_LEVEL2_CACHE_SIZE), 2097152 },
102 { 0x46, 4, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
103 { 0x47, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
104 { 0x48, 12, 64, M(_SC_LEVEL2_CACHE_SIZE), 3145728 },
105 { 0x49, 16, 64, M(_SC_LEVEL2_CACHE_SIZE), 4194304 },
106 { 0x4a, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 6291456 },
107 { 0x4b, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
108 { 0x4c, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
109 { 0x4d, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 16777216 },
110 { 0x4e, 24, 64, M(_SC_LEVEL2_CACHE_SIZE), 6291456 },
111 { 0x60, 8, 64, M(_SC_LEVEL1_DCACHE_SIZE), 16384 },
112 { 0x66, 4, 64, M(_SC_LEVEL1_DCACHE_SIZE), 8192 },
113 { 0x67, 4, 64, M(_SC_LEVEL1_DCACHE_SIZE), 16384 },
114 { 0x68, 4, 64, M(_SC_LEVEL1_DCACHE_SIZE), 32768 },
115 { 0x78, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 1048576 },
116 { 0x79, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 131072 },
117 { 0x7a, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
118 { 0x7b, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
119 { 0x7c, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 1048576 },
120 { 0x7d, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 2097152 },
121 { 0x7f, 2, 64, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
122 { 0x82, 8, 32, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
123 { 0x83, 8, 32, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
124 { 0x84, 8, 32, M(_SC_LEVEL2_CACHE_SIZE), 1048576 },
125 { 0x85, 8, 32, M(_SC_LEVEL2_CACHE_SIZE), 2097152 },
126 { 0x86, 4, 64, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
127 { 0x87, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 1048576 },
128 { 0xd0, 4, 64, M(_SC_LEVEL3_CACHE_SIZE), 524288 },
129 { 0xd1, 4, 64, M(_SC_LEVEL3_CACHE_SIZE), 1048576 },
130 { 0xd2, 4, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
131 { 0xd6, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 1048576 },
132 { 0xd7, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
133 { 0xd8, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
134 { 0xdc, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
135 { 0xdd, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
136 { 0xde, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
137 { 0xe2, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
138 { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
139 { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
140 { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
141 { 0xeb, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 18874368 },
142 { 0xec, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 25165824 },
144 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
147 static int
148 intel_02_known_compare (const void *p1, const void *p2)
150 const struct intel_02_cache_info *i1;
151 const struct intel_02_cache_info *i2;
153 i1 = (const struct intel_02_cache_info *) p1;
154 i2 = (const struct intel_02_cache_info *) p2;
156 if (i1->idx == i2->idx)
157 return 0;
159 return i1->idx < i2->idx ? -1 : 1;
163 static long int
164 __attribute__ ((noinline))
165 intel_check_word (int name, unsigned int value, bool *has_level_2,
166 bool *no_level_2_or_3)
168 if ((value & 0x80000000) != 0)
169 /* The register value is reserved. */
170 return 0;
172 /* Fold the name. The _SC_ constants are always in the order SIZE,
173 ASSOC, LINESIZE. */
174 int folded_rel_name = (M(name) / 3) * 3;
176 while (value != 0)
178 unsigned int byte = value & 0xff;
180 if (byte == 0x40)
182 *no_level_2_or_3 = true;
184 if (folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
185 /* No need to look further. */
186 break;
188 else if (byte == 0xff)
190 /* CPUID leaf 0x4 contains all the information. We need to
191 iterate over it. */
192 unsigned int eax;
193 unsigned int ebx;
194 unsigned int ecx;
195 unsigned int edx;
197 unsigned int round = 0;
198 while (1)
200 asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
201 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
202 : "0" (4), "2" (round));
204 enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f;
205 if (type == null)
206 /* That was the end. */
207 break;
209 unsigned int level = (eax >> 5) & 0x7;
211 if ((level == 1 && type == data
212 && folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE))
213 || (level == 1 && type == inst
214 && folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE))
215 || (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE))
216 || (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
217 || (level == 4 && folded_rel_name == M(_SC_LEVEL4_CACHE_SIZE)))
219 unsigned int offset = M(name) - folded_rel_name;
221 if (offset == 0)
222 /* Cache size. */
223 return (((ebx >> 22) + 1)
224 * (((ebx >> 12) & 0x3ff) + 1)
225 * ((ebx & 0xfff) + 1)
226 * (ecx + 1));
227 if (offset == 1)
228 return (ebx >> 22) + 1;
230 assert (offset == 2);
231 return (ebx & 0xfff) + 1;
234 ++round;
236 /* There is no other cache information anywhere else. */
237 break;
239 else
241 if (byte == 0x49 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
243 /* Intel reused this value. For family 15, model 6 it
244 specifies the 3rd level cache. Otherwise the 2nd
245 level cache. */
246 unsigned int eax;
247 unsigned int ebx;
248 unsigned int ecx;
249 unsigned int edx;
250 asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
251 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
252 : "0" (1));
254 unsigned int family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
255 unsigned int model = ((((eax >>16) & 0xf) << 4)
256 + ((eax >> 4) & 0xf));
257 if (family == 15 && model == 6)
259 /* The level 3 cache is encoded for this model like
260 the level 2 cache is for other models. Pretend
261 the caller asked for the level 2 cache. */
262 name = (_SC_LEVEL2_CACHE_SIZE
263 + (name - _SC_LEVEL3_CACHE_SIZE));
264 folded_rel_name = M(_SC_LEVEL2_CACHE_SIZE);
268 struct intel_02_cache_info *found;
269 struct intel_02_cache_info search;
271 search.idx = byte;
272 found = bsearch (&search, intel_02_known, nintel_02_known,
273 sizeof (intel_02_known[0]), intel_02_known_compare);
274 if (found != NULL)
276 if (found->rel_name == folded_rel_name)
278 unsigned int offset = M(name) - folded_rel_name;
280 if (offset == 0)
281 /* Cache size. */
282 return found->size;
283 if (offset == 1)
284 return found->assoc;
286 assert (offset == 2);
287 return found->linesize;
290 if (found->rel_name == M(_SC_LEVEL2_CACHE_SIZE))
291 *has_level_2 = true;
295 /* Next byte for the next round. */
296 value >>= 8;
299 /* Nothing found. */
300 return 0;
304 static long int __attribute__ ((noinline))
305 handle_intel (int name, unsigned int maxidx)
307 if (maxidx < 2)
309 // XXX Do such processors exist? When we know we can fill in some
310 // values.
311 return 0;
314 /* OK, we can use the CPUID instruction to get all info about the
315 caches. */
316 unsigned int cnt = 0;
317 unsigned int max = 1;
318 long int result = 0;
319 bool no_level_2_or_3 = false;
320 bool has_level_2 = false;
321 while (cnt++ < max)
323 unsigned int eax;
324 unsigned int ebx;
325 unsigned int ecx;
326 unsigned int edx;
327 asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
328 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
329 : "0" (2));
331 /* The low byte of EAX in the first round contain the number of
332 rounds we have to make. At least one, the one we are already
333 doing. */
334 if (cnt == 1)
336 max = eax & 0xff;
337 eax &= 0xffffff00;
340 /* Process the individual registers' value. */
341 result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
342 if (result != 0)
343 return result;
345 result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
346 if (result != 0)
347 return result;
349 result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
350 if (result != 0)
351 return result;
353 result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
354 if (result != 0)
355 return result;
358 if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
359 && no_level_2_or_3)
360 return -1;
362 return 0;
366 static long int __attribute__ ((noinline))
367 handle_amd (int name)
369 unsigned int eax;
370 unsigned int ebx;
371 unsigned int ecx;
372 unsigned int edx;
373 asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
374 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
375 : "0" (0x80000000));
377 if (name >= _SC_LEVEL3_CACHE_SIZE)
378 return 0;
380 unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
381 if (eax < fn)
382 return 0;
384 asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
385 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
386 : "0" (fn));
388 if (name < _SC_LEVEL1_DCACHE_SIZE)
390 name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
391 ecx = edx;
394 switch (name)
396 case _SC_LEVEL1_DCACHE_SIZE:
397 return (ecx >> 14) & 0x3fc00;
398 case _SC_LEVEL1_DCACHE_ASSOC:
399 ecx >>= 16;
400 if ((ecx & 0xff) == 0xff)
401 /* Fully associative. */
402 return (ecx << 2) & 0x3fc00;
403 return ecx & 0xff;
404 case _SC_LEVEL1_DCACHE_LINESIZE:
405 return ecx & 0xff;
406 case _SC_LEVEL2_CACHE_SIZE:
407 return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
408 case _SC_LEVEL2_CACHE_ASSOC:
409 ecx >>= 12;
410 switch (ecx & 0xf)
412 case 0:
413 case 1:
414 case 2:
415 case 4:
416 return ecx & 0xf;
417 case 6:
418 return 8;
419 case 8:
420 return 16;
421 case 0xf:
422 return (ecx << 6) & 0x3fffc00;
423 default:
424 return 0;
426 case _SC_LEVEL2_CACHE_LINESIZE:
427 return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
428 default:
429 assert (! "cannot happen");
431 return -1;
435 static int
436 i386_i486_test (void)
438 int eflags;
439 int ac;
440 asm volatile ("pushfl;\n\t"
441 "popl %0;\n\t"
442 "movl $0x240000, %1;\n\t"
443 "xorl %0, %1;\n\t"
444 "pushl %1;\n\t"
445 "popfl;\n\t"
446 "pushfl;\n\t"
447 "popl %1;\n\t"
448 "xorl %0, %1;\n\t"
449 "pushl %0;\n\t"
450 "popfl"
451 : "=r" (eflags), "=r" (ac));
453 return ac;
457 /* Get the value of the system variable NAME. */
458 long int
459 __sysconf (int name)
461 /* All the remainder, except the cache information, is handled in
462 the generic code. */
463 if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
464 return linux_sysconf (name);
466 /* Recognize i386 and compatible. These don't have any cache on
467 board. */
468 int ac = i386_i486_test ();
470 if (ac == 0)
471 /* This is an i386. */
472 // XXX Is this true for all brands?
473 return -1;
475 /* Detect i486, the last Intel processor without CPUID. */
476 if ((ac & (1 << 21)) == 0)
478 /* No CPUID. */
479 // XXX Fill in info about other brands. For now only Intel.
480 return handle_i486 (name);
483 /* Find out what brand of processor. */
484 unsigned int eax;
485 unsigned int ebx;
486 unsigned int ecx;
487 unsigned int edx;
488 asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
489 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
490 : "0" (0));
492 /* This spells out "GenuineIntel". */
493 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
494 return handle_intel (name, eax);
496 /* This spells out "AuthenticAMD". */
497 if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
498 return handle_amd (name);
500 // XXX Fill in more vendors.
502 /* CPU not known, we have no information. */
503 return 0;
506 /* Now the generic Linux version. */
507 #undef __sysconf
508 #define __sysconf static linux_sysconf
509 #include "../sysconf.c"