sysdeps/arm/fraiseexcpt.c

   1 /* Raise given exceptions.
   2    Copyright (C) 2004-2023 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library.  If not, see
  17    <https://www.gnu.org/licenses/>.  */
  18
  19 #include <fpu_control.h>
  20 #include <fenv.h>
  21 #include <float.h>
  22 #include <arm-features.h>
  23
  24
  25 int
  26 __feraiseexcept (int excepts)
  27 {
  28   /* Fail if a VFP unit isn't present unless nothing needs to be done.  */
  29   if (!ARM_HAVE_VFP)
  30     return (excepts != 0);
  31   else
  32     {
  33       fpu_control_t fpscr;
  34       const float fp_zero = 0.0, fp_one = 1.0, fp_max = FLT_MAX,
  35                   fp_min = FLT_MIN, fp_1e32 = 1.0e32f, fp_two = 2.0,
  36                   fp_three = 3.0;
  37
  38       /* Raise exceptions represented by EXPECTS.  But we must raise only
  39          one signal at a time.  It is important that if the overflow/underflow
  40          exception and the inexact exception are given at the same time,
  41          the overflow/underflow exception follows the inexact exception.  After
  42          each exception we read from the fpscr, to force the exception to be
  43          raised immediately.  */
  44
  45       /* There are additional complications because this file may be compiled
  46          without VFP support enabled, and we also can't assume that the
  47          assembler has VFP instructions enabled. To get around this we use the
  48          generic coprocessor mnemonics and avoid asking GCC to put float values
  49          in VFP registers.  */
  50
  51       /* First: invalid exception.  */
  52       if (FE_INVALID & excepts)
  53         __asm__ __volatile__ (
  54           "ldc p10, cr0, %1\n\t"                        /* flds s0, %1  */
  55           "cdp p10, 8, cr0, cr0, cr0, 0\n\t"            /* fdivs s0, s0, s0  */
  56           "mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr)  /* fmrx %0, fpscr  */
  57                                         : "m" (fp_zero)
  58                                         : "s0");
  59
  60       /* Next: division by zero.  */
  61       if (FE_DIVBYZERO & excepts)
  62         __asm__ __volatile__ (
  63           "ldc p10, cr0, %1\n\t"                        /* flds s0, %1  */
  64           "ldcl p10, cr0, %2\n\t"                       /* flds s1, %2  */
  65           "cdp p10, 8, cr0, cr0, cr0, 1\n\t"            /* fdivs s0, s0, s1  */
  66           "mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr)  /* fmrx %0, fpscr  */
  67                                         : "m" (fp_one), "m" (fp_zero)
  68                                         : "s0", "s1");
  69
  70       /* Next: overflow.  */
  71       if (FE_OVERFLOW & excepts)
  72         /* There's no way to raise overflow without also raising inexact.  */
  73         __asm__ __volatile__ (
  74           "ldc p10, cr0, %1\n\t"                        /* flds s0, %1  */
  75           "ldcl p10, cr0, %2\n\t"                       /* flds s1, %2  */
  76           "cdp p10, 3, cr0, cr0, cr0, 1\n\t"            /* fadds s0, s0, s1  */
  77           "mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr)  /* fmrx %0, fpscr  */
  78                                         : "m" (fp_max), "m" (fp_1e32)
  79                                         : "s0", "s1");
  80
  81       /* Next: underflow.  */
  82       if (FE_UNDERFLOW & excepts)
  83         __asm__ __volatile__ (
  84           "ldc p10, cr0, %1\n\t"                        /* flds s0, %1  */
  85           "ldcl p10, cr0, %2\n\t"                       /* flds s1, %2  */
  86           "cdp p10, 8, cr0, cr0, cr0, 1\n\t"            /* fdivs s0, s0, s1  */
  87           "mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr)  /* fmrx %0, fpscr  */
  88                                         : "m" (fp_min), "m" (fp_three)
  89                                         : "s0", "s1");
  90
  91       /* Last: inexact.  */
  92       if (FE_INEXACT & excepts)
  93         __asm__ __volatile__ (
  94           "ldc p10, cr0, %1\n\t"                        /* flds s0, %1  */
  95           "ldcl p10, cr0, %2\n\t"                       /* flds s1, %2  */
  96           "cdp p10, 8, cr0, cr0, cr0, 1\n\t"            /* fdivs s0, s0, s1  */
  97           "mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr)  /* fmrx %0, fpscr  */
  98                                         : "m" (fp_two), "m" (fp_three)
  99                                         : "s0", "s1");
 100
 101       /* Success.  */
 102       return 0;
 103     }
 104 }
 105 libm_hidden_def (__feraiseexcept)
 106 weak_alias (__feraiseexcept, feraiseexcept)
 107 libm_hidden_weak (feraiseexcept)