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* sysdeps/unix/sysv/linux/sparc/bits/pthreadtypes.h: Likewise.
[glibc.git] / stdlib / longlong.h
blob4e1931d8234f3a64ab764c6e01e0db0c35c52dc4
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
5
6 This file is part of the GNU C Library.
7
8 The GNU C Library is free software; you can redistribute it and/or
9 modify it under the terms of the GNU Lesser General Public
10 License as published by the Free Software Foundation; either
11 version 2.1 of the License, or (at your option) any later version.
12
13 The GNU C Library is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 Lesser General Public License for more details.
17
18 You should have received a copy of the GNU Lesser General Public
19 License along with the GNU C Library; if not, write to the Free
20 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
21 02111-1307 USA. */
22
23 /* You have to define the following before including this file:
24
25 UWtype -- An unsigned type, default type for operations (typically a "word")
26 UHWtype -- An unsigned type, at least half the size of UWtype.
27 UDWtype -- An unsigned type, at least twice as large a UWtype
28 W_TYPE_SIZE -- size in bits of UWtype
29
30 UQItype -- Unsigned 8 bit type.
31 SItype, USItype -- Signed and unsigned 32 bit types.
32 DItype, UDItype -- Signed and unsigned 64 bit types.
33
34 On a 32 bit machine UWtype should typically be USItype;
35 on a 64 bit machine, UWtype should typically be UDItype. */
36
37 #define __BITS4 (W_TYPE_SIZE / 4)
38 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
39 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
40 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
41
42 #ifndef W_TYPE_SIZE
43 #define W_TYPE_SIZE 32
44 #define UWtype USItype
45 #define UHWtype USItype
46 #define UDWtype UDItype
47 #endif
48
49 extern const UQItype __clz_tab[256];
50
51 /* Define auxiliary asm macros.
52
53 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
54 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
55 word product in HIGH_PROD and LOW_PROD.
56
57 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
58 UDWtype product. This is just a variant of umul_ppmm.
59
60 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
61 denominator) divides a UDWtype, composed by the UWtype integers
62 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
63 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
64 than DENOMINATOR for correct operation. If, in addition, the most
65 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
66 UDIV_NEEDS_NORMALIZATION is defined to 1.
67
68 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
69 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
70 is rounded towards 0.
71
72 5) count_leading_zeros(count, x) counts the number of zero-bits from the
73 msb to the first nonzero bit in the UWtype X. This is the number of
74 steps X needs to be shifted left to set the msb. Undefined for X == 0,
75 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
76
77 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
78 from the least significant end.
79
80 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
81 high_addend_2, low_addend_2) adds two UWtype integers, composed by
82 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
83 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
84 (i.e. carry out) is not stored anywhere, and is lost.
85
86 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
87 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
88 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
89 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
90 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
91 and is lost.
92
93 If any of these macros are left undefined for a particular CPU,
94 C macros are used. */
95
96 /* The CPUs come in alphabetical order below.
97
98 Please add support for more CPUs here, or improve the current support
99 for the CPUs below!
100 (E.g. WE32100, IBM360.) */
101
102 #if defined (__GNUC__) && !defined (NO_ASM)
103
104 /* We sometimes need to clobber "cc" with gcc2, but that would not be
105 understood by gcc1. Use cpp to avoid major code duplication. */
106 #if __GNUC__ < 2
107 #define __CLOBBER_CC
108 #define __AND_CLOBBER_CC
109 #else /* __GNUC__ >= 2 */
110 #define __CLOBBER_CC : "cc"
111 #define __AND_CLOBBER_CC , "cc"
112 #endif /* __GNUC__ < 2 */
113
114 #if defined (__alpha) && W_TYPE_SIZE == 64
115 #define umul_ppmm(ph, pl, m0, m1) \
116 do { \
117 UDItype __m0 = (m0), __m1 = (m1); \
118 (ph) = __builtin_alpha_umulh (__m0, __m1); \
119 (pl) = __m0 * __m1; \
120 } while (0)
121 #define UMUL_TIME 46
122 #ifndef LONGLONG_STANDALONE
123 #define udiv_qrnnd(q, r, n1, n0, d) \
124 do { UDItype __r; \
125 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
126 (r) = __r; \
127 } while (0)
128 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
129 #define UDIV_TIME 220
130 #endif /* LONGLONG_STANDALONE */
131 #ifdef __alpha_cix__
132 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
133 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
134 #define COUNT_LEADING_ZEROS_0 64
135 #else
136 #define count_leading_zeros(COUNT,X) \
137 do { \
138 UDItype __xr = (X), __t, __a; \
139 __t = __builtin_alpha_cmpbge (0, __xr); \
140 __a = __clz_tab[__t ^ 0xff] - 1; \
141 __t = __builtin_alpha_extbl (__xr, __a); \
142 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
143 } while (0)
144 #define count_trailing_zeros(COUNT,X) \
145 do { \
146 UDItype __xr = (X), __t, __a; \
147 __t = __builtin_alpha_cmpbge (0, __xr); \
148 __t = ~__t & -~__t; \
149 __a = ((__t & 0xCC) != 0) * 2; \
150 __a += ((__t & 0xF0) != 0) * 4; \
151 __a += ((__t & 0xAA) != 0); \
152 __t = __builtin_alpha_extbl (__xr, __a); \
153 __a <<= 3; \
154 __t &= -__t; \
155 __a += ((__t & 0xCC) != 0) * 2; \
156 __a += ((__t & 0xF0) != 0) * 4; \
157 __a += ((__t & 0xAA) != 0); \
158 (COUNT) = __a; \
159 } while (0)
160 #endif /* __alpha_cix__ */
161 #endif /* __alpha */
162
163 #if defined (__arc__) && W_TYPE_SIZE == 32
164 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
165 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
166 : "=r" ((USItype) (sh)), \
167 "=&r" ((USItype) (sl)) \
168 : "%r" ((USItype) (ah)), \
169 "rIJ" ((USItype) (bh)), \
170 "%r" ((USItype) (al)), \
171 "rIJ" ((USItype) (bl)))
172 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
173 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
174 : "=r" ((USItype) (sh)), \
175 "=&r" ((USItype) (sl)) \
176 : "r" ((USItype) (ah)), \
177 "rIJ" ((USItype) (bh)), \
178 "r" ((USItype) (al)), \
179 "rIJ" ((USItype) (bl)))
180 /* Call libgcc routine. */
181 #define umul_ppmm(w1, w0, u, v) \
182 do { \
183 DWunion __w; \
184 __w.ll = __umulsidi3 (u, v); \
185 w1 = __w.s.high; \
186 w0 = __w.s.low; \
187 } while (0)
188 #define __umulsidi3 __umulsidi3
189 UDItype __umulsidi3 (USItype, USItype);
190 #endif
191
192 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
193 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
194 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
195 : "=r" ((USItype) (sh)), \
196 "=&r" ((USItype) (sl)) \
197 : "%r" ((USItype) (ah)), \
198 "rI" ((USItype) (bh)), \
199 "%r" ((USItype) (al)), \
200 "rI" ((USItype) (bl)) __CLOBBER_CC)
201 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
202 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
203 : "=r" ((USItype) (sh)), \
204 "=&r" ((USItype) (sl)) \
205 : "r" ((USItype) (ah)), \
206 "rI" ((USItype) (bh)), \
207 "r" ((USItype) (al)), \
208 "rI" ((USItype) (bl)) __CLOBBER_CC)
209 #define umul_ppmm(xh, xl, a, b) \
210 {register USItype __t0, __t1, __t2; \
211 __asm__ ("%@ Inlined umul_ppmm\n" \
212 " mov %2, %5, lsr #16\n" \
213 " mov %0, %6, lsr #16\n" \
214 " bic %3, %5, %2, lsl #16\n" \
215 " bic %4, %6, %0, lsl #16\n" \
216 " mul %1, %3, %4\n" \
217 " mul %4, %2, %4\n" \
218 " mul %3, %0, %3\n" \
219 " mul %0, %2, %0\n" \
220 " adds %3, %4, %3\n" \
221 " addcs %0, %0, #65536\n" \
222 " adds %1, %1, %3, lsl #16\n" \
223 " adc %0, %0, %3, lsr #16" \
224 : "=&r" ((USItype) (xh)), \
225 "=r" ((USItype) (xl)), \
226 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
227 : "r" ((USItype) (a)), \
228 "r" ((USItype) (b)) __CLOBBER_CC );}
229 #define UMUL_TIME 20
230 #define UDIV_TIME 100
231 #endif /* __arm__ */
232
233 #if defined (__hppa) && W_TYPE_SIZE == 32
234 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
235 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
236 : "=r" ((USItype) (sh)), \
237 "=&r" ((USItype) (sl)) \
238 : "%rM" ((USItype) (ah)), \
239 "rM" ((USItype) (bh)), \
240 "%rM" ((USItype) (al)), \
241 "rM" ((USItype) (bl)))
242 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
243 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
244 : "=r" ((USItype) (sh)), \
245 "=&r" ((USItype) (sl)) \
246 : "rM" ((USItype) (ah)), \
247 "rM" ((USItype) (bh)), \
248 "rM" ((USItype) (al)), \
249 "rM" ((USItype) (bl)))
250 #if defined (_PA_RISC1_1)
251 #define umul_ppmm(w1, w0, u, v) \
252 do { \
253 union \
254 { \
255 UDItype __f; \
256 struct {USItype __w1, __w0;} __w1w0; \
257 } __t; \
258 __asm__ ("xmpyu %1,%2,%0" \
259 : "=x" (__t.__f) \
260 : "x" ((USItype) (u)), \
261 "x" ((USItype) (v))); \
262 (w1) = __t.__w1w0.__w1; \
263 (w0) = __t.__w1w0.__w0; \
264 } while (0)
265 #define UMUL_TIME 8
266 #else
267 #define UMUL_TIME 30
268 #endif
269 #define UDIV_TIME 40
270 #define count_leading_zeros(count, x) \
271 do { \
272 USItype __tmp; \
273 __asm__ ( \
274 "ldi 1,%0\n" \
275 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
276 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
277 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
278 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
279 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
280 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
281 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
282 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
283 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
284 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
285 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
286 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
287 " extru %1,30,1,%1 ; Extract bit 1.\n" \
288 " sub %0,%1,%0 ; Subtract it.\n" \
289 : "=r" (count), "=r" (__tmp) : "1" (x)); \
290 } while (0)
291 #endif
292
293 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
294 #define smul_ppmm(xh, xl, m0, m1) \
295 do { \
296 union {DItype __ll; \
297 struct {USItype __h, __l;} __i; \
298 } __x; \
299 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
300 : "=&r" (__x.__ll) \
301 : "r" (m0), "r" (m1)); \
302 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
303 } while (0)
304 #define sdiv_qrnnd(q, r, n1, n0, d) \
305 do { \
306 union {DItype __ll; \
307 struct {USItype __h, __l;} __i; \
308 } __x; \
309 __x.__i.__h = n1; __x.__i.__l = n0; \
310 __asm__ ("dr %0,%2" \
311 : "=r" (__x.__ll) \
312 : "0" (__x.__ll), "r" (d)); \
313 (q) = __x.__i.__l; (r) = __x.__i.__h; \
314 } while (0)
315 #endif
316
317 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
318 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
319 __asm__ ("addl %5,%1\n\tadcl %3,%0" \
320 : "=r" ((USItype) (sh)), \
321 "=&r" ((USItype) (sl)) \
322 : "%0" ((USItype) (ah)), \
323 "g" ((USItype) (bh)), \
324 "%1" ((USItype) (al)), \
325 "g" ((USItype) (bl)))
326 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
327 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
328 : "=r" ((USItype) (sh)), \
329 "=&r" ((USItype) (sl)) \
330 : "0" ((USItype) (ah)), \
331 "g" ((USItype) (bh)), \
332 "1" ((USItype) (al)), \
333 "g" ((USItype) (bl)))
334 #define umul_ppmm(w1, w0, u, v) \
335 __asm__ ("mull %3" \
336 : "=a" ((USItype) (w0)), \
337 "=d" ((USItype) (w1)) \
338 : "%0" ((USItype) (u)), \
339 "rm" ((USItype) (v)))
340 #define udiv_qrnnd(q, r, n1, n0, dv) \
341 __asm__ ("divl %4" \
342 : "=a" ((USItype) (q)), \
343 "=d" ((USItype) (r)) \
344 : "0" ((USItype) (n0)), \
345 "1" ((USItype) (n1)), \
346 "rm" ((USItype) (dv)))
347 #define count_leading_zeros(count, x) \
348 do { \
349 USItype __cbtmp; \
350 __asm__ ("bsrl %1,%0" \
351 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \
352 (count) = __cbtmp ^ 31; \
353 } while (0)
354 #define count_trailing_zeros(count, x) \
355 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
356 #define UMUL_TIME 40
357 #define UDIV_TIME 40
358 #endif /* 80x86 */
359
360 #if defined (__i960__) && W_TYPE_SIZE == 32
361 #define umul_ppmm(w1, w0, u, v) \
362 ({union {UDItype __ll; \
363 struct {USItype __l, __h;} __i; \
364 } __xx; \
365 __asm__ ("emul %2,%1,%0" \
366 : "=d" (__xx.__ll) \
367 : "%dI" ((USItype) (u)), \
368 "dI" ((USItype) (v))); \
369 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
370 #define __umulsidi3(u, v) \
371 ({UDItype __w; \
372 __asm__ ("emul %2,%1,%0" \
373 : "=d" (__w) \
374 : "%dI" ((USItype) (u)), \
375 "dI" ((USItype) (v))); \
376 __w; })
377 #endif /* __i960__ */
378
379 #if defined (__M32R__) && W_TYPE_SIZE == 32
380 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
381 /* The cmp clears the condition bit. */ \
382 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
383 : "=r" ((USItype) (sh)), \
384 "=&r" ((USItype) (sl)) \
385 : "0" ((USItype) (ah)), \
386 "r" ((USItype) (bh)), \
387 "1" ((USItype) (al)), \
388 "r" ((USItype) (bl)) \
389 : "cbit")
390 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
391 /* The cmp clears the condition bit. */ \
392 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
393 : "=r" ((USItype) (sh)), \
394 "=&r" ((USItype) (sl)) \
395 : "0" ((USItype) (ah)), \
396 "r" ((USItype) (bh)), \
397 "1" ((USItype) (al)), \
398 "r" ((USItype) (bl)) \
399 : "cbit")
400 #endif /* __M32R__ */
401
402 #if defined (__mc68000__) && W_TYPE_SIZE == 32
403 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
404 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
405 : "=d" ((USItype) (sh)), \
406 "=&d" ((USItype) (sl)) \
407 : "%0" ((USItype) (ah)), \
408 "d" ((USItype) (bh)), \
409 "%1" ((USItype) (al)), \
410 "g" ((USItype) (bl)))
411 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
412 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
413 : "=d" ((USItype) (sh)), \
414 "=&d" ((USItype) (sl)) \
415 : "0" ((USItype) (ah)), \
416 "d" ((USItype) (bh)), \
417 "1" ((USItype) (al)), \
418 "g" ((USItype) (bl)))
419
420 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
421 #if (defined (__mc68020__) && !defined (__mc68060__))
422 #define umul_ppmm(w1, w0, u, v) \
423 __asm__ ("mulu%.l %3,%1:%0" \
424 : "=d" ((USItype) (w0)), \
425 "=d" ((USItype) (w1)) \
426 : "%0" ((USItype) (u)), \
427 "dmi" ((USItype) (v)))
428 #define UMUL_TIME 45
429 #define udiv_qrnnd(q, r, n1, n0, d) \
430 __asm__ ("divu%.l %4,%1:%0" \
431 : "=d" ((USItype) (q)), \
432 "=d" ((USItype) (r)) \
433 : "0" ((USItype) (n0)), \
434 "1" ((USItype) (n1)), \
435 "dmi" ((USItype) (d)))
436 #define UDIV_TIME 90
437 #define sdiv_qrnnd(q, r, n1, n0, d) \
438 __asm__ ("divs%.l %4,%1:%0" \
439 : "=d" ((USItype) (q)), \
440 "=d" ((USItype) (r)) \
441 : "0" ((USItype) (n0)), \
442 "1" ((USItype) (n1)), \
443 "dmi" ((USItype) (d)))
444
445 #elif defined (__mcoldfire__) /* not mc68020 */
446
447 #define umul_ppmm(xh, xl, a, b) \
448 __asm__ ("| Inlined umul_ppmm\n" \
449 " move%.l %2,%/d0\n" \
450 " move%.l %3,%/d1\n" \
451 " move%.l %/d0,%/d2\n" \
452 " swap %/d0\n" \
453 " move%.l %/d1,%/d3\n" \
454 " swap %/d1\n" \
455 " move%.w %/d2,%/d4\n" \
456 " mulu %/d3,%/d4\n" \
457 " mulu %/d1,%/d2\n" \
458 " mulu %/d0,%/d3\n" \
459 " mulu %/d0,%/d1\n" \
460 " move%.l %/d4,%/d0\n" \
461 " clr%.w %/d0\n" \
462 " swap %/d0\n" \
463 " add%.l %/d0,%/d2\n" \
464 " add%.l %/d3,%/d2\n" \
465 " jcc 1f\n" \
466 " add%.l %#65536,%/d1\n" \
467 "1: swap %/d2\n" \
468 " moveq %#0,%/d0\n" \
469 " move%.w %/d2,%/d0\n" \
470 " move%.w %/d4,%/d2\n" \
471 " move%.l %/d2,%1\n" \
472 " add%.l %/d1,%/d0\n" \
473 " move%.l %/d0,%0" \
474 : "=g" ((USItype) (xh)), \
475 "=g" ((USItype) (xl)) \
476 : "g" ((USItype) (a)), \
477 "g" ((USItype) (b)) \
478 : "d0", "d1", "d2", "d3", "d4")
479 #define UMUL_TIME 100
480 #define UDIV_TIME 400
481 #else /* not ColdFire */
482 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
483 #define umul_ppmm(xh, xl, a, b) \
484 __asm__ ("| Inlined umul_ppmm\n" \
485 " move%.l %2,%/d0\n" \
486 " move%.l %3,%/d1\n" \
487 " move%.l %/d0,%/d2\n" \
488 " swap %/d0\n" \
489 " move%.l %/d1,%/d3\n" \
490 " swap %/d1\n" \
491 " move%.w %/d2,%/d4\n" \
492 " mulu %/d3,%/d4\n" \
493 " mulu %/d1,%/d2\n" \
494 " mulu %/d0,%/d3\n" \
495 " mulu %/d0,%/d1\n" \
496 " move%.l %/d4,%/d0\n" \
497 " eor%.w %/d0,%/d0\n" \
498 " swap %/d0\n" \
499 " add%.l %/d0,%/d2\n" \
500 " add%.l %/d3,%/d2\n" \
501 " jcc 1f\n" \
502 " add%.l %#65536,%/d1\n" \
503 "1: swap %/d2\n" \
504 " moveq %#0,%/d0\n" \
505 " move%.w %/d2,%/d0\n" \
506 " move%.w %/d4,%/d2\n" \
507 " move%.l %/d2,%1\n" \
508 " add%.l %/d1,%/d0\n" \
509 " move%.l %/d0,%0" \
510 : "=g" ((USItype) (xh)), \
511 "=g" ((USItype) (xl)) \
512 : "g" ((USItype) (a)), \
513 "g" ((USItype) (b)) \
514 : "d0", "d1", "d2", "d3", "d4")
515 #define UMUL_TIME 100
516 #define UDIV_TIME 400
517
518 #endif /* not mc68020 */
519
520 /* The '020, '030, '040 and '060 have bitfield insns.
521 cpu32 disguises as a 68020, but lacks them. */
522 #if defined (__mc68020__) && !defined (__mcpu32__)
523 #define count_leading_zeros(count, x) \
524 __asm__ ("bfffo %1{%b2:%b2},%0" \
525 : "=d" ((USItype) (count)) \
526 : "od" ((USItype) (x)), "n" (0))
527 #endif
528 #endif /* mc68000 */
529
530 #if defined (__m88000__) && W_TYPE_SIZE == 32
531 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
532 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
533 : "=r" ((USItype) (sh)), \
534 "=&r" ((USItype) (sl)) \
535 : "%rJ" ((USItype) (ah)), \
536 "rJ" ((USItype) (bh)), \
537 "%rJ" ((USItype) (al)), \
538 "rJ" ((USItype) (bl)))
539 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
540 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
541 : "=r" ((USItype) (sh)), \
542 "=&r" ((USItype) (sl)) \
543 : "rJ" ((USItype) (ah)), \
544 "rJ" ((USItype) (bh)), \
545 "rJ" ((USItype) (al)), \
546 "rJ" ((USItype) (bl)))
547 #define count_leading_zeros(count, x) \
548 do { \
549 USItype __cbtmp; \
550 __asm__ ("ff1 %0,%1" \
551 : "=r" (__cbtmp) \
552 : "r" ((USItype) (x))); \
553 (count) = __cbtmp ^ 31; \
554 } while (0)
555 #define COUNT_LEADING_ZEROS_0 63 /* sic */
556 #if defined (__mc88110__)
557 #define umul_ppmm(wh, wl, u, v) \
558 do { \
559 union {UDItype __ll; \
560 struct {USItype __h, __l;} __i; \
561 } __xx; \
562 __asm__ ("mulu.d %0,%1,%2" \
563 : "=r" (__xx.__ll) \
564 : "r" ((USItype) (u)), \
565 "r" ((USItype) (v))); \
566 (wh) = __xx.__i.__h; \
567 (wl) = __xx.__i.__l; \
568 } while (0)
569 #define udiv_qrnnd(q, r, n1, n0, d) \
570 ({union {UDItype __ll; \
571 struct {USItype __h, __l;} __i; \
572 } __xx; \
573 USItype __q; \
574 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
575 __asm__ ("divu.d %0,%1,%2" \
576 : "=r" (__q) \
577 : "r" (__xx.__ll), \
578 "r" ((USItype) (d))); \
579 (r) = (n0) - __q * (d); (q) = __q; })
580 #define UMUL_TIME 5
581 #define UDIV_TIME 25
582 #else
583 #define UMUL_TIME 17
584 #define UDIV_TIME 150
585 #endif /* __mc88110__ */
586 #endif /* __m88000__ */
587
588 #if defined (__mips__) && W_TYPE_SIZE == 32
589 #define umul_ppmm(w1, w0, u, v) \
590 __asm__ ("multu %2,%3" \
591 : "=l" ((USItype) (w0)), \
592 "=h" ((USItype) (w1)) \
593 : "d" ((USItype) (u)), \
594 "d" ((USItype) (v)))
595 #define UMUL_TIME 10
596 #define UDIV_TIME 100
597 #endif /* __mips__ */
598
599 #if defined (__ns32000__) && W_TYPE_SIZE == 32
600 #define umul_ppmm(w1, w0, u, v) \
601 ({union {UDItype __ll; \
602 struct {USItype __l, __h;} __i; \
603 } __xx; \
604 __asm__ ("meid %2,%0" \
605 : "=g" (__xx.__ll) \
606 : "%0" ((USItype) (u)), \
607 "g" ((USItype) (v))); \
608 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
609 #define __umulsidi3(u, v) \
610 ({UDItype __w; \
611 __asm__ ("meid %2,%0" \
612 : "=g" (__w) \
613 : "%0" ((USItype) (u)), \
614 "g" ((USItype) (v))); \
615 __w; })
616 #define udiv_qrnnd(q, r, n1, n0, d) \
617 ({union {UDItype __ll; \
618 struct {USItype __l, __h;} __i; \
619 } __xx; \
620 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
621 __asm__ ("deid %2,%0" \
622 : "=g" (__xx.__ll) \
623 : "0" (__xx.__ll), \
624 "g" ((USItype) (d))); \
625 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
626 #define count_trailing_zeros(count,x) \
627 do { \
628 __asm__ ("ffsd %2,%0" \
629 : "=r" ((USItype) (count)) \
630 : "0" ((USItype) 0), \
631 "r" ((USItype) (x))); \
632 } while (0)
633 #endif /* __ns32000__ */
634
635 /* FIXME: We should test _IBMR2 here when we add assembly support for the
636 system vendor compilers.
637 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
638 enough, since that hits ARM and m68k too. */
639 #if (defined (_ARCH_PPC) /* AIX */ \
640 || defined (_ARCH_PWR) /* AIX */ \
641 || defined (_ARCH_COM) /* AIX */ \
642 || defined (__powerpc__) /* gcc */ \
643 || defined (__POWERPC__) /* BEOS */ \
644 || defined (__ppc__) /* Darwin */ \
645 || defined (PPC) /* GNU/Linux, SysV */ \
646 ) && W_TYPE_SIZE == 32
647 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
648 do { \
649 if (__builtin_constant_p (bh) && (bh) == 0) \
650 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
651 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
652 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
653 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
654 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
655 else \
656 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
657 : "=r" (sh), "=&r" (sl) \
658 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
659 } while (0)
660 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
661 do { \
662 if (__builtin_constant_p (ah) && (ah) == 0) \
663 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
664 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
665 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
666 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
667 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
668 else if (__builtin_constant_p (bh) && (bh) == 0) \
669 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
670 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
671 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
672 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
673 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
674 else \
675 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
676 : "=r" (sh), "=&r" (sl) \
677 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
678 } while (0)
679 #define count_leading_zeros(count, x) \
680 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
681 #define COUNT_LEADING_ZEROS_0 32
682 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
683 || defined (__ppc__) || defined (PPC)
684 #define umul_ppmm(ph, pl, m0, m1) \
685 do { \
686 USItype __m0 = (m0), __m1 = (m1); \
687 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
688 (pl) = __m0 * __m1; \
689 } while (0)
690 #define UMUL_TIME 15
691 #define smul_ppmm(ph, pl, m0, m1) \
692 do { \
693 SItype __m0 = (m0), __m1 = (m1); \
694 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
695 (pl) = __m0 * __m1; \
696 } while (0)
697 #define SMUL_TIME 14
698 #define UDIV_TIME 120
699 #elif defined (_ARCH_PWR)
700 #define UMUL_TIME 8
701 #define smul_ppmm(xh, xl, m0, m1) \
702 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
703 #define SMUL_TIME 4
704 #define sdiv_qrnnd(q, r, nh, nl, d) \
705 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
706 #define UDIV_TIME 100
707 #endif
708 #endif /* 32-bit POWER architecture variants. */
709
710 /* We should test _IBMR2 here when we add assembly support for the system
711 vendor compilers. */
712 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
713 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
714 do { \
715 if (__builtin_constant_p (bh) && (bh) == 0) \
716 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
717 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
718 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
719 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
720 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
721 else \
722 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
723 : "=r" (sh), "=&r" (sl) \
724 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
725 } while (0)
726 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
727 do { \
728 if (__builtin_constant_p (ah) && (ah) == 0) \
729 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
730 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
731 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
732 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
733 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
734 else if (__builtin_constant_p (bh) && (bh) == 0) \
735 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
736 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
737 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
738 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
739 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
740 else \
741 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
742 : "=r" (sh), "=&r" (sl) \
743 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
744 } while (0)
745 #define count_leading_zeros(count, x) \
746 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
747 #define COUNT_LEADING_ZEROS_0 64
748 #define umul_ppmm(ph, pl, m0, m1) \
749 do { \
750 UDItype __m0 = (m0), __m1 = (m1); \
751 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
752 (pl) = __m0 * __m1; \
753 } while (0)
754 #define UMUL_TIME 15
755 #define smul_ppmm(ph, pl, m0, m1) \
756 do { \
757 DItype __m0 = (m0), __m1 = (m1); \
758 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
759 (pl) = __m0 * __m1; \
760 } while (0)
761 #define SMUL_TIME 14 /* ??? */
762 #define UDIV_TIME 120 /* ??? */
763 #endif /* 64-bit PowerPC. */
764
765 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
766 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
767 __asm__ ("a %1,%5\n\tae %0,%3" \
768 : "=r" ((USItype) (sh)), \
769 "=&r" ((USItype) (sl)) \
770 : "%0" ((USItype) (ah)), \
771 "r" ((USItype) (bh)), \
772 "%1" ((USItype) (al)), \
773 "r" ((USItype) (bl)))
774 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
775 __asm__ ("s %1,%5\n\tse %0,%3" \
776 : "=r" ((USItype) (sh)), \
777 "=&r" ((USItype) (sl)) \
778 : "0" ((USItype) (ah)), \
779 "r" ((USItype) (bh)), \
780 "1" ((USItype) (al)), \
781 "r" ((USItype) (bl)))
782 #define umul_ppmm(ph, pl, m0, m1) \
783 do { \
784 USItype __m0 = (m0), __m1 = (m1); \
785 __asm__ ( \
786 "s r2,r2\n" \
787 " mts r10,%2\n" \
788 " m r2,%3\n" \
789 " m r2,%3\n" \
790 " m r2,%3\n" \
791 " m r2,%3\n" \
792 " m r2,%3\n" \
793 " m r2,%3\n" \
794 " m r2,%3\n" \
795 " m r2,%3\n" \
796 " m r2,%3\n" \
797 " m r2,%3\n" \
798 " m r2,%3\n" \
799 " m r2,%3\n" \
800 " m r2,%3\n" \
801 " m r2,%3\n" \
802 " m r2,%3\n" \
803 " m r2,%3\n" \
804 " cas %0,r2,r0\n" \
805 " mfs r10,%1" \
806 : "=r" ((USItype) (ph)), \
807 "=r" ((USItype) (pl)) \
808 : "%r" (__m0), \
809 "r" (__m1) \
810 : "r2"); \
811 (ph) += ((((SItype) __m0 >> 31) & __m1) \
812 + (((SItype) __m1 >> 31) & __m0)); \
813 } while (0)
814 #define UMUL_TIME 20
815 #define UDIV_TIME 200
816 #define count_leading_zeros(count, x) \
817 do { \
818 if ((x) >= 0x10000) \
819 __asm__ ("clz %0,%1" \
820 : "=r" ((USItype) (count)) \
821 : "r" ((USItype) (x) >> 16)); \
822 else \
823 { \
824 __asm__ ("clz %0,%1" \
825 : "=r" ((USItype) (count)) \
826 : "r" ((USItype) (x))); \
827 (count) += 16; \
828 } \
829 } while (0)
830 #endif
831
832 #if defined (__sh2__) && W_TYPE_SIZE == 32
833 #define umul_ppmm(w1, w0, u, v) \
834 __asm__ ( \
835 "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
836 : "=r" ((USItype)(w1)), \
837 "=r" ((USItype)(w0)) \
838 : "r" ((USItype)(u)), \
839 "r" ((USItype)(v)) \
840 : "macl", "mach")
841 #define UMUL_TIME 5
842 #endif
843
844 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
845 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
846 #define count_leading_zeros(count, x) \
847 do \
848 { \
849 UDItype x_ = (USItype)(x); \
850 SItype c_; \
851 \
852 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
853 (count) = c_ - 31; \
854 } \
855 while (0)
856 #define COUNT_LEADING_ZEROS_0 32
857 #endif
858
859 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
860 && W_TYPE_SIZE == 32
861 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
862 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
863 : "=r" ((USItype) (sh)), \
864 "=&r" ((USItype) (sl)) \
865 : "%rJ" ((USItype) (ah)), \
866 "rI" ((USItype) (bh)), \
867 "%rJ" ((USItype) (al)), \
868 "rI" ((USItype) (bl)) \
869 __CLOBBER_CC)
870 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
871 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
872 : "=r" ((USItype) (sh)), \
873 "=&r" ((USItype) (sl)) \
874 : "rJ" ((USItype) (ah)), \
875 "rI" ((USItype) (bh)), \
876 "rJ" ((USItype) (al)), \
877 "rI" ((USItype) (bl)) \
878 __CLOBBER_CC)
879 #if defined (__sparc_v8__)
880 #define umul_ppmm(w1, w0, u, v) \
881 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
882 : "=r" ((USItype) (w1)), \
883 "=r" ((USItype) (w0)) \
884 : "r" ((USItype) (u)), \
885 "r" ((USItype) (v)))
886 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
887 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
888 : "=&r" ((USItype) (__q)), \
889 "=&r" ((USItype) (__r)) \
890 : "r" ((USItype) (__n1)), \
891 "r" ((USItype) (__n0)), \
892 "r" ((USItype) (__d)))
893 #else
894 #if defined (__sparclite__)
895 /* This has hardware multiply but not divide. It also has two additional
896 instructions scan (ffs from high bit) and divscc. */
897 #define umul_ppmm(w1, w0, u, v) \
898 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
899 : "=r" ((USItype) (w1)), \
900 "=r" ((USItype) (w0)) \
901 : "r" ((USItype) (u)), \
902 "r" ((USItype) (v)))
903 #define udiv_qrnnd(q, r, n1, n0, d) \
904 __asm__ ("! Inlined udiv_qrnnd\n" \
905 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
906 " tst %%g0\n" \
907 " divscc %3,%4,%%g1\n" \
908 " divscc %%g1,%4,%%g1\n" \
909 " divscc %%g1,%4,%%g1\n" \
910 " divscc %%g1,%4,%%g1\n" \
911 " divscc %%g1,%4,%%g1\n" \
912 " divscc %%g1,%4,%%g1\n" \
913 " divscc %%g1,%4,%%g1\n" \
914 " divscc %%g1,%4,%%g1\n" \
915 " divscc %%g1,%4,%%g1\n" \
916 " divscc %%g1,%4,%%g1\n" \
917 " divscc %%g1,%4,%%g1\n" \
918 " divscc %%g1,%4,%%g1\n" \
919 " divscc %%g1,%4,%%g1\n" \
920 " divscc %%g1,%4,%%g1\n" \
921 " divscc %%g1,%4,%%g1\n" \
922 " divscc %%g1,%4,%%g1\n" \
923 " divscc %%g1,%4,%%g1\n" \
924 " divscc %%g1,%4,%%g1\n" \
925 " divscc %%g1,%4,%%g1\n" \
926 " divscc %%g1,%4,%%g1\n" \
927 " divscc %%g1,%4,%%g1\n" \
928 " divscc %%g1,%4,%%g1\n" \
929 " divscc %%g1,%4,%%g1\n" \
930 " divscc %%g1,%4,%%g1\n" \
931 " divscc %%g1,%4,%%g1\n" \
932 " divscc %%g1,%4,%%g1\n" \
933 " divscc %%g1,%4,%%g1\n" \
934 " divscc %%g1,%4,%%g1\n" \
935 " divscc %%g1,%4,%%g1\n" \
936 " divscc %%g1,%4,%%g1\n" \
937 " divscc %%g1,%4,%%g1\n" \
938 " divscc %%g1,%4,%0\n" \
939 " rd %%y,%1\n" \
940 " bl,a 1f\n" \
941 " add %1,%4,%1\n" \
942 "1: ! End of inline udiv_qrnnd" \
943 : "=r" ((USItype) (q)), \
944 "=r" ((USItype) (r)) \
945 : "r" ((USItype) (n1)), \
946 "r" ((USItype) (n0)), \
947 "rI" ((USItype) (d)) \
948 : "g1" __AND_CLOBBER_CC)
949 #define UDIV_TIME 37
950 #define count_leading_zeros(count, x) \
951 do { \
952 __asm__ ("scan %1,1,%0" \
953 : "=r" ((USItype) (count)) \
954 : "r" ((USItype) (x))); \
955 } while (0)
956 /* Early sparclites return 63 for an argument of 0, but they warn that future
957 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
958 undefined. */
959 #else
960 /* SPARC without integer multiplication and divide instructions.
961 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
962 #define umul_ppmm(w1, w0, u, v) \
963 __asm__ ("! Inlined umul_ppmm\n" \
964 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
965 " sra %3,31,%%o5 ! Don't move this insn\n" \
966 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
967 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
968 " mulscc %%g1,%3,%%g1\n" \
969 " mulscc %%g1,%3,%%g1\n" \
970 " mulscc %%g1,%3,%%g1\n" \
971 " mulscc %%g1,%3,%%g1\n" \
972 " mulscc %%g1,%3,%%g1\n" \
973 " mulscc %%g1,%3,%%g1\n" \
974 " mulscc %%g1,%3,%%g1\n" \
975 " mulscc %%g1,%3,%%g1\n" \
976 " mulscc %%g1,%3,%%g1\n" \
977 " mulscc %%g1,%3,%%g1\n" \
978 " mulscc %%g1,%3,%%g1\n" \
979 " mulscc %%g1,%3,%%g1\n" \
980 " mulscc %%g1,%3,%%g1\n" \
981 " mulscc %%g1,%3,%%g1\n" \
982 " mulscc %%g1,%3,%%g1\n" \
983 " mulscc %%g1,%3,%%g1\n" \
984 " mulscc %%g1,%3,%%g1\n" \
985 " mulscc %%g1,%3,%%g1\n" \
986 " mulscc %%g1,%3,%%g1\n" \
987 " mulscc %%g1,%3,%%g1\n" \
988 " mulscc %%g1,%3,%%g1\n" \
989 " mulscc %%g1,%3,%%g1\n" \
990 " mulscc %%g1,%3,%%g1\n" \
991 " mulscc %%g1,%3,%%g1\n" \
992 " mulscc %%g1,%3,%%g1\n" \
993 " mulscc %%g1,%3,%%g1\n" \
994 " mulscc %%g1,%3,%%g1\n" \
995 " mulscc %%g1,%3,%%g1\n" \
996 " mulscc %%g1,%3,%%g1\n" \
997 " mulscc %%g1,%3,%%g1\n" \
998 " mulscc %%g1,%3,%%g1\n" \
999 " mulscc %%g1,%3,%%g1\n" \
1000 " mulscc %%g1,0,%%g1\n" \
1001 " add %%g1,%%o5,%0\n" \
1002 " rd %%y,%1" \
1003 : "=r" ((USItype) (w1)), \
1004 "=r" ((USItype) (w0)) \
1005 : "%rI" ((USItype) (u)), \
1006 "r" ((USItype) (v)) \
1007 : "g1", "o5" __AND_CLOBBER_CC)
1008 #define UMUL_TIME 39 /* 39 instructions */
1009 /* It's quite necessary to add this much assembler for the sparc.
1010 The default udiv_qrnnd (in C) is more than 10 times slower! */
1011 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1012 __asm__ ("! Inlined udiv_qrnnd\n" \
1013 " mov 32,%%g1\n" \
1014 " subcc %1,%2,%%g0\n" \
1015 "1: bcs 5f\n" \
1016 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1017 " sub %1,%2,%1 ! this kills msb of n\n" \
1018 " addx %1,%1,%1 ! so this can't give carry\n" \
1019 " subcc %%g1,1,%%g1\n" \
1020 "2: bne 1b\n" \
1021 " subcc %1,%2,%%g0\n" \
1022 " bcs 3f\n" \
1023 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1024 " b 3f\n" \
1025 " sub %1,%2,%1 ! this kills msb of n\n" \
1026 "4: sub %1,%2,%1\n" \
1027 "5: addxcc %1,%1,%1\n" \
1028 " bcc 2b\n" \
1029 " subcc %%g1,1,%%g1\n" \
1030 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1031 " bne 4b\n" \
1032 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1033 " sub %1,%2,%1\n" \
1034 "3: xnor %0,0,%0\n" \
1035 " ! End of inline udiv_qrnnd" \
1036 : "=&r" ((USItype) (__q)), \
1037 "=&r" ((USItype) (__r)) \
1038 : "r" ((USItype) (__d)), \
1039 "1" ((USItype) (__n1)), \
1040 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1041 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1042 #endif /* __sparclite__ */
1043 #endif /* __sparc_v8__ */
1044 #endif /* sparc32 */
1045
1046 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1047 && W_TYPE_SIZE == 64
1048 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1049 __asm__ ("addcc %r4,%5,%1\n\t" \
1050 "add %r2,%3,%0\n\t" \
1051 "bcs,a,pn %%xcc, 1f\n\t" \
1052 "add %0, 1, %0\n" \
1053 "1:" \
1054 : "=r" ((UDItype)(sh)), \
1055 "=&r" ((UDItype)(sl)) \
1056 : "%rJ" ((UDItype)(ah)), \
1057 "rI" ((UDItype)(bh)), \
1058 "%rJ" ((UDItype)(al)), \
1059 "rI" ((UDItype)(bl)) \
1060 __CLOBBER_CC)
1061
1062 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1063 __asm__ ("subcc %r4,%5,%1\n\t" \
1064 "sub %r2,%3,%0\n\t" \
1065 "bcs,a,pn %%xcc, 1f\n\t" \
1066 "sub %0, 1, %0\n\t" \
1067 "1:" \
1068 : "=r" ((UDItype)(sh)), \
1069 "=&r" ((UDItype)(sl)) \
1070 : "rJ" ((UDItype)(ah)), \
1071 "rI" ((UDItype)(bh)), \
1072 "rJ" ((UDItype)(al)), \
1073 "rI" ((UDItype)(bl)) \
1074 __CLOBBER_CC)
1075
1076 #define umul_ppmm(wh, wl, u, v) \
1077 do { \
1078 UDItype tmp1, tmp2, tmp3, tmp4; \
1079 __asm__ __volatile__ ( \
1080 "srl %7,0,%3\n\t" \
1081 "mulx %3,%6,%1\n\t" \
1082 "srlx %6,32,%2\n\t" \
1083 "mulx %2,%3,%4\n\t" \
1084 "sllx %4,32,%5\n\t" \
1085 "srl %6,0,%3\n\t" \
1086 "sub %1,%5,%5\n\t" \
1087 "srlx %5,32,%5\n\t" \
1088 "addcc %4,%5,%4\n\t" \
1089 "srlx %7,32,%5\n\t" \
1090 "mulx %3,%5,%3\n\t" \
1091 "mulx %2,%5,%5\n\t" \
1092 "sethi %%hi(0x80000000),%2\n\t" \
1093 "addcc %4,%3,%4\n\t" \
1094 "srlx %4,32,%4\n\t" \
1095 "add %2,%2,%2\n\t" \
1096 "movcc %%xcc,%%g0,%2\n\t" \
1097 "addcc %5,%4,%5\n\t" \
1098 "sllx %3,32,%3\n\t" \
1099 "add %1,%3,%1\n\t" \
1100 "add %5,%2,%0" \
1101 : "=r" ((UDItype)(wh)), \
1102 "=&r" ((UDItype)(wl)), \
1103 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1104 : "r" ((UDItype)(u)), \
1105 "r" ((UDItype)(v)) \
1106 __CLOBBER_CC); \
1107 } while (0)
1108 #define UMUL_TIME 96
1109 #define UDIV_TIME 230
1110 #endif /* sparc64 */
1111
1112 #if defined (__vax__) && W_TYPE_SIZE == 32
1113 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1114 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1115 : "=g" ((USItype) (sh)), \
1116 "=&g" ((USItype) (sl)) \
1117 : "%0" ((USItype) (ah)), \
1118 "g" ((USItype) (bh)), \
1119 "%1" ((USItype) (al)), \
1120 "g" ((USItype) (bl)))
1121 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1122 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1123 : "=g" ((USItype) (sh)), \
1124 "=&g" ((USItype) (sl)) \
1125 : "0" ((USItype) (ah)), \
1126 "g" ((USItype) (bh)), \
1127 "1" ((USItype) (al)), \
1128 "g" ((USItype) (bl)))
1129 #define umul_ppmm(xh, xl, m0, m1) \
1130 do { \
1131 union { \
1132 UDItype __ll; \
1133 struct {USItype __l, __h;} __i; \
1134 } __xx; \
1135 USItype __m0 = (m0), __m1 = (m1); \
1136 __asm__ ("emul %1,%2,$0,%0" \
1137 : "=r" (__xx.__ll) \
1138 : "g" (__m0), \
1139 "g" (__m1)); \
1140 (xh) = __xx.__i.__h; \
1141 (xl) = __xx.__i.__l; \
1142 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1143 + (((SItype) __m1 >> 31) & __m0)); \
1144 } while (0)
1145 #define sdiv_qrnnd(q, r, n1, n0, d) \
1146 do { \
1147 union {DItype __ll; \
1148 struct {SItype __l, __h;} __i; \
1149 } __xx; \
1150 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1151 __asm__ ("ediv %3,%2,%0,%1" \
1152 : "=g" (q), "=g" (r) \
1153 : "g" (__xx.__ll), "g" (d)); \
1154 } while (0)
1155 #endif /* __vax__ */
1156
1157 #if defined (__z8000__) && W_TYPE_SIZE == 16
1158 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1159 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1160 : "=r" ((unsigned int)(sh)), \
1161 "=&r" ((unsigned int)(sl)) \
1162 : "%0" ((unsigned int)(ah)), \
1163 "r" ((unsigned int)(bh)), \
1164 "%1" ((unsigned int)(al)), \
1165 "rQR" ((unsigned int)(bl)))
1166 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1167 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1168 : "=r" ((unsigned int)(sh)), \
1169 "=&r" ((unsigned int)(sl)) \
1170 : "0" ((unsigned int)(ah)), \
1171 "r" ((unsigned int)(bh)), \
1172 "1" ((unsigned int)(al)), \
1173 "rQR" ((unsigned int)(bl)))
1174 #define umul_ppmm(xh, xl, m0, m1) \
1175 do { \
1176 union {long int __ll; \
1177 struct {unsigned int __h, __l;} __i; \
1178 } __xx; \
1179 unsigned int __m0 = (m0), __m1 = (m1); \
1180 __asm__ ("mult %S0,%H3" \
1181 : "=r" (__xx.__i.__h), \
1182 "=r" (__xx.__i.__l) \
1183 : "%1" (__m0), \
1184 "rQR" (__m1)); \
1185 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1186 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1187 + (((signed int) __m1 >> 15) & __m0)); \
1188 } while (0)
1189 #endif /* __z8000__ */
1190
1191 #endif /* __GNUC__ */
1192
1193 /* If this machine has no inline assembler, use C macros. */
1194
1195 #if !defined (add_ssaaaa)
1196 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1197 do { \
1198 UWtype __x; \
1199 __x = (al) + (bl); \
1200 (sh) = (ah) + (bh) + (__x < (al)); \
1201 (sl) = __x; \
1202 } while (0)
1203 #endif
1204
1205 #if !defined (sub_ddmmss)
1206 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1207 do { \
1208 UWtype __x; \
1209 __x = (al) - (bl); \
1210 (sh) = (ah) - (bh) - (__x > (al)); \
1211 (sl) = __x; \
1212 } while (0)
1213 #endif
1214
1215 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1216 smul_ppmm. */
1217 #if !defined (umul_ppmm) && defined (smul_ppmm)
1218 #define umul_ppmm(w1, w0, u, v) \
1219 do { \
1220 UWtype __w1; \
1221 UWtype __xm0 = (u), __xm1 = (v); \
1222 smul_ppmm (__w1, w0, __xm0, __xm1); \
1223 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1224 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1225 } while (0)
1226 #endif
1227
1228 /* If we still don't have umul_ppmm, define it using plain C. */
1229 #if !defined (umul_ppmm)
1230 #define umul_ppmm(w1, w0, u, v) \
1231 do { \
1232 UWtype __x0, __x1, __x2, __x3; \
1233 UHWtype __ul, __vl, __uh, __vh; \
1234 \
1235 __ul = __ll_lowpart (u); \
1236 __uh = __ll_highpart (u); \
1237 __vl = __ll_lowpart (v); \
1238 __vh = __ll_highpart (v); \
1239 \
1240 __x0 = (UWtype) __ul * __vl; \
1241 __x1 = (UWtype) __ul * __vh; \
1242 __x2 = (UWtype) __uh * __vl; \
1243 __x3 = (UWtype) __uh * __vh; \
1244 \
1245 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1246 __x1 += __x2; /* but this indeed can */ \
1247 if (__x1 < __x2) /* did we get it? */ \
1248 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1249 \
1250 (w1) = __x3 + __ll_highpart (__x1); \
1251 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1252 } while (0)
1253 #endif
1254
1255 #if !defined (__umulsidi3)
1256 #define __umulsidi3(u, v) \
1257 ({DWunion __w; \
1258 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1259 __w.ll; })
1260 #endif
1261
1262 /* Define this unconditionally, so it can be used for debugging. */
1263 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1264 do { \
1265 UWtype __d1, __d0, __q1, __q0; \
1266 UWtype __r1, __r0, __m; \
1267 __d1 = __ll_highpart (d); \
1268 __d0 = __ll_lowpart (d); \
1269 \
1270 __r1 = (n1) % __d1; \
1271 __q1 = (n1) / __d1; \
1272 __m = (UWtype) __q1 * __d0; \
1273 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1274 if (__r1 < __m) \
1275 { \
1276 __q1--, __r1 += (d); \
1277 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1278 if (__r1 < __m) \
1279 __q1--, __r1 += (d); \
1280 } \
1281 __r1 -= __m; \
1282 \
1283 __r0 = __r1 % __d1; \
1284 __q0 = __r1 / __d1; \
1285 __m = (UWtype) __q0 * __d0; \
1286 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1287 if (__r0 < __m) \
1288 { \
1289 __q0--, __r0 += (d); \
1290 if (__r0 >= (d)) \
1291 if (__r0 < __m) \
1292 __q0--, __r0 += (d); \
1293 } \
1294 __r0 -= __m; \
1295 \
1296 (q) = (UWtype) __q1 * __ll_B | __q0; \
1297 (r) = __r0; \
1298 } while (0)
1299
1300 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1301 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1302 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1303 #define udiv_qrnnd(q, r, nh, nl, d) \
1304 do { \
1305 USItype __r; \
1306 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1307 (r) = __r; \
1308 } while (0)
1309 #endif
1310
1311 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1312 #if !defined (udiv_qrnnd)
1313 #define UDIV_NEEDS_NORMALIZATION 1
1314 #define udiv_qrnnd __udiv_qrnnd_c
1315 #endif
1316
1317 #if !defined (count_leading_zeros)
1318 #define count_leading_zeros(count, x) \
1319 do { \
1320 UWtype __xr = (x); \
1321 UWtype __a; \
1322 \
1323 if (W_TYPE_SIZE <= 32) \
1324 { \
1325 __a = __xr < ((UWtype)1<<2*__BITS4) \
1326 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1327 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1328 } \
1329 else \
1330 { \
1331 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1332 if (((__xr >> __a) & 0xff) != 0) \
1333 break; \
1334 } \
1335 \
1336 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1337 } while (0)
1338 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1339 #endif
1340
1341 #if !defined (count_trailing_zeros)
1342 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1343 defined in asm, but if it is not, the C version above is good enough. */
1344 #define count_trailing_zeros(count, x) \
1345 do { \
1346 UWtype __ctz_x = (x); \
1347 UWtype __ctz_c; \
1348 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1349 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1350 } while (0)
1351 #endif
1352
1353 #ifndef UDIV_NEEDS_NORMALIZATION
1354 #define UDIV_NEEDS_NORMALIZATION 0
1355 #endif
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