1 /* memset with unaligned store and rep stosb
2 Copyright (C) 2016-2024 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <https://www.gnu.org/licenses/>. */
19 /* memset is implemented as:
20 1. Use overlapping store to avoid branch.
21 2. If size is less than VEC, use integer register stores.
22 3. If size is from VEC_SIZE to 2 * VEC_SIZE, use 2 VEC stores.
23 4. If size is from 2 * VEC_SIZE to 4 * VEC_SIZE, use 4 VEC stores.
24 5. If size is more to 4 * VEC_SIZE, align to 4 * VEC_SIZE with
25 4 VEC stores and store 4 * VEC at a time until done. */
29 #ifndef MEMSET_CHK_SYMBOL
30 # define MEMSET_CHK_SYMBOL(p,s) MEMSET_SYMBOL(p, s)
33 #ifndef WMEMSET_CHK_SYMBOL
34 # define WMEMSET_CHK_SYMBOL(p,s) WMEMSET_SYMBOL(p, s)
39 # define VZEROUPPER vzeroupper
40 # define VZEROUPPER_SHORT_RETURN vzeroupper; ret
46 #ifndef VZEROUPPER_SHORT_RETURN
47 # define VZEROUPPER_SHORT_RETURN rep; ret
61 # define LOOP_4X_OFFSET (VEC_SIZE * 4)
63 # define LOOP_4X_OFFSET (0)
66 #if defined USE_WITH_EVEX || defined USE_WITH_AVX512
69 # define LESS_VEC_REG rax
73 # define LESS_VEC_REG rdi
76 #ifdef USE_XMM_LESS_VEC
82 #ifdef USE_LESS_VEC_MASK_STORE
83 # define SET_REG64 rcx
84 # define SET_REG32 ecx
88 # define SET_REG64 rsi
89 # define SET_REG32 esi
94 #define PAGE_SIZE 4096
96 /* Macro to calculate size of small memset block for aligning
98 #define SMALL_MEMSET_ALIGN(mov_sz, ret_sz) (2 * (mov_sz) + (ret_sz) + 1)
102 # error SECTION is not defined!
105 .section SECTION(.text), "ax", @progbits
108 ENTRY_CHK (WMEMSET_CHK_SYMBOL (__wmemset_chk, unaligned))
110 jb HIDDEN_JUMPTARGET (__chk_fail)
111 END_CHK (WMEMSET_CHK_SYMBOL (__wmemset_chk, unaligned))
114 ENTRY (WMEMSET_SYMBOL (__wmemset, unaligned))
116 WMEMSET_SET_VEC0_AND_SET_RETURN (%esi, %rdi)
117 WMEMSET_VDUP_TO_VEC0_LOW()
119 jb L(less_vec_from_wmemset)
120 WMEMSET_VDUP_TO_VEC0_HIGH()
121 jmp L(entry_from_wmemset)
122 END (WMEMSET_SYMBOL (__wmemset, unaligned))
125 #if defined SHARED && IS_IN (libc)
126 ENTRY_CHK (MEMSET_CHK_SYMBOL (__memset_chk, unaligned))
128 jb HIDDEN_JUMPTARGET (__chk_fail)
129 END_CHK (MEMSET_CHK_SYMBOL (__memset_chk, unaligned))
132 ENTRY (MEMSET_SYMBOL (__memset, unaligned))
133 MEMSET_SET_VEC0_AND_SET_RETURN (%esi, %rdi)
135 /* Clear the upper 32 bits. */
140 MEMSET_VDUP_TO_VEC0_HIGH()
141 L(entry_from_wmemset):
142 cmpq $(VEC_SIZE * 2), %rdx
144 /* From VEC and to 2 * VEC. No branch when size == VEC_SIZE. */
145 VMOVU %VMM(0), -VEC_SIZE(%rdi,%rdx)
146 VMOVU %VMM(0), (%rdi)
148 #if defined USE_MULTIARCH && IS_IN (libc)
149 END (MEMSET_SYMBOL (__memset, unaligned))
151 # if defined SHARED && IS_IN (libc)
152 ENTRY_CHK (MEMSET_CHK_SYMBOL (__memset_chk, unaligned_erms))
154 jb HIDDEN_JUMPTARGET (__chk_fail)
155 END_CHK (MEMSET_CHK_SYMBOL (__memset_chk, unaligned_erms))
158 ENTRY_P2ALIGN (MEMSET_SYMBOL (__memset, unaligned_erms), 6)
159 MEMSET_SET_VEC0_AND_SET_RETURN (%esi, %rdi)
161 /* Clear the upper 32 bits. */
164 cmp $VEC_SIZE, %RDX_LP
166 MEMSET_VDUP_TO_VEC0_HIGH ()
167 cmp $(VEC_SIZE * 2), %RDX_LP
168 ja L(stosb_more_2x_vec)
169 /* From VEC and to 2 * VEC. No branch when size == VEC_SIZE. */
170 VMOVU %VMM(0), (%rdi)
171 VMOVU %VMM(0), (VEC_SIZE * -1)(%rdi, %rdx)
177 #ifdef USE_LESS_VEC_MASK_STORE
178 VMOVU %VMM(0), (VEC_SIZE * -2)(%rdi, %rdx)
179 VMOVU %VMM(0), (VEC_SIZE * -1)(%rdi, %rdx)
181 VMOVU %VMM(0), (VEC_SIZE * -2)(%rdi)
182 VMOVU %VMM(0), (VEC_SIZE * -1)(%rdi)
186 /* If have AVX512 mask instructions put L(less_vec) close to
187 entry as it doesn't take much space and is likely a hot target.
189 #ifdef USE_LESS_VEC_MASK_STORE
192 L(less_vec_from_wmemset):
193 /* Less than 1 VEC. */
194 # if VEC_SIZE != 16 && VEC_SIZE != 32 && VEC_SIZE != 64
195 # error Unsupported VEC_SIZE!
197 /* Clear high bits from edi. Only keeping bits relevant to page
198 cross check. Note that we are using rax which is set in
199 MEMSET_VDUP_TO_VEC0_AND_SET_RETURN as ptr from here on out. */
200 andl $(PAGE_SIZE - 1), %edi
201 /* Check if VEC_SIZE store cross page. Mask stores suffer
202 serious performance degradation when it has to fault suppress.
204 cmpl $(PAGE_SIZE - VEC_SIZE), %edi
205 /* This is generally considered a cold target. */
209 bzhiq %rdx, %rcx, %rcx
213 bzhil %edx, %ecx, %ecx
216 vmovdqu8 %VMM(0), (%rax){%k1}
219 # if defined USE_MULTIARCH && IS_IN (libc)
220 /* Include L(stosb_local) here if including L(less_vec) between
221 L(stosb_more_2x_vec) and ENTRY. This is to cache align the
222 L(stosb_more_2x_vec) target. */
234 #if defined USE_MULTIARCH && IS_IN (libc)
236 L(stosb_more_2x_vec):
237 cmp __x86_rep_stosb_threshold(%rip), %RDX_LP
240 /* Fallthrough goes to L(loop_4x_vec). Tests for memset (2x, 4x]
241 and (4x, 8x] jump to target. */
243 /* Store next 2x vec regardless. */
244 VMOVU %VMM(0), (%rdi)
245 VMOVU %VMM(0), (VEC_SIZE * 1)(%rdi)
248 /* Two different methods of setting up pointers / compare. The two
249 methods are based on the fact that EVEX/AVX512 mov instructions take
250 more bytes then AVX2/SSE2 mov instructions. As well that EVEX/AVX512
251 machines also have fast LEA_BID. Both setup and END_REG to avoid complex
252 address mode. For EVEX/AVX512 this saves code size and keeps a few
253 targets in one fetch block. For AVX2/SSE2 this helps prevent AGU
255 #if !(defined USE_WITH_EVEX || defined USE_WITH_AVX512)
256 /* If AVX2/SSE2 compute END_REG (rdi) with ALU. */
260 cmpq $(VEC_SIZE * 4), %rdx
264 #if defined USE_WITH_EVEX || defined USE_WITH_AVX512
265 /* If EVEX/AVX512 compute END_REG - (VEC_SIZE * 4 + LOOP_4X_OFFSET) with
268 /* END_REG is rcx for EVEX/AVX512. */
269 leaq -(VEC_SIZE * 4 + LOOP_4X_OFFSET)(%rdi, %rdx), %END_REG
272 /* Store next 2x vec regardless. */
273 VMOVU %VMM(0), (VEC_SIZE * 2)(%rax)
274 VMOVU %VMM(0), (VEC_SIZE * 3)(%rax)
277 #if defined USE_WITH_EVEX || defined USE_WITH_AVX512
278 /* If LOOP_4X_OFFSET don't readjust LOOP_REG (rdi), just add
279 extra offset to addresses in loop. Used for AVX512 to save space
280 as no way to get (VEC_SIZE * 4) in imm8. */
281 # if LOOP_4X_OFFSET == 0
282 subq $-(VEC_SIZE * 4), %LOOP_REG
284 /* Avoid imm32 compare here to save code size. */
287 addq $-(VEC_SIZE * 4), %END_REG
288 cmpq $(VEC_SIZE * 8), %rdx
291 #if !(defined USE_WITH_EVEX || defined USE_WITH_AVX512)
292 /* Set LOOP_REG (rdx). */
293 leaq (VEC_SIZE * 4)(%rax), %LOOP_REG
295 /* Align dst for loop. */
296 andq $(VEC_SIZE * -1), %LOOP_REG
299 VMOVA %VMM(0), LOOP_4X_OFFSET(%LOOP_REG)
300 VMOVA %VMM(0), (VEC_SIZE + LOOP_4X_OFFSET)(%LOOP_REG)
301 VMOVA %VMM(0), (VEC_SIZE * 2 + LOOP_4X_OFFSET)(%LOOP_REG)
302 VMOVA %VMM(0), (VEC_SIZE * 3 + LOOP_4X_OFFSET)(%LOOP_REG)
303 subq $-(VEC_SIZE * 4), %LOOP_REG
304 cmpq %END_REG, %LOOP_REG
306 .p2align 4,, MOV_SIZE
308 VMOVU %VMM(0), LOOP_4X_OFFSET(%END_REG)
309 VMOVU %VMM(0), (VEC_SIZE + LOOP_4X_OFFSET)(%END_REG)
310 VMOVU %VMM(0), (VEC_SIZE * 2 + LOOP_4X_OFFSET)(%END_REG)
311 VMOVU %VMM(0), (VEC_SIZE * 3 + LOOP_4X_OFFSET)(%END_REG)
312 L(return_vzeroupper):
314 ZERO_UPPER_VEC_REGISTERS_RETURN
320 #ifndef USE_LESS_VEC_MASK_STORE
321 # if defined USE_MULTIARCH && IS_IN (libc)
322 /* If no USE_LESS_VEC_MASK put L(stosb_local) here. Will be in
323 range for 2-byte jump encoding. */
332 /* Define L(less_vec) only if not otherwise defined. */
335 /* Broadcast esi to partial register (i.e VEC_SIZE == 32 broadcast to
336 xmm). This is only does anything for AVX2. */
337 MEMSET_VDUP_TO_VEC0_LOW ()
338 L(less_vec_from_wmemset):
349 #ifndef USE_XMM_LESS_VEC
350 MOVQ %VMM_128(0), %SET_REG64
359 movb %SET_REG8, (%LESS_VEC_REG)
363 /* Align small targets only if not doing so would cross a fetch line.
366 .p2align 4,, SMALL_MEMSET_ALIGN(MOV_SIZE, RET_SIZE)
367 /* From 32 to 63. No branch when size == 32. */
369 VMOVU %VMM_256(0), (%LESS_VEC_REG)
370 VMOVU %VMM_256(0), -32(%LESS_VEC_REG, %rdx)
375 .p2align 4,, SMALL_MEMSET_ALIGN(MOV_SIZE, 1)
377 /* From 16 to 31. No branch when size == 16. */
378 VMOVU %VMM_128(0), (%LESS_VEC_REG)
379 VMOVU %VMM_128(0), -16(%LESS_VEC_REG, %rdx)
383 /* Move size is 3 for SSE2, EVEX, and AVX512. Move size is 4 for AVX2.
385 .p2align 4,, SMALL_MEMSET_ALIGN(3 + XMM_SMALL, 1)
387 /* From 8 to 15. No branch when size == 8. */
388 #ifdef USE_XMM_LESS_VEC
389 MOVQ %VMM_128(0), (%rdi)
390 MOVQ %VMM_128(0), -8(%rdi, %rdx)
392 movq %SET_REG64, (%LESS_VEC_REG)
393 movq %SET_REG64, -8(%LESS_VEC_REG, %rdx)
397 /* Move size is 2 for SSE2, EVEX, and AVX512. Move size is 4 for AVX2.
399 .p2align 4,, SMALL_MEMSET_ALIGN(2 << XMM_SMALL, 1)
401 /* From 4 to 7. No branch when size == 4. */
402 #ifdef USE_XMM_LESS_VEC
403 MOVD %VMM_128(0), (%rdi)
404 MOVD %VMM_128(0), -4(%rdi, %rdx)
406 movl %SET_REG32, (%LESS_VEC_REG)
407 movl %SET_REG32, -4(%LESS_VEC_REG, %rdx)
411 /* 4 * XMM_SMALL for the third mov for AVX2. */
412 .p2align 4,, 4 * XMM_SMALL + SMALL_MEMSET_ALIGN(3, 1)
414 /* From 2 to 3. No branch when size == 2. */
415 #ifdef USE_XMM_LESS_VEC
416 movb %SET_REG8, (%rdi)
417 movb %SET_REG8, 1(%rdi)
418 movb %SET_REG8, -1(%rdi, %rdx)
420 movw %SET_REG16, (%LESS_VEC_REG)
421 movb %SET_REG8, -1(%LESS_VEC_REG, %rdx)
424 END (MEMSET_SYMBOL (__memset, unaligned_erms))