sysdeps/powerpc/fpu/fenv_libc.h

   1 /* Internal libc stuff for floating point environment routines.
   2    Copyright (C) 1997-2019 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, see
  17    <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef _FENV_LIBC_H
  20 #define _FENV_LIBC_H    1
  21
  22 #include <fenv.h>
  23 #include <ldsodefs.h>
  24 #include <sysdep.h>
  25
  26 extern const fenv_t *__fe_nomask_env_priv (void);
  27
  28 extern const fenv_t *__fe_mask_env (void) attribute_hidden;
  29
  30 /* The sticky bits in the FPSCR indicating exceptions have occurred.  */
  31 #define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
  32
  33 /* Equivalent to fegetenv, but returns a fenv_t instead of taking a
  34    pointer.  */
  35 #define fegetenv_register() __builtin_mffs()
  36
  37 /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
  38 #define fesetenv_register(env) \
  39         do { \
  40           double d = (env); \
  41           if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
  42             asm volatile (".machine push; " \
  43                           ".machine \"power6\"; " \
  44                           "mtfsf 0xff,%0,1,0; " \
  45                           ".machine pop" : : "f" (d)); \
  46           else \
  47             __builtin_mtfsf (0xff, d); \
  48         } while(0)
  49
  50 /* This very handy macro:
  51    - Sets the rounding mode to 'round to nearest';
  52    - Sets the processor into IEEE mode; and
  53    - Prevents exceptions from being raised for inexact results.
  54    These things happen to be exactly what you need for typical elementary
  55    functions.  */
  56 #define relax_fenv_state() \
  57         do { \
  58            if (GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
  59              asm (".machine push; .machine \"power6\"; " \
  60                   "mtfsfi 7,0,1; .machine pop"); \
  61            asm ("mtfsfi 7,0"); \
  62         } while(0)
  63
  64 /* Set/clear a particular FPSCR bit (for instance,
  65    reset_fpscr_bit(FPSCR_VE);
  66    prevents INVALID exceptions from being raised).  */
  67 #define set_fpscr_bit(x) asm volatile ("mtfsb1 %0" : : "i"(x))
  68 #define reset_fpscr_bit(x) asm volatile ("mtfsb0 %0" : : "i"(x))
  69
  70 typedef union
  71 {
  72   fenv_t fenv;
  73   unsigned long long l;
  74 } fenv_union_t;
  75
  76
  77 static inline int
  78 __fesetround_inline (int round)
  79 {
  80   if ((unsigned int) round < 2)
  81     {
  82        asm volatile ("mtfsb0 30");
  83        if ((unsigned int) round == 0)
  84          asm volatile ("mtfsb0 31");
  85        else
  86          asm volatile ("mtfsb1 31");
  87     }
  88   else
  89     {
  90        asm volatile ("mtfsb1 30");
  91        if ((unsigned int) round == 2)
  92          asm volatile ("mtfsb0 31");
  93        else
  94          asm volatile ("mtfsb1 31");
  95     }
  96
  97   return 0;
  98 }
  99
 100 /* Definitions of all the FPSCR bit numbers */
 101 enum {
 102   FPSCR_FX = 0,    /* exception summary */
 103   FPSCR_FEX,       /* enabled exception summary */
 104   FPSCR_VX,        /* invalid operation summary */
 105   FPSCR_OX,        /* overflow */
 106   FPSCR_UX,        /* underflow */
 107   FPSCR_ZX,        /* zero divide */
 108   FPSCR_XX,        /* inexact */
 109   FPSCR_VXSNAN,    /* invalid operation for sNaN */
 110   FPSCR_VXISI,     /* invalid operation for Inf-Inf */
 111   FPSCR_VXIDI,     /* invalid operation for Inf/Inf */
 112   FPSCR_VXZDZ,     /* invalid operation for 0/0 */
 113   FPSCR_VXIMZ,     /* invalid operation for Inf*0 */
 114   FPSCR_VXVC,      /* invalid operation for invalid compare */
 115   FPSCR_FR,        /* fraction rounded [fraction was incremented by round] */
 116   FPSCR_FI,        /* fraction inexact */
 117   FPSCR_FPRF_C,    /* result class descriptor */
 118   FPSCR_FPRF_FL,   /* result less than (usually, less than 0) */
 119   FPSCR_FPRF_FG,   /* result greater than */
 120   FPSCR_FPRF_FE,   /* result equal to */
 121   FPSCR_FPRF_FU,   /* result unordered */
 122   FPSCR_20,        /* reserved */
 123   FPSCR_VXSOFT,    /* invalid operation set by software */
 124   FPSCR_VXSQRT,    /* invalid operation for square root */
 125   FPSCR_VXCVI,     /* invalid operation for invalid integer convert */
 126   FPSCR_VE,        /* invalid operation exception enable */
 127   FPSCR_OE,        /* overflow exception enable */
 128   FPSCR_UE,        /* underflow exception enable */
 129   FPSCR_ZE,        /* zero divide exception enable */
 130   FPSCR_XE,        /* inexact exception enable */
 131 #ifdef _ARCH_PWR6
 132   FPSCR_29,        /* Reserved in ISA 2.05  */
 133 #else
 134   FPSCR_NI         /* non-IEEE mode (typically, no denormalised numbers) */
 135 #endif /* _ARCH_PWR6 */
 136   /* the remaining two least-significant bits keep the rounding mode */
 137 };
 138
 139 static inline int
 140 fenv_reg_to_exceptions (unsigned long long l)
 141 {
 142   int result = 0;
 143   if (l & (1 << (31 - FPSCR_XE)))
 144     result |= FE_INEXACT;
 145   if (l & (1 << (31 - FPSCR_ZE)))
 146     result |= FE_DIVBYZERO;
 147   if (l & (1 << (31 - FPSCR_UE)))
 148     result |= FE_UNDERFLOW;
 149   if (l & (1 << (31 - FPSCR_OE)))
 150     result |= FE_OVERFLOW;
 151   if (l & (1 << (31 - FPSCR_VE)))
 152     result |= FE_INVALID;
 153   return result;
 154 }
 155
 156 #ifdef _ARCH_PWR6
 157   /* Not supported in ISA 2.05.  Provided for source compat only.  */
 158 # define FPSCR_NI 29
 159 #endif /* _ARCH_PWR6 */
 160
 161 /* This operation (i) sets the appropriate FPSCR bits for its
 162    parameter, (ii) converts sNaN to the corresponding qNaN, and (iii)
 163    otherwise passes its parameter through unchanged (in particular, -0
 164    and +0 stay as they were).  The `obvious' way to do this is optimised
 165    out by gcc.  */
 166 #define f_wash(x) \
 167    ({ double d; asm volatile ("fmul %0,%1,%2" \
 168                               : "=f"(d) \
 169                               : "f" (x), "f"((float)1.0)); d; })
 170 #define f_washf(x) \
 171    ({ float f; asm volatile ("fmuls %0,%1,%2" \
 172                              : "=f"(f) \
 173                              : "f" (x), "f"((float)1.0)); f; })
 174
 175 #endif /* fenv_libc.h */