sysdeps/x86_64/cacheinfo.c

   1 /* x86_64 cache info.
   2    Copyright (C) 2003, 2004, 2006, 2007, 2009 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.
  19 */
  20
  21 #include <assert.h>
  22 #include <stdbool.h>
  23 #include <stdlib.h>
  24 #include <unistd.h>
  25
  26 #ifdef USE_MULTIARCH
  27 # include "multiarch/init-arch.h"
  28
  29 # define is_intel __cpu_features.kind == arch_kind_intel
  30 # define is_amd __cpu_features.kind == arch_kind_amd
  31 # define max_cpuid __cpu_features.max_cpuid
  32 #else
  33   /* This spells out "GenuineIntel".  */
  34 # define is_intel \
  35   ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69
  36   /* This spells out "AuthenticAMD".  */
  37 # define is_amd \
  38   ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65
  39 #endif
  40
  41 static const struct intel_02_cache_info
  42 {
  43   unsigned char idx;
  44   unsigned char assoc;
  45   unsigned char linesize;
  46   unsigned char rel_name;
  47   unsigned int size;
  48 } intel_02_known [] =
  49   {
  50 #define M(sc) ((sc) - _SC_LEVEL1_ICACHE_SIZE)
  51     { 0x06,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),    8192 },
  52     { 0x08,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),   16384 },
  53     { 0x09,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),   32768 },
  54     { 0x0a,  2, 32, M(_SC_LEVEL1_DCACHE_SIZE),    8192 },
  55     { 0x0c,  4, 32, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
  56     { 0x0d,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
  57     { 0x21,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
  58     { 0x22,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),   524288 },
  59     { 0x23,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
  60     { 0x25,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
  61     { 0x29,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
  62     { 0x2c,  8, 64, M(_SC_LEVEL1_DCACHE_SIZE),   32768 },
  63     { 0x30,  8, 64, M(_SC_LEVEL1_ICACHE_SIZE),   32768 },
  64     { 0x39,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
  65     { 0x3a,  6, 64, M(_SC_LEVEL2_CACHE_SIZE),   196608 },
  66     { 0x3b,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
  67     { 0x3c,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
  68     { 0x3d,  6, 64, M(_SC_LEVEL2_CACHE_SIZE),   393216 },
  69     { 0x3e,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
  70     { 0x3f,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
  71     { 0x41,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
  72     { 0x42,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
  73     { 0x43,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
  74     { 0x44,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
  75     { 0x45,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
  76     { 0x46,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
  77     { 0x47,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
  78     { 0x48, 12, 64, M(_SC_LEVEL2_CACHE_SIZE),  3145728 },
  79     { 0x49, 16, 64, M(_SC_LEVEL2_CACHE_SIZE),  4194304 },
  80     { 0x4a, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  6291456 },
  81     { 0x4b, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
  82     { 0x4c, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
  83     { 0x4d, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 16777216 },
  84     { 0x4e, 24, 64, M(_SC_LEVEL2_CACHE_SIZE),  6291456 },
  85     { 0x60,  8, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
  86     { 0x66,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),    8192 },
  87     { 0x67,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
  88     { 0x68,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   32768 },
  89     { 0x78,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
  90     { 0x79,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
  91     { 0x7a,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
  92     { 0x7b,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
  93     { 0x7c,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
  94     { 0x7d,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
  95     { 0x7f,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
  96     { 0x82,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
  97     { 0x83,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
  98     { 0x84,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
  99     { 0x85,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
 100     { 0x86,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
 101     { 0x87,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
 102     { 0xd0,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),   524288 },
 103     { 0xd1,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
 104     { 0xd2,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
 105     { 0xd6,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
 106     { 0xd7,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
 107     { 0xd8,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
 108     { 0xdc, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
 109     { 0xdd, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
 110     { 0xde, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
 111     { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
 112     { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
 113     { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
 114     { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
 115     { 0xeb, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 18874368 },
 116     { 0xec, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 25165824 },
 117   };
 118
 119 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known [0]))
 120
 121 static int
 122 intel_02_known_compare (const void *p1, const void *p2)
 123 {
 124   const struct intel_02_cache_info *i1;
 125   const struct intel_02_cache_info *i2;
 126
 127   i1 = (const struct intel_02_cache_info *) p1;
 128   i2 = (const struct intel_02_cache_info *) p2;
 129
 130   if (i1->idx == i2->idx)
 131     return 0;
 132
 133   return i1->idx < i2->idx ? -1 : 1;
 134 }
 135
 136
 137 static long int
 138 __attribute__ ((noinline))
 139 intel_check_word (int name, unsigned int value, bool *has_level_2,
 140                   bool *no_level_2_or_3)
 141 {
 142   if ((value & 0x80000000) != 0)
 143     /* The register value is reserved.  */
 144     return 0;
 145
 146   /* Fold the name.  The _SC_ constants are always in the order SIZE,
 147      ASSOC, LINESIZE.  */
 148   int folded_rel_name = (M(name) / 3) * 3;
 149
 150   while (value != 0)
 151     {
 152       unsigned int byte = value & 0xff;
 153
 154       if (byte == 0x40)
 155         {
 156           *no_level_2_or_3 = true;
 157
 158           if (folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
 159             /* No need to look further.  */
 160             break;
 161         }
 162       else
 163         {
 164           if (byte == 0x49 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
 165             {
 166               /* Intel reused this value.  For family 15, model 6 it
 167                  specifies the 3rd level cache.  Otherwise the 2nd
 168                  level cache.  */
 169               unsigned int family;
 170               unsigned int model;
 171 #ifdef USE_MULTIARCH
 172               family = __cpu_features.family;
 173               model = __cpu_features.model;
 174 #else
 175               unsigned int eax;
 176               unsigned int ebx;
 177               unsigned int ecx;
 178               unsigned int edx;
 179               asm volatile ("cpuid"
 180                             : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
 181                             : "0" (1));
 182
 183               family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
 184               model = (((eax >>16) & 0xf) << 4) + ((eax >> 4) & 0xf);
 185 #endif
 186
 187               if (family == 15 && model == 6)
 188                 {
 189                   /* The level 3 cache is encoded for this model like
 190                      the level 2 cache is for other models.  Pretend
 191                      the caller asked for the level 2 cache.  */
 192                   name = (_SC_LEVEL2_CACHE_SIZE
 193                           + (name - _SC_LEVEL3_CACHE_SIZE));
 194                   folded_rel_name = M(_SC_LEVEL2_CACHE_SIZE);
 195                 }
 196             }
 197
 198           struct intel_02_cache_info *found;
 199           struct intel_02_cache_info search;
 200
 201           search.idx = byte;
 202           found = bsearch (&search, intel_02_known, nintel_02_known,
 203                            sizeof (intel_02_known[0]), intel_02_known_compare);
 204           if (found != NULL)
 205             {
 206               if (found->rel_name == folded_rel_name)
 207                 {
 208                   unsigned int offset = M(name) - folded_rel_name;
 209
 210                   if (offset == 0)
 211                     /* Cache size.  */
 212                     return found->size;
 213                   if (offset == 1)
 214                     return found->assoc;
 215
 216                   assert (offset == 2);
 217                   return found->linesize;
 218                 }
 219
 220               if (found->rel_name == M(_SC_LEVEL2_CACHE_SIZE))
 221                 *has_level_2 = true;
 222             }
 223         }
 224
 225       /* Next byte for the next round.  */
 226       value >>= 8;
 227     }
 228
 229   /* Nothing found.  */
 230   return 0;
 231 }
 232
 233
 234 static long int __attribute__ ((noinline))
 235 handle_intel (int name, unsigned int maxidx)
 236 {
 237   assert (maxidx >= 2);
 238
 239   /* OK, we can use the CPUID instruction to get all info about the
 240      caches.  */
 241   unsigned int cnt = 0;
 242   unsigned int max = 1;
 243   long int result = 0;
 244   bool no_level_2_or_3 = false;
 245   bool has_level_2 = false;
 246
 247   while (cnt++ < max)
 248     {
 249       unsigned int eax;
 250       unsigned int ebx;
 251       unsigned int ecx;
 252       unsigned int edx;
 253       asm volatile ("cpuid"
 254                     : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
 255                     : "0" (2));
 256
 257       /* The low byte of EAX in the first round contain the number of
 258          rounds we have to make.  At least one, the one we are already
 259          doing.  */
 260       if (cnt == 1)
 261         {
 262           max = eax & 0xff;
 263           eax &= 0xffffff00;
 264         }
 265
 266       /* Process the individual registers' value.  */
 267       result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
 268       if (result != 0)
 269         return result;
 270
 271       result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
 272       if (result != 0)
 273         return result;
 274
 275       result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
 276       if (result != 0)
 277         return result;
 278
 279       result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
 280       if (result != 0)
 281         return result;
 282     }
 283
 284   if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
 285       && no_level_2_or_3)
 286     return -1;
 287
 288   return 0;
 289 }
 290
 291
 292 static long int __attribute__ ((noinline))
 293 handle_amd (int name)
 294 {
 295   unsigned int eax;
 296   unsigned int ebx;
 297   unsigned int ecx;
 298   unsigned int edx;
 299   asm volatile ("cpuid"
 300                 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
 301                 : "0" (0x80000000));
 302
 303   /* No level 4 cache (yet).  */
 304   if (name > _SC_LEVEL3_CACHE_LINESIZE)
 305     return 0;
 306
 307   unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
 308   if (eax < fn)
 309     return 0;
 310
 311   asm volatile ("cpuid"
 312                 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
 313                 : "0" (fn));
 314
 315   if (name < _SC_LEVEL1_DCACHE_SIZE)
 316     {
 317       name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
 318       ecx = edx;
 319     }
 320
 321   switch (name)
 322     {
 323     case _SC_LEVEL1_DCACHE_SIZE:
 324       return (ecx >> 14) & 0x3fc00;
 325
 326     case _SC_LEVEL1_DCACHE_ASSOC:
 327       ecx >>= 16;
 328       if ((ecx & 0xff) == 0xff)
 329         /* Fully associative.  */
 330         return (ecx << 2) & 0x3fc00;
 331       return ecx & 0xff;
 332
 333     case _SC_LEVEL1_DCACHE_LINESIZE:
 334       return ecx & 0xff;
 335
 336     case _SC_LEVEL2_CACHE_SIZE:
 337       return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
 338
 339     case _SC_LEVEL2_CACHE_ASSOC:
 340       switch ((ecx >> 12) & 0xf)
 341         {
 342         case 0:
 343         case 1:
 344         case 2:
 345         case 4:
 346           return (ecx >> 12) & 0xf;
 347         case 6:
 348           return 8;
 349         case 8:
 350           return 16;
 351         case 10:
 352           return 32;
 353         case 11:
 354           return 48;
 355         case 12:
 356           return 64;
 357         case 13:
 358           return 96;
 359         case 14:
 360           return 128;
 361         case 15:
 362           return ((ecx >> 6) & 0x3fffc00) / (ecx & 0xff);
 363         default:
 364           return 0;
 365         }
 366       /* NOTREACHED */
 367
 368     case _SC_LEVEL2_CACHE_LINESIZE:
 369       return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
 370
 371     case _SC_LEVEL3_CACHE_SIZE:
 372       return (edx & 0xf000) == 0 ? 0 : (edx & 0x3ffc0000) << 1;
 373
 374     case _SC_LEVEL3_CACHE_ASSOC:
 375       switch ((edx >> 12) & 0xf)
 376         {
 377         case 0:
 378         case 1:
 379         case 2:
 380         case 4:
 381           return (edx >> 12) & 0xf;
 382         case 6:
 383           return 8;
 384         case 8:
 385           return 16;
 386         case 10:
 387           return 32;
 388         case 11:
 389           return 48;
 390         case 12:
 391           return 64;
 392         case 13:
 393           return 96;
 394         case 14:
 395           return 128;
 396         case 15:
 397           return ((edx & 0x3ffc0000) << 1) / (edx & 0xff);
 398         default:
 399           return 0;
 400         }
 401       /* NOTREACHED */
 402
 403     case _SC_LEVEL3_CACHE_LINESIZE:
 404       return (edx & 0xf000) == 0 ? 0 : edx & 0xff;
 405
 406     default:
 407       assert (! "cannot happen");
 408     }
 409   return -1;
 410 }
 411
 412
 413 /* Get the value of the system variable NAME.  */
 414 long int
 415 attribute_hidden
 416 __cache_sysconf (int name)
 417 {
 418 #ifdef USE_MULTIARCH
 419   if (__cpu_features.kind == arch_kind_unknown)
 420     __init_cpu_features ();
 421 #else
 422   /* Find out what brand of processor.  */
 423   unsigned int max_cpuid;
 424   unsigned int ebx;
 425   unsigned int ecx;
 426   unsigned int edx;
 427   asm volatile ("cpuid"
 428                 : "=a" (max_cpuid), "=b" (ebx), "=c" (ecx), "=d" (edx)
 429                 : "0" (0));
 430 #endif
 431
 432   if (is_intel)
 433     return handle_intel (name, max_cpuid);
 434
 435   if (is_amd)
 436     return handle_amd (name);
 437
 438   // XXX Fill in more vendors.
 439
 440   /* CPU not known, we have no information.  */
 441   return 0;
 442 }
 443
 444
 445 /* Half the data cache size for use in memory and string routines, typically
 446    L1 size.  */
 447 long int __x86_64_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
 448 /* Shared cache size for use in memory and string routines, typically
 449    L2 or L3 size.  */
 450 long int __x86_64_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
 451 long int __x86_64_shared_cache_size attribute_hidden = 1024 * 1024;
 452 /* PREFETCHW support flag for use in memory and string routines.  */
 453 int __x86_64_prefetchw attribute_hidden;
 454
 455 /* Instructions preferred for memory and string routines.
 456
 457   0: Regular instructions
 458   1: MMX instructions
 459   2: SSE2 instructions
 460   3: SSSE3 instructions
 461
 462   */
 463 int __x86_64_preferred_memory_instruction attribute_hidden;
 464
 465
 466 static void
 467 __attribute__((constructor))
 468 init_cacheinfo (void)
 469 {
 470   /* Find out what brand of processor.  */
 471   unsigned int eax;
 472   unsigned int ebx;
 473   unsigned int ecx;
 474   unsigned int edx;
 475   int max_cpuid_ex;
 476   long int data = -1;
 477   long int shared = -1;
 478   unsigned int level;
 479   unsigned int threads = 0;
 480
 481 #ifdef USE_MULTIARCH
 482   if (__cpu_features.kind == arch_kind_unknown)
 483     __init_cpu_features ();
 484 #else
 485   int max_cpuid;
 486   asm volatile ("cpuid"
 487                 : "=a" (max_cpuid), "=b" (ebx), "=c" (ecx), "=d" (edx)
 488                 : "0" (0));
 489 #endif
 490
 491   if (is_intel)
 492     {
 493       data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid);
 494
 495       /* Try L3 first.  */
 496       level  = 3;
 497       shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid);
 498
 499       if (shared <= 0)
 500         {
 501           /* Try L2 otherwise.  */
 502           level  = 2;
 503           shared = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
 504         }
 505
 506 #ifdef USE_MULTIARCH
 507       eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
 508       ebx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx;
 509       ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
 510       edx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].edx;
 511 #else
 512       asm volatile ("cpuid"
 513                     : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
 514                     : "0" (1));
 515 #endif
 516
 517       /* Intel prefers SSSE3 instructions for memory/string routines
 518          if they are avaiable.  */
 519       if ((ecx & 0x200))
 520         __x86_64_preferred_memory_instruction = 3;
 521       else
 522         __x86_64_preferred_memory_instruction = 2;
 523
 524       /* Figure out the number of logical threads that share the
 525          highest cache level.  */
 526       if (max_cpuid >= 4)
 527         {
 528           int i = 0;
 529
 530           /* Query until desired cache level is enumerated.  */
 531           do
 532             {
 533               asm volatile ("cpuid"
 534                             : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
 535                             : "0" (4), "2" (i++));
 536
 537               /* There seems to be a bug in at least some Pentium Ds
 538                  which sometimes fail to iterate all cache parameters.
 539                  Do not loop indefinitely here, stop in this case and
 540                  assume there is no such information.  */
 541               if ((eax & 0x1f) == 0)
 542                 goto intel_bug_no_cache_info;
 543             }
 544           while (((eax >> 5) & 0x7) != level);
 545
 546           threads = ((eax >> 14) & 0x3ff) + 1;
 547         }
 548       else
 549         {
 550         intel_bug_no_cache_info:
 551           /* Assume that all logical threads share the highest cache level.  */
 552
 553           threads = (ebx >> 16) & 0xff;
 554         }
 555
 556       /* Cap usage of highest cache level to the number of supported
 557          threads.  */
 558       if (shared > 0 && threads > 0)
 559         shared /= threads;
 560     }
 561   /* This spells out "AuthenticAMD".  */
 562   else if (is_amd)
 563     {
 564       data   = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
 565       long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE);
 566       shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
 567
 568       /* Get maximum extended function. */
 569       asm volatile ("cpuid"
 570                     : "=a" (max_cpuid_ex), "=b" (ebx), "=c" (ecx), "=d" (edx)
 571                     : "0" (0x80000000));
 572
 573       if (shared <= 0)
 574         /* No shared L3 cache.  All we have is the L2 cache.  */
 575         shared = core;
 576       else
 577         {
 578           /* Figure out the number of logical threads that share L3.  */
 579           if (max_cpuid_ex >= 0x80000008)
 580             {
 581               /* Get width of APIC ID.  */
 582               asm volatile ("cpuid"
 583                             : "=a" (max_cpuid_ex), "=b" (ebx), "=c" (ecx),
 584                               "=d" (edx)
 585                             : "0" (0x80000008));
 586               threads = 1 << ((ecx >> 12) & 0x0f);
 587             }
 588
 589           if (threads == 0)
 590             {
 591               /* If APIC ID width is not available, use logical
 592                  processor count.  */
 593               asm volatile ("cpuid"
 594                             : "=a" (max_cpuid_ex), "=b" (ebx), "=c" (ecx),
 595                               "=d" (edx)
 596                             : "0" (0x00000001));
 597
 598               if ((edx & (1 << 28)) != 0)
 599                 threads = (ebx >> 16) & 0xff;
 600             }
 601
 602           /* Cap usage of highest cache level to the number of
 603              supported threads.  */
 604           if (threads > 0)
 605             shared /= threads;
 606
 607           /* Account for exclusive L2 and L3 caches.  */
 608           shared += core;
 609         }
 610
 611       if (max_cpuid_ex >= 0x80000001)
 612         {
 613           asm volatile ("cpuid"
 614                         : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
 615                         : "0" (0x80000001));
 616           /*  PREFETCHW     || 3DNow!  */
 617           if ((ecx & 0x100) || (edx & 0x80000000))
 618             __x86_64_prefetchw = -1;
 619         }
 620     }
 621
 622   if (data > 0)
 623     __x86_64_data_cache_size_half = data / 2;
 624
 625   if (shared > 0)
 626     {
 627       __x86_64_shared_cache_size_half = shared / 2;
 628       __x86_64_shared_cache_size = shared;
 629     }
 630 }