?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Consolidate multiple precision sin/cos functions
[glibc.git] / stdlib / longlong.h
blobc4b1b97be0afbff9c8513e9ca7c023a9f7b945c6
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3
4 This file is part of the GNU C Library.
5
6 The GNU C Library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
10
11 In addition to the permissions in the GNU Lesser General Public
12 License, the Free Software Foundation gives you unlimited
13 permission to link the compiled version of this file into
14 combinations with other programs, and to distribute those
15 combinations without any restriction coming from the use of this
16 file. (The Lesser General Public License restrictions do apply in
17 other respects; for example, they cover modification of the file,
18 and distribution when not linked into a combine executable.)
19
20 The GNU C Library is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 Lesser General Public License for more details.
24
25 You should have received a copy of the GNU Lesser General Public
26 License along with the GNU C Library; if not, see
27 <http://www.gnu.org/licenses/>. */
28
29 /* You have to define the following before including this file:
30
31 UWtype -- An unsigned type, default type for operations (typically a "word")
32 UHWtype -- An unsigned type, at least half the size of UWtype.
33 UDWtype -- An unsigned type, at least twice as large a UWtype
34 W_TYPE_SIZE -- size in bits of UWtype
35
36 UQItype -- Unsigned 8 bit type.
37 SItype, USItype -- Signed and unsigned 32 bit types.
38 DItype, UDItype -- Signed and unsigned 64 bit types.
39
40 On a 32 bit machine UWtype should typically be USItype;
41 on a 64 bit machine, UWtype should typically be UDItype. */
42
43 #define __BITS4 (W_TYPE_SIZE / 4)
44 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
45 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
46 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
47
48 #ifndef W_TYPE_SIZE
49 #define W_TYPE_SIZE 32
50 #define UWtype USItype
51 #define UHWtype USItype
52 #define UDWtype UDItype
53 #endif
54
55 /* Used in glibc only. */
56 #ifndef attribute_hidden
57 #define attribute_hidden
58 #endif
59
60 extern const UQItype __clz_tab[256] attribute_hidden;
61
62 /* Define auxiliary asm macros.
63
64 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
65 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
66 word product in HIGH_PROD and LOW_PROD.
67
68 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
69 UDWtype product. This is just a variant of umul_ppmm.
70
71 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
72 denominator) divides a UDWtype, composed by the UWtype integers
73 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
74 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
75 than DENOMINATOR for correct operation. If, in addition, the most
76 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
77 UDIV_NEEDS_NORMALIZATION is defined to 1.
78
79 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
80 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
81 is rounded towards 0.
82
83 5) count_leading_zeros(count, x) counts the number of zero-bits from the
84 msb to the first nonzero bit in the UWtype X. This is the number of
85 steps X needs to be shifted left to set the msb. Undefined for X == 0,
86 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
87
88 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
89 from the least significant end.
90
91 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
92 high_addend_2, low_addend_2) adds two UWtype integers, composed by
93 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
94 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
95 (i.e. carry out) is not stored anywhere, and is lost.
96
97 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
98 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
99 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
100 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
101 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
102 and is lost.
103
104 If any of these macros are left undefined for a particular CPU,
105 C macros are used. */
106
107 /* The CPUs come in alphabetical order below.
108
109 Please add support for more CPUs here, or improve the current support
110 for the CPUs below!
111 (E.g. WE32100, IBM360.) */
112
113 #if defined (__GNUC__) && !defined (NO_ASM)
114
115 /* We sometimes need to clobber "cc" with gcc2, but that would not be
116 understood by gcc1. Use cpp to avoid major code duplication. */
117 #if __GNUC__ < 2
118 #define __CLOBBER_CC
119 #define __AND_CLOBBER_CC
120 #else /* __GNUC__ >= 2 */
121 #define __CLOBBER_CC : "cc"
122 #define __AND_CLOBBER_CC , "cc"
123 #endif /* __GNUC__ < 2 */
124
125 #if defined (__alpha) && W_TYPE_SIZE == 64
126 #define umul_ppmm(ph, pl, m0, m1) \
127 do { \
128 UDItype __m0 = (m0), __m1 = (m1); \
129 (ph) = __builtin_alpha_umulh (__m0, __m1); \
130 (pl) = __m0 * __m1; \
131 } while (0)
132 #define UMUL_TIME 46
133 #ifndef LONGLONG_STANDALONE
134 #define udiv_qrnnd(q, r, n1, n0, d) \
135 do { UDItype __r; \
136 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
137 (r) = __r; \
138 } while (0)
139 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
140 #define UDIV_TIME 220
141 #endif /* LONGLONG_STANDALONE */
142 #ifdef __alpha_cix__
143 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
144 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
145 #define COUNT_LEADING_ZEROS_0 64
146 #else
147 #define count_leading_zeros(COUNT,X) \
148 do { \
149 UDItype __xr = (X), __t, __a; \
150 __t = __builtin_alpha_cmpbge (0, __xr); \
151 __a = __clz_tab[__t ^ 0xff] - 1; \
152 __t = __builtin_alpha_extbl (__xr, __a); \
153 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
154 } while (0)
155 #define count_trailing_zeros(COUNT,X) \
156 do { \
157 UDItype __xr = (X), __t, __a; \
158 __t = __builtin_alpha_cmpbge (0, __xr); \
159 __t = ~__t & -~__t; \
160 __a = ((__t & 0xCC) != 0) * 2; \
161 __a += ((__t & 0xF0) != 0) * 4; \
162 __a += ((__t & 0xAA) != 0); \
163 __t = __builtin_alpha_extbl (__xr, __a); \
164 __a <<= 3; \
165 __t &= -__t; \
166 __a += ((__t & 0xCC) != 0) * 2; \
167 __a += ((__t & 0xF0) != 0) * 4; \
168 __a += ((__t & 0xAA) != 0); \
169 (COUNT) = __a; \
170 } while (0)
171 #endif /* __alpha_cix__ */
172 #endif /* __alpha */
173
174 #if defined (__arc__) && W_TYPE_SIZE == 32
175 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
176 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
177 : "=r" ((USItype) (sh)), \
178 "=&r" ((USItype) (sl)) \
179 : "%r" ((USItype) (ah)), \
180 "rIJ" ((USItype) (bh)), \
181 "%r" ((USItype) (al)), \
182 "rIJ" ((USItype) (bl)))
183 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
184 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
185 : "=r" ((USItype) (sh)), \
186 "=&r" ((USItype) (sl)) \
187 : "r" ((USItype) (ah)), \
188 "rIJ" ((USItype) (bh)), \
189 "r" ((USItype) (al)), \
190 "rIJ" ((USItype) (bl)))
191 /* Call libgcc routine. */
192 #define umul_ppmm(w1, w0, u, v) \
193 do { \
194 DWunion __w; \
195 __w.ll = __umulsidi3 (u, v); \
196 w1 = __w.s.high; \
197 w0 = __w.s.low; \
198 } while (0)
199 #define __umulsidi3 __umulsidi3
200 UDItype __umulsidi3 (USItype, USItype);
201 #endif
202
203 #if defined (__arm__) && (defined (__thumb2__) || !defined (__thumb__)) \
204 && W_TYPE_SIZE == 32
205 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
206 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
207 : "=r" ((USItype) (sh)), \
208 "=&r" ((USItype) (sl)) \
209 : "%r" ((USItype) (ah)), \
210 "rI" ((USItype) (bh)), \
211 "%r" ((USItype) (al)), \
212 "rI" ((USItype) (bl)) __CLOBBER_CC)
213 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
214 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
215 : "=r" ((USItype) (sh)), \
216 "=&r" ((USItype) (sl)) \
217 : "r" ((USItype) (ah)), \
218 "rI" ((USItype) (bh)), \
219 "r" ((USItype) (al)), \
220 "rI" ((USItype) (bl)) __CLOBBER_CC)
221 # if defined(__ARM_ARCH_2__) || defined(__ARM_ARCH_2A__) \
222 || defined(__ARM_ARCH_3__)
223 # define umul_ppmm(xh, xl, a, b) \
224 do { \
225 register USItype __t0, __t1, __t2; \
226 __asm__ ("%@ Inlined umul_ppmm\n" \
227 " mov %2, %5, lsr #16\n" \
228 " mov %0, %6, lsr #16\n" \
229 " bic %3, %5, %2, lsl #16\n" \
230 " bic %4, %6, %0, lsl #16\n" \
231 " mul %1, %3, %4\n" \
232 " mul %4, %2, %4\n" \
233 " mul %3, %0, %3\n" \
234 " mul %0, %2, %0\n" \
235 " adds %3, %4, %3\n" \
236 " addcs %0, %0, #65536\n" \
237 " adds %1, %1, %3, lsl #16\n" \
238 " adc %0, %0, %3, lsr #16" \
239 : "=&r" ((USItype) (xh)), \
240 "=r" ((USItype) (xl)), \
241 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
242 : "r" ((USItype) (a)), \
243 "r" ((USItype) (b)) __CLOBBER_CC ); \
244 } while (0)
245 # define UMUL_TIME 20
246 # else
247 # define umul_ppmm(xh, xl, a, b) \
248 do { \
249 /* Generate umull, under compiler control. */ \
250 register UDItype __t0 = (UDItype)(USItype)(a) * (USItype)(b); \
251 (xl) = (USItype)__t0; \
252 (xh) = (USItype)(__t0 >> 32); \
253 } while (0)
254 # define UMUL_TIME 3
255 # endif
256 # define UDIV_TIME 100
257 #endif /* __arm__ */
258
259 #if defined(__arm__)
260 /* Let gcc decide how best to implement count_leading_zeros. */
261 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
262 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
263 #define COUNT_LEADING_ZEROS_0 32
264 #endif
265
266 #if defined (__AVR__)
267
268 #if W_TYPE_SIZE == 16
269 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
270 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
271 #define COUNT_LEADING_ZEROS_0 16
272 #endif /* W_TYPE_SIZE == 16 */
273
274 #if W_TYPE_SIZE == 32
275 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
276 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
277 #define COUNT_LEADING_ZEROS_0 32
278 #endif /* W_TYPE_SIZE == 32 */
279
280 #if W_TYPE_SIZE == 64
281 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzll (X))
282 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzll (X))
283 #define COUNT_LEADING_ZEROS_0 64
284 #endif /* W_TYPE_SIZE == 64 */
285
286 #endif /* defined (__AVR__) */
287
288 #if defined (__CRIS__) && __CRIS_arch_version >= 3
289 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
290 #if __CRIS_arch_version >= 8
291 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
292 #endif
293 #endif /* __CRIS__ */
294
295 #if defined (__hppa) && W_TYPE_SIZE == 32
296 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
297 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
298 : "=r" ((USItype) (sh)), \
299 "=&r" ((USItype) (sl)) \
300 : "%rM" ((USItype) (ah)), \
301 "rM" ((USItype) (bh)), \
302 "%rM" ((USItype) (al)), \
303 "rM" ((USItype) (bl)))
304 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
305 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
306 : "=r" ((USItype) (sh)), \
307 "=&r" ((USItype) (sl)) \
308 : "rM" ((USItype) (ah)), \
309 "rM" ((USItype) (bh)), \
310 "rM" ((USItype) (al)), \
311 "rM" ((USItype) (bl)))
312 #if defined (_PA_RISC1_1)
313 #define umul_ppmm(w1, w0, u, v) \
314 do { \
315 union \
316 { \
317 UDItype __f; \
318 struct {USItype __w1, __w0;} __w1w0; \
319 } __t; \
320 __asm__ ("xmpyu %1,%2,%0" \
321 : "=x" (__t.__f) \
322 : "x" ((USItype) (u)), \
323 "x" ((USItype) (v))); \
324 (w1) = __t.__w1w0.__w1; \
325 (w0) = __t.__w1w0.__w0; \
326 } while (0)
327 #define UMUL_TIME 8
328 #else
329 #define UMUL_TIME 30
330 #endif
331 #define UDIV_TIME 40
332 #define count_leading_zeros(count, x) \
333 do { \
334 USItype __tmp; \
335 __asm__ ( \
336 "ldi 1,%0\n" \
337 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
338 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
339 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
340 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
341 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
342 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
343 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
344 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
345 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
346 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
347 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
348 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
349 " extru %1,30,1,%1 ; Extract bit 1.\n" \
350 " sub %0,%1,%0 ; Subtract it.\n" \
351 : "=r" (count), "=r" (__tmp) : "1" (x)); \
352 } while (0)
353 #endif
354
355 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
356 #if !defined (__zarch__)
357 #define smul_ppmm(xh, xl, m0, m1) \
358 do { \
359 union {DItype __ll; \
360 struct {USItype __h, __l;} __i; \
361 } __x; \
362 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
363 : "=&r" (__x.__ll) \
364 : "r" (m0), "r" (m1)); \
365 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
366 } while (0)
367 #define sdiv_qrnnd(q, r, n1, n0, d) \
368 do { \
369 union {DItype __ll; \
370 struct {USItype __h, __l;} __i; \
371 } __x; \
372 __x.__i.__h = n1; __x.__i.__l = n0; \
373 __asm__ ("dr %0,%2" \
374 : "=r" (__x.__ll) \
375 : "0" (__x.__ll), "r" (d)); \
376 (q) = __x.__i.__l; (r) = __x.__i.__h; \
377 } while (0)
378 #else
379 #define smul_ppmm(xh, xl, m0, m1) \
380 do { \
381 register SItype __r0 __asm__ ("0"); \
382 register SItype __r1 __asm__ ("1") = (m0); \
383 \
384 __asm__ ("mr\t%%r0,%3" \
385 : "=r" (__r0), "=r" (__r1) \
386 : "r" (__r1), "r" (m1)); \
387 (xh) = __r0; (xl) = __r1; \
388 } while (0)
389
390 #define sdiv_qrnnd(q, r, n1, n0, d) \
391 do { \
392 register SItype __r0 __asm__ ("0") = (n1); \
393 register SItype __r1 __asm__ ("1") = (n0); \
394 \
395 __asm__ ("dr\t%%r0,%4" \
396 : "=r" (__r0), "=r" (__r1) \
397 : "r" (__r0), "r" (__r1), "r" (d)); \
398 (q) = __r1; (r) = __r0; \
399 } while (0)
400 #endif /* __zarch__ */
401 #endif
402
403 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
404 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
405 __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
406 : "=r" ((USItype) (sh)), \
407 "=&r" ((USItype) (sl)) \
408 : "%0" ((USItype) (ah)), \
409 "g" ((USItype) (bh)), \
410 "%1" ((USItype) (al)), \
411 "g" ((USItype) (bl)))
412 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
413 __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
414 : "=r" ((USItype) (sh)), \
415 "=&r" ((USItype) (sl)) \
416 : "0" ((USItype) (ah)), \
417 "g" ((USItype) (bh)), \
418 "1" ((USItype) (al)), \
419 "g" ((USItype) (bl)))
420 #define umul_ppmm(w1, w0, u, v) \
421 __asm__ ("mul{l} %3" \
422 : "=a" ((USItype) (w0)), \
423 "=d" ((USItype) (w1)) \
424 : "%0" ((USItype) (u)), \
425 "rm" ((USItype) (v)))
426 #define udiv_qrnnd(q, r, n1, n0, dv) \
427 __asm__ ("div{l} %4" \
428 : "=a" ((USItype) (q)), \
429 "=d" ((USItype) (r)) \
430 : "0" ((USItype) (n0)), \
431 "1" ((USItype) (n1)), \
432 "rm" ((USItype) (dv)))
433 #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
434 #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
435 #define UMUL_TIME 40
436 #define UDIV_TIME 40
437 #endif /* 80x86 */
438
439 #if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
440 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
441 __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
442 : "=r" ((UDItype) (sh)), \
443 "=&r" ((UDItype) (sl)) \
444 : "%0" ((UDItype) (ah)), \
445 "rme" ((UDItype) (bh)), \
446 "%1" ((UDItype) (al)), \
447 "rme" ((UDItype) (bl)))
448 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
449 __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
450 : "=r" ((UDItype) (sh)), \
451 "=&r" ((UDItype) (sl)) \
452 : "0" ((UDItype) (ah)), \
453 "rme" ((UDItype) (bh)), \
454 "1" ((UDItype) (al)), \
455 "rme" ((UDItype) (bl)))
456 #define umul_ppmm(w1, w0, u, v) \
457 __asm__ ("mul{q} %3" \
458 : "=a" ((UDItype) (w0)), \
459 "=d" ((UDItype) (w1)) \
460 : "%0" ((UDItype) (u)), \
461 "rm" ((UDItype) (v)))
462 #define udiv_qrnnd(q, r, n1, n0, dv) \
463 __asm__ ("div{q} %4" \
464 : "=a" ((UDItype) (q)), \
465 "=d" ((UDItype) (r)) \
466 : "0" ((UDItype) (n0)), \
467 "1" ((UDItype) (n1)), \
468 "rm" ((UDItype) (dv)))
469 #define count_leading_zeros(count, x) ((count) = __builtin_clzll (x))
470 #define count_trailing_zeros(count, x) ((count) = __builtin_ctzll (x))
471 #define UMUL_TIME 40
472 #define UDIV_TIME 40
473 #endif /* x86_64 */
474
475 #if defined (__i960__) && W_TYPE_SIZE == 32
476 #define umul_ppmm(w1, w0, u, v) \
477 ({union {UDItype __ll; \
478 struct {USItype __l, __h;} __i; \
479 } __xx; \
480 __asm__ ("emul %2,%1,%0" \
481 : "=d" (__xx.__ll) \
482 : "%dI" ((USItype) (u)), \
483 "dI" ((USItype) (v))); \
484 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
485 #define __umulsidi3(u, v) \
486 ({UDItype __w; \
487 __asm__ ("emul %2,%1,%0" \
488 : "=d" (__w) \
489 : "%dI" ((USItype) (u)), \
490 "dI" ((USItype) (v))); \
491 __w; })
492 #endif /* __i960__ */
493
494 #if defined (__ia64) && W_TYPE_SIZE == 64
495 /* This form encourages gcc (pre-release 3.4 at least) to emit predicated
496 "sub r=r,r" and "sub r=r,r,1", giving a 2 cycle latency. The generic
497 code using "al<bl" arithmetically comes out making an actual 0 or 1 in a
498 register, which takes an extra cycle. */
499 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
500 do { \
501 UWtype __x; \
502 __x = (al) - (bl); \
503 if ((al) < (bl)) \
504 (sh) = (ah) - (bh) - 1; \
505 else \
506 (sh) = (ah) - (bh); \
507 (sl) = __x; \
508 } while (0)
509
510 /* Do both product parts in assembly, since that gives better code with
511 all gcc versions. Some callers will just use the upper part, and in
512 that situation we waste an instruction, but not any cycles. */
513 #define umul_ppmm(ph, pl, m0, m1) \
514 __asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0" \
515 : "=&f" (ph), "=f" (pl) \
516 : "f" (m0), "f" (m1))
517 #define count_leading_zeros(count, x) \
518 do { \
519 UWtype _x = (x), _y, _a, _c; \
520 __asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x)); \
521 __asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y)); \
522 _c = (_a - 1) << 3; \
523 _x >>= _c; \
524 if (_x >= 1 << 4) \
525 _x >>= 4, _c += 4; \
526 if (_x >= 1 << 2) \
527 _x >>= 2, _c += 2; \
528 _c += _x >> 1; \
529 (count) = W_TYPE_SIZE - 1 - _c; \
530 } while (0)
531 /* similar to what gcc does for __builtin_ffs, but 0 based rather than 1
532 based, and we don't need a special case for x==0 here */
533 #define count_trailing_zeros(count, x) \
534 do { \
535 UWtype __ctz_x = (x); \
536 __asm__ ("popcnt %0 = %1" \
537 : "=r" (count) \
538 : "r" ((__ctz_x-1) & ~__ctz_x)); \
539 } while (0)
540 #define UMUL_TIME 14
541 #endif
542
543 #if defined (__M32R__) && W_TYPE_SIZE == 32
544 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
545 /* The cmp clears the condition bit. */ \
546 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
547 : "=r" ((USItype) (sh)), \
548 "=&r" ((USItype) (sl)) \
549 : "0" ((USItype) (ah)), \
550 "r" ((USItype) (bh)), \
551 "1" ((USItype) (al)), \
552 "r" ((USItype) (bl)) \
553 : "cbit")
554 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
555 /* The cmp clears the condition bit. */ \
556 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
557 : "=r" ((USItype) (sh)), \
558 "=&r" ((USItype) (sl)) \
559 : "0" ((USItype) (ah)), \
560 "r" ((USItype) (bh)), \
561 "1" ((USItype) (al)), \
562 "r" ((USItype) (bl)) \
563 : "cbit")
564 #endif /* __M32R__ */
565
566 #if defined (__mc68000__) && W_TYPE_SIZE == 32
567 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
568 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
569 : "=d" ((USItype) (sh)), \
570 "=&d" ((USItype) (sl)) \
571 : "%0" ((USItype) (ah)), \
572 "d" ((USItype) (bh)), \
573 "%1" ((USItype) (al)), \
574 "g" ((USItype) (bl)))
575 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
576 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
577 : "=d" ((USItype) (sh)), \
578 "=&d" ((USItype) (sl)) \
579 : "0" ((USItype) (ah)), \
580 "d" ((USItype) (bh)), \
581 "1" ((USItype) (al)), \
582 "g" ((USItype) (bl)))
583
584 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
585 #if (defined (__mc68020__) && !defined (__mc68060__))
586 #define umul_ppmm(w1, w0, u, v) \
587 __asm__ ("mulu%.l %3,%1:%0" \
588 : "=d" ((USItype) (w0)), \
589 "=d" ((USItype) (w1)) \
590 : "%0" ((USItype) (u)), \
591 "dmi" ((USItype) (v)))
592 #define UMUL_TIME 45
593 #define udiv_qrnnd(q, r, n1, n0, d) \
594 __asm__ ("divu%.l %4,%1:%0" \
595 : "=d" ((USItype) (q)), \
596 "=d" ((USItype) (r)) \
597 : "0" ((USItype) (n0)), \
598 "1" ((USItype) (n1)), \
599 "dmi" ((USItype) (d)))
600 #define UDIV_TIME 90
601 #define sdiv_qrnnd(q, r, n1, n0, d) \
602 __asm__ ("divs%.l %4,%1:%0" \
603 : "=d" ((USItype) (q)), \
604 "=d" ((USItype) (r)) \
605 : "0" ((USItype) (n0)), \
606 "1" ((USItype) (n1)), \
607 "dmi" ((USItype) (d)))
608
609 #elif defined (__mcoldfire__) /* not mc68020 */
610
611 #define umul_ppmm(xh, xl, a, b) \
612 __asm__ ("| Inlined umul_ppmm\n" \
613 " move%.l %2,%/d0\n" \
614 " move%.l %3,%/d1\n" \
615 " move%.l %/d0,%/d2\n" \
616 " swap %/d0\n" \
617 " move%.l %/d1,%/d3\n" \
618 " swap %/d1\n" \
619 " move%.w %/d2,%/d4\n" \
620 " mulu %/d3,%/d4\n" \
621 " mulu %/d1,%/d2\n" \
622 " mulu %/d0,%/d3\n" \
623 " mulu %/d0,%/d1\n" \
624 " move%.l %/d4,%/d0\n" \
625 " clr%.w %/d0\n" \
626 " swap %/d0\n" \
627 " add%.l %/d0,%/d2\n" \
628 " add%.l %/d3,%/d2\n" \
629 " jcc 1f\n" \
630 " add%.l %#65536,%/d1\n" \
631 "1: swap %/d2\n" \
632 " moveq %#0,%/d0\n" \
633 " move%.w %/d2,%/d0\n" \
634 " move%.w %/d4,%/d2\n" \
635 " move%.l %/d2,%1\n" \
636 " add%.l %/d1,%/d0\n" \
637 " move%.l %/d0,%0" \
638 : "=g" ((USItype) (xh)), \
639 "=g" ((USItype) (xl)) \
640 : "g" ((USItype) (a)), \
641 "g" ((USItype) (b)) \
642 : "d0", "d1", "d2", "d3", "d4")
643 #define UMUL_TIME 100
644 #define UDIV_TIME 400
645 #else /* not ColdFire */
646 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
647 #define umul_ppmm(xh, xl, a, b) \
648 __asm__ ("| Inlined umul_ppmm\n" \
649 " move%.l %2,%/d0\n" \
650 " move%.l %3,%/d1\n" \
651 " move%.l %/d0,%/d2\n" \
652 " swap %/d0\n" \
653 " move%.l %/d1,%/d3\n" \
654 " swap %/d1\n" \
655 " move%.w %/d2,%/d4\n" \
656 " mulu %/d3,%/d4\n" \
657 " mulu %/d1,%/d2\n" \
658 " mulu %/d0,%/d3\n" \
659 " mulu %/d0,%/d1\n" \
660 " move%.l %/d4,%/d0\n" \
661 " eor%.w %/d0,%/d0\n" \
662 " swap %/d0\n" \
663 " add%.l %/d0,%/d2\n" \
664 " add%.l %/d3,%/d2\n" \
665 " jcc 1f\n" \
666 " add%.l %#65536,%/d1\n" \
667 "1: swap %/d2\n" \
668 " moveq %#0,%/d0\n" \
669 " move%.w %/d2,%/d0\n" \
670 " move%.w %/d4,%/d2\n" \
671 " move%.l %/d2,%1\n" \
672 " add%.l %/d1,%/d0\n" \
673 " move%.l %/d0,%0" \
674 : "=g" ((USItype) (xh)), \
675 "=g" ((USItype) (xl)) \
676 : "g" ((USItype) (a)), \
677 "g" ((USItype) (b)) \
678 : "d0", "d1", "d2", "d3", "d4")
679 #define UMUL_TIME 100
680 #define UDIV_TIME 400
681
682 #endif /* not mc68020 */
683
684 /* The '020, '030, '040 and '060 have bitfield insns.
685 cpu32 disguises as a 68020, but lacks them. */
686 #if defined (__mc68020__) && !defined (__mcpu32__)
687 #define count_leading_zeros(count, x) \
688 __asm__ ("bfffo %1{%b2:%b2},%0" \
689 : "=d" ((USItype) (count)) \
690 : "od" ((USItype) (x)), "n" (0))
691 /* Some ColdFire architectures have a ff1 instruction supported via
692 __builtin_clz. */
693 #elif defined (__mcfisaaplus__) || defined (__mcfisac__)
694 #define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
695 #define COUNT_LEADING_ZEROS_0 32
696 #endif
697 #endif /* mc68000 */
698
699 #if defined (__m88000__) && W_TYPE_SIZE == 32
700 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
701 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
702 : "=r" ((USItype) (sh)), \
703 "=&r" ((USItype) (sl)) \
704 : "%rJ" ((USItype) (ah)), \
705 "rJ" ((USItype) (bh)), \
706 "%rJ" ((USItype) (al)), \
707 "rJ" ((USItype) (bl)))
708 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
709 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
710 : "=r" ((USItype) (sh)), \
711 "=&r" ((USItype) (sl)) \
712 : "rJ" ((USItype) (ah)), \
713 "rJ" ((USItype) (bh)), \
714 "rJ" ((USItype) (al)), \
715 "rJ" ((USItype) (bl)))
716 #define count_leading_zeros(count, x) \
717 do { \
718 USItype __cbtmp; \
719 __asm__ ("ff1 %0,%1" \
720 : "=r" (__cbtmp) \
721 : "r" ((USItype) (x))); \
722 (count) = __cbtmp ^ 31; \
723 } while (0)
724 #define COUNT_LEADING_ZEROS_0 63 /* sic */
725 #if defined (__mc88110__)
726 #define umul_ppmm(wh, wl, u, v) \
727 do { \
728 union {UDItype __ll; \
729 struct {USItype __h, __l;} __i; \
730 } __xx; \
731 __asm__ ("mulu.d %0,%1,%2" \
732 : "=r" (__xx.__ll) \
733 : "r" ((USItype) (u)), \
734 "r" ((USItype) (v))); \
735 (wh) = __xx.__i.__h; \
736 (wl) = __xx.__i.__l; \
737 } while (0)
738 #define udiv_qrnnd(q, r, n1, n0, d) \
739 ({union {UDItype __ll; \
740 struct {USItype __h, __l;} __i; \
741 } __xx; \
742 USItype __q; \
743 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
744 __asm__ ("divu.d %0,%1,%2" \
745 : "=r" (__q) \
746 : "r" (__xx.__ll), \
747 "r" ((USItype) (d))); \
748 (r) = (n0) - __q * (d); (q) = __q; })
749 #define UMUL_TIME 5
750 #define UDIV_TIME 25
751 #else
752 #define UMUL_TIME 17
753 #define UDIV_TIME 150
754 #endif /* __mc88110__ */
755 #endif /* __m88000__ */
756
757 #if defined (__mn10300__)
758 # if defined (__AM33__)
759 # define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
760 # define umul_ppmm(w1, w0, u, v) \
761 asm("mulu %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
762 # define smul_ppmm(w1, w0, u, v) \
763 asm("mul %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
764 # else
765 # define umul_ppmm(w1, w0, u, v) \
766 asm("nop; nop; mulu %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
767 # define smul_ppmm(w1, w0, u, v) \
768 asm("nop; nop; mul %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
769 # endif
770 # define add_ssaaaa(sh, sl, ah, al, bh, bl) \
771 do { \
772 DWunion __s, __a, __b; \
773 __a.s.low = (al); __a.s.high = (ah); \
774 __b.s.low = (bl); __b.s.high = (bh); \
775 __s.ll = __a.ll + __b.ll; \
776 (sl) = __s.s.low; (sh) = __s.s.high; \
777 } while (0)
778 # define sub_ddmmss(sh, sl, ah, al, bh, bl) \
779 do { \
780 DWunion __s, __a, __b; \
781 __a.s.low = (al); __a.s.high = (ah); \
782 __b.s.low = (bl); __b.s.high = (bh); \
783 __s.ll = __a.ll - __b.ll; \
784 (sl) = __s.s.low; (sh) = __s.s.high; \
785 } while (0)
786 # define udiv_qrnnd(q, r, nh, nl, d) \
787 asm("divu %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
788 # define sdiv_qrnnd(q, r, nh, nl, d) \
789 asm("div %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
790 # define UMUL_TIME 3
791 # define UDIV_TIME 38
792 #endif
793
794 #if defined (__mips__) && W_TYPE_SIZE == 32
795 #define umul_ppmm(w1, w0, u, v) \
796 do { \
797 UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
798 (w1) = (USItype) (__x >> 32); \
799 (w0) = (USItype) (__x); \
800 } while (0)
801 #define UMUL_TIME 10
802 #define UDIV_TIME 100
803
804 #if (__mips == 32 || __mips == 64) && ! __mips16
805 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
806 #define COUNT_LEADING_ZEROS_0 32
807 #endif
808 #endif /* __mips__ */
809
810 #if defined (__ns32000__) && W_TYPE_SIZE == 32
811 #define umul_ppmm(w1, w0, u, v) \
812 ({union {UDItype __ll; \
813 struct {USItype __l, __h;} __i; \
814 } __xx; \
815 __asm__ ("meid %2,%0" \
816 : "=g" (__xx.__ll) \
817 : "%0" ((USItype) (u)), \
818 "g" ((USItype) (v))); \
819 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
820 #define __umulsidi3(u, v) \
821 ({UDItype __w; \
822 __asm__ ("meid %2,%0" \
823 : "=g" (__w) \
824 : "%0" ((USItype) (u)), \
825 "g" ((USItype) (v))); \
826 __w; })
827 #define udiv_qrnnd(q, r, n1, n0, d) \
828 ({union {UDItype __ll; \
829 struct {USItype __l, __h;} __i; \
830 } __xx; \
831 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
832 __asm__ ("deid %2,%0" \
833 : "=g" (__xx.__ll) \
834 : "0" (__xx.__ll), \
835 "g" ((USItype) (d))); \
836 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
837 #define count_trailing_zeros(count,x) \
838 do { \
839 __asm__ ("ffsd %2,%0" \
840 : "=r" ((USItype) (count)) \
841 : "0" ((USItype) 0), \
842 "r" ((USItype) (x))); \
843 } while (0)
844 #endif /* __ns32000__ */
845
846 /* FIXME: We should test _IBMR2 here when we add assembly support for the
847 system vendor compilers.
848 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
849 enough, since that hits ARM and m68k too. */
850 #if (defined (_ARCH_PPC) /* AIX */ \
851 || defined (__powerpc__) /* gcc */ \
852 || defined (__POWERPC__) /* BEOS */ \
853 || defined (__ppc__) /* Darwin */ \
854 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
855 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
856 && CPU_FAMILY == PPC) \
857 ) && W_TYPE_SIZE == 32
858 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
859 do { \
860 if (__builtin_constant_p (bh) && (bh) == 0) \
861 __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
862 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
863 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
864 __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
865 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
866 else \
867 __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
868 : "=r" (sh), "=&r" (sl) \
869 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
870 } while (0)
871 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
872 do { \
873 if (__builtin_constant_p (ah) && (ah) == 0) \
874 __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
875 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
876 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
877 __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
878 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
879 else if (__builtin_constant_p (bh) && (bh) == 0) \
880 __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
881 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
882 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
883 __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
884 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
885 else \
886 __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
887 : "=r" (sh), "=&r" (sl) \
888 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
889 } while (0)
890 #define count_leading_zeros(count, x) \
891 __asm__ ("cntlzw %0,%1" : "=r" (count) : "r" (x))
892 #define COUNT_LEADING_ZEROS_0 32
893 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
894 || defined (__ppc__) \
895 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
896 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
897 && CPU_FAMILY == PPC)
898 #define umul_ppmm(ph, pl, m0, m1) \
899 do { \
900 USItype __m0 = (m0), __m1 = (m1); \
901 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
902 (pl) = __m0 * __m1; \
903 } while (0)
904 #define UMUL_TIME 15
905 #define smul_ppmm(ph, pl, m0, m1) \
906 do { \
907 SItype __m0 = (m0), __m1 = (m1); \
908 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
909 (pl) = __m0 * __m1; \
910 } while (0)
911 #define SMUL_TIME 14
912 #define UDIV_TIME 120
913 #endif
914 #endif /* 32-bit POWER architecture variants. */
915
916 /* We should test _IBMR2 here when we add assembly support for the system
917 vendor compilers. */
918 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
919 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
920 do { \
921 if (__builtin_constant_p (bh) && (bh) == 0) \
922 __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
923 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
924 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
925 __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
926 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
927 else \
928 __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
929 : "=r" (sh), "=&r" (sl) \
930 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
931 } while (0)
932 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
933 do { \
934 if (__builtin_constant_p (ah) && (ah) == 0) \
935 __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
936 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
937 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
938 __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
939 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
940 else if (__builtin_constant_p (bh) && (bh) == 0) \
941 __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
942 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
943 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
944 __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
945 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
946 else \
947 __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
948 : "=r" (sh), "=&r" (sl) \
949 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
950 } while (0)
951 #define count_leading_zeros(count, x) \
952 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
953 #define COUNT_LEADING_ZEROS_0 64
954 #define umul_ppmm(ph, pl, m0, m1) \
955 do { \
956 UDItype __m0 = (m0), __m1 = (m1); \
957 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
958 (pl) = __m0 * __m1; \
959 } while (0)
960 #define UMUL_TIME 15
961 #define smul_ppmm(ph, pl, m0, m1) \
962 do { \
963 DItype __m0 = (m0), __m1 = (m1); \
964 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
965 (pl) = __m0 * __m1; \
966 } while (0)
967 #define SMUL_TIME 14 /* ??? */
968 #define UDIV_TIME 120 /* ??? */
969 #endif /* 64-bit PowerPC. */
970
971 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
972 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
973 __asm__ ("a %1,%5\n\tae %0,%3" \
974 : "=r" ((USItype) (sh)), \
975 "=&r" ((USItype) (sl)) \
976 : "%0" ((USItype) (ah)), \
977 "r" ((USItype) (bh)), \
978 "%1" ((USItype) (al)), \
979 "r" ((USItype) (bl)))
980 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
981 __asm__ ("s %1,%5\n\tse %0,%3" \
982 : "=r" ((USItype) (sh)), \
983 "=&r" ((USItype) (sl)) \
984 : "0" ((USItype) (ah)), \
985 "r" ((USItype) (bh)), \
986 "1" ((USItype) (al)), \
987 "r" ((USItype) (bl)))
988 #define umul_ppmm(ph, pl, m0, m1) \
989 do { \
990 USItype __m0 = (m0), __m1 = (m1); \
991 __asm__ ( \
992 "s r2,r2\n" \
993 " mts r10,%2\n" \
994 " m r2,%3\n" \
995 " m r2,%3\n" \
996 " m r2,%3\n" \
997 " m r2,%3\n" \
998 " m r2,%3\n" \
999 " m r2,%3\n" \
1000 " m r2,%3\n" \
1001 " m r2,%3\n" \
1002 " m r2,%3\n" \
1003 " m r2,%3\n" \
1004 " m r2,%3\n" \
1005 " m r2,%3\n" \
1006 " m r2,%3\n" \
1007 " m r2,%3\n" \
1008 " m r2,%3\n" \
1009 " m r2,%3\n" \
1010 " cas %0,r2,r0\n" \
1011 " mfs r10,%1" \
1012 : "=r" ((USItype) (ph)), \
1013 "=r" ((USItype) (pl)) \
1014 : "%r" (__m0), \
1015 "r" (__m1) \
1016 : "r2"); \
1017 (ph) += ((((SItype) __m0 >> 31) & __m1) \
1018 + (((SItype) __m1 >> 31) & __m0)); \
1019 } while (0)
1020 #define UMUL_TIME 20
1021 #define UDIV_TIME 200
1022 #define count_leading_zeros(count, x) \
1023 do { \
1024 if ((x) >= 0x10000) \
1025 __asm__ ("clz %0,%1" \
1026 : "=r" ((USItype) (count)) \
1027 : "r" ((USItype) (x) >> 16)); \
1028 else \
1029 { \
1030 __asm__ ("clz %0,%1" \
1031 : "=r" ((USItype) (count)) \
1032 : "r" ((USItype) (x))); \
1033 (count) += 16; \
1034 } \
1035 } while (0)
1036 #endif
1037
1038 #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
1039 #ifndef __sh1__
1040 #define umul_ppmm(w1, w0, u, v) \
1041 __asm__ ( \
1042 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
1043 : "=r<" ((USItype)(w1)), \
1044 "=r<" ((USItype)(w0)) \
1045 : "r" ((USItype)(u)), \
1046 "r" ((USItype)(v)) \
1047 : "macl", "mach")
1048 #define UMUL_TIME 5
1049 #endif
1050
1051 /* This is the same algorithm as __udiv_qrnnd_c. */
1052 #define UDIV_NEEDS_NORMALIZATION 1
1053
1054 #define udiv_qrnnd(q, r, n1, n0, d) \
1055 do { \
1056 extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
1057 __attribute__ ((visibility ("hidden"))); \
1058 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
1059 __asm__ ( \
1060 "mov%M4 %4,r5\n" \
1061 " swap.w %3,r4\n" \
1062 " swap.w r5,r6\n" \
1063 " jsr @%5\n" \
1064 " shll16 r6\n" \
1065 " swap.w r4,r4\n" \
1066 " jsr @%5\n" \
1067 " swap.w r1,%0\n" \
1068 " or r1,%0" \
1069 : "=r" (q), "=&z" (r) \
1070 : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
1071 : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
1072 } while (0)
1073
1074 #define UDIV_TIME 80
1075
1076 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1077 __asm__ ("clrt;subc %5,%1; subc %4,%0" \
1078 : "=r" (sh), "=r" (sl) \
1079 : "0" (ah), "1" (al), "r" (bh), "r" (bl) : "t")
1080
1081 #endif /* __sh__ */
1082
1083 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
1084 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
1085 #define count_leading_zeros(count, x) \
1086 do \
1087 { \
1088 UDItype x_ = (USItype)(x); \
1089 SItype c_; \
1090 \
1091 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
1092 (count) = c_ - 31; \
1093 } \
1094 while (0)
1095 #define COUNT_LEADING_ZEROS_0 32
1096 #endif
1097
1098 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
1099 && W_TYPE_SIZE == 32
1100 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1101 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
1102 : "=r" ((USItype) (sh)), \
1103 "=&r" ((USItype) (sl)) \
1104 : "%rJ" ((USItype) (ah)), \
1105 "rI" ((USItype) (bh)), \
1106 "%rJ" ((USItype) (al)), \
1107 "rI" ((USItype) (bl)) \
1108 __CLOBBER_CC)
1109 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1110 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
1111 : "=r" ((USItype) (sh)), \
1112 "=&r" ((USItype) (sl)) \
1113 : "rJ" ((USItype) (ah)), \
1114 "rI" ((USItype) (bh)), \
1115 "rJ" ((USItype) (al)), \
1116 "rI" ((USItype) (bl)) \
1117 __CLOBBER_CC)
1118 #if defined (__sparc_v9__)
1119 #define umul_ppmm(w1, w0, u, v) \
1120 do { \
1121 register USItype __g1 asm ("g1"); \
1122 __asm__ ("umul\t%2,%3,%1\n\t" \
1123 "srlx\t%1, 32, %0" \
1124 : "=r" ((USItype) (w1)), \
1125 "=r" (__g1) \
1126 : "r" ((USItype) (u)), \
1127 "r" ((USItype) (v))); \
1128 (w0) = __g1; \
1129 } while (0)
1130 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1131 __asm__ ("mov\t%2,%%y\n\t" \
1132 "udiv\t%3,%4,%0\n\t" \
1133 "umul\t%0,%4,%1\n\t" \
1134 "sub\t%3,%1,%1" \
1135 : "=&r" ((USItype) (__q)), \
1136 "=&r" ((USItype) (__r)) \
1137 : "r" ((USItype) (__n1)), \
1138 "r" ((USItype) (__n0)), \
1139 "r" ((USItype) (__d)))
1140 #else
1141 #if defined (__sparc_v8__)
1142 #define umul_ppmm(w1, w0, u, v) \
1143 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1144 : "=r" ((USItype) (w1)), \
1145 "=r" ((USItype) (w0)) \
1146 : "r" ((USItype) (u)), \
1147 "r" ((USItype) (v)))
1148 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1149 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
1150 : "=&r" ((USItype) (__q)), \
1151 "=&r" ((USItype) (__r)) \
1152 : "r" ((USItype) (__n1)), \
1153 "r" ((USItype) (__n0)), \
1154 "r" ((USItype) (__d)))
1155 #else
1156 #if defined (__sparclite__)
1157 /* This has hardware multiply but not divide. It also has two additional
1158 instructions scan (ffs from high bit) and divscc. */
1159 #define umul_ppmm(w1, w0, u, v) \
1160 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1161 : "=r" ((USItype) (w1)), \
1162 "=r" ((USItype) (w0)) \
1163 : "r" ((USItype) (u)), \
1164 "r" ((USItype) (v)))
1165 #define udiv_qrnnd(q, r, n1, n0, d) \
1166 __asm__ ("! Inlined udiv_qrnnd\n" \
1167 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
1168 " tst %%g0\n" \
1169 " divscc %3,%4,%%g1\n" \
1170 " divscc %%g1,%4,%%g1\n" \
1171 " divscc %%g1,%4,%%g1\n" \
1172 " divscc %%g1,%4,%%g1\n" \
1173 " divscc %%g1,%4,%%g1\n" \
1174 " divscc %%g1,%4,%%g1\n" \
1175 " divscc %%g1,%4,%%g1\n" \
1176 " divscc %%g1,%4,%%g1\n" \
1177 " divscc %%g1,%4,%%g1\n" \
1178 " divscc %%g1,%4,%%g1\n" \
1179 " divscc %%g1,%4,%%g1\n" \
1180 " divscc %%g1,%4,%%g1\n" \
1181 " divscc %%g1,%4,%%g1\n" \
1182 " divscc %%g1,%4,%%g1\n" \
1183 " divscc %%g1,%4,%%g1\n" \
1184 " divscc %%g1,%4,%%g1\n" \
1185 " divscc %%g1,%4,%%g1\n" \
1186 " divscc %%g1,%4,%%g1\n" \
1187 " divscc %%g1,%4,%%g1\n" \
1188 " divscc %%g1,%4,%%g1\n" \
1189 " divscc %%g1,%4,%%g1\n" \
1190 " divscc %%g1,%4,%%g1\n" \
1191 " divscc %%g1,%4,%%g1\n" \
1192 " divscc %%g1,%4,%%g1\n" \
1193 " divscc %%g1,%4,%%g1\n" \
1194 " divscc %%g1,%4,%%g1\n" \
1195 " divscc %%g1,%4,%%g1\n" \
1196 " divscc %%g1,%4,%%g1\n" \
1197 " divscc %%g1,%4,%%g1\n" \
1198 " divscc %%g1,%4,%%g1\n" \
1199 " divscc %%g1,%4,%%g1\n" \
1200 " divscc %%g1,%4,%0\n" \
1201 " rd %%y,%1\n" \
1202 " bl,a 1f\n" \
1203 " add %1,%4,%1\n" \
1204 "1: ! End of inline udiv_qrnnd" \
1205 : "=r" ((USItype) (q)), \
1206 "=r" ((USItype) (r)) \
1207 : "r" ((USItype) (n1)), \
1208 "r" ((USItype) (n0)), \
1209 "rI" ((USItype) (d)) \
1210 : "g1" __AND_CLOBBER_CC)
1211 #define UDIV_TIME 37
1212 #define count_leading_zeros(count, x) \
1213 do { \
1214 __asm__ ("scan %1,1,%0" \
1215 : "=r" ((USItype) (count)) \
1216 : "r" ((USItype) (x))); \
1217 } while (0)
1218 /* Early sparclites return 63 for an argument of 0, but they warn that future
1219 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
1220 undefined. */
1221 #else
1222 /* SPARC without integer multiplication and divide instructions.
1223 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
1224 #define umul_ppmm(w1, w0, u, v) \
1225 __asm__ ("! Inlined umul_ppmm\n" \
1226 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
1227 " sra %3,31,%%o5 ! Don't move this insn\n" \
1228 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
1229 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1230 " mulscc %%g1,%3,%%g1\n" \
1231 " mulscc %%g1,%3,%%g1\n" \
1232 " mulscc %%g1,%3,%%g1\n" \
1233 " mulscc %%g1,%3,%%g1\n" \
1234 " mulscc %%g1,%3,%%g1\n" \
1235 " mulscc %%g1,%3,%%g1\n" \
1236 " mulscc %%g1,%3,%%g1\n" \
1237 " mulscc %%g1,%3,%%g1\n" \
1238 " mulscc %%g1,%3,%%g1\n" \
1239 " mulscc %%g1,%3,%%g1\n" \
1240 " mulscc %%g1,%3,%%g1\n" \
1241 " mulscc %%g1,%3,%%g1\n" \
1242 " mulscc %%g1,%3,%%g1\n" \
1243 " mulscc %%g1,%3,%%g1\n" \
1244 " mulscc %%g1,%3,%%g1\n" \
1245 " mulscc %%g1,%3,%%g1\n" \
1246 " mulscc %%g1,%3,%%g1\n" \
1247 " mulscc %%g1,%3,%%g1\n" \
1248 " mulscc %%g1,%3,%%g1\n" \
1249 " mulscc %%g1,%3,%%g1\n" \
1250 " mulscc %%g1,%3,%%g1\n" \
1251 " mulscc %%g1,%3,%%g1\n" \
1252 " mulscc %%g1,%3,%%g1\n" \
1253 " mulscc %%g1,%3,%%g1\n" \
1254 " mulscc %%g1,%3,%%g1\n" \
1255 " mulscc %%g1,%3,%%g1\n" \
1256 " mulscc %%g1,%3,%%g1\n" \
1257 " mulscc %%g1,%3,%%g1\n" \
1258 " mulscc %%g1,%3,%%g1\n" \
1259 " mulscc %%g1,%3,%%g1\n" \
1260 " mulscc %%g1,%3,%%g1\n" \
1261 " mulscc %%g1,%3,%%g1\n" \
1262 " mulscc %%g1,0,%%g1\n" \
1263 " add %%g1,%%o5,%0\n" \
1264 " rd %%y,%1" \
1265 : "=r" ((USItype) (w1)), \
1266 "=r" ((USItype) (w0)) \
1267 : "%rI" ((USItype) (u)), \
1268 "r" ((USItype) (v)) \
1269 : "g1", "o5" __AND_CLOBBER_CC)
1270 #define UMUL_TIME 39 /* 39 instructions */
1271 /* It's quite necessary to add this much assembler for the sparc.
1272 The default udiv_qrnnd (in C) is more than 10 times slower! */
1273 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1274 __asm__ ("! Inlined udiv_qrnnd\n" \
1275 " mov 32,%%g1\n" \
1276 " subcc %1,%2,%%g0\n" \
1277 "1: bcs 5f\n" \
1278 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1279 " sub %1,%2,%1 ! this kills msb of n\n" \
1280 " addx %1,%1,%1 ! so this can't give carry\n" \
1281 " subcc %%g1,1,%%g1\n" \
1282 "2: bne 1b\n" \
1283 " subcc %1,%2,%%g0\n" \
1284 " bcs 3f\n" \
1285 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1286 " b 3f\n" \
1287 " sub %1,%2,%1 ! this kills msb of n\n" \
1288 "4: sub %1,%2,%1\n" \
1289 "5: addxcc %1,%1,%1\n" \
1290 " bcc 2b\n" \
1291 " subcc %%g1,1,%%g1\n" \
1292 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1293 " bne 4b\n" \
1294 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1295 " sub %1,%2,%1\n" \
1296 "3: xnor %0,0,%0\n" \
1297 " ! End of inline udiv_qrnnd" \
1298 : "=&r" ((USItype) (__q)), \
1299 "=&r" ((USItype) (__r)) \
1300 : "r" ((USItype) (__d)), \
1301 "1" ((USItype) (__n1)), \
1302 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1303 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1304 #endif /* __sparclite__ */
1305 #endif /* __sparc_v8__ */
1306 #endif /* __sparc_v9__ */
1307 #endif /* sparc32 */
1308
1309 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1310 && W_TYPE_SIZE == 64
1311 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1312 do { \
1313 UDItype __carry = 0; \
1314 __asm__ ("addcc\t%r5,%6,%1\n\t" \
1315 "add\t%r3,%4,%0\n\t" \
1316 "movcs\t%%xcc, 1, %2\n\t" \
1317 "add\t%0, %2, %0" \
1318 : "=r" ((UDItype)(sh)), \
1319 "=&r" ((UDItype)(sl)), \
1320 "+r" (__carry) \
1321 : "%rJ" ((UDItype)(ah)), \
1322 "rI" ((UDItype)(bh)), \
1323 "%rJ" ((UDItype)(al)), \
1324 "rI" ((UDItype)(bl)) \
1325 __CLOBBER_CC); \
1326 } while (0)
1327
1328 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1329 do { \
1330 UDItype __carry = 0; \
1331 __asm__ ("subcc\t%r5,%6,%1\n\t" \
1332 "sub\t%r3,%4,%0\n\t" \
1333 "movcs\t%%xcc, 1, %2\n\t" \
1334 "sub\t%0, %2, %0" \
1335 : "=r" ((UDItype)(sh)), \
1336 "=&r" ((UDItype)(sl)), \
1337 "+r" (__carry) \
1338 : "%rJ" ((UDItype)(ah)), \
1339 "rI" ((UDItype)(bh)), \
1340 "%rJ" ((UDItype)(al)), \
1341 "rI" ((UDItype)(bl)) \
1342 __CLOBBER_CC); \
1343 } while (0)
1344
1345 #define umul_ppmm(wh, wl, u, v) \
1346 do { \
1347 UDItype tmp1, tmp2, tmp3, tmp4; \
1348 __asm__ __volatile__ ( \
1349 "srl %7,0,%3\n\t" \
1350 "mulx %3,%6,%1\n\t" \
1351 "srlx %6,32,%2\n\t" \
1352 "mulx %2,%3,%4\n\t" \
1353 "sllx %4,32,%5\n\t" \
1354 "srl %6,0,%3\n\t" \
1355 "sub %1,%5,%5\n\t" \
1356 "srlx %5,32,%5\n\t" \
1357 "addcc %4,%5,%4\n\t" \
1358 "srlx %7,32,%5\n\t" \
1359 "mulx %3,%5,%3\n\t" \
1360 "mulx %2,%5,%5\n\t" \
1361 "sethi %%hi(0x80000000),%2\n\t" \
1362 "addcc %4,%3,%4\n\t" \
1363 "srlx %4,32,%4\n\t" \
1364 "add %2,%2,%2\n\t" \
1365 "movcc %%xcc,%%g0,%2\n\t" \
1366 "addcc %5,%4,%5\n\t" \
1367 "sllx %3,32,%3\n\t" \
1368 "add %1,%3,%1\n\t" \
1369 "add %5,%2,%0" \
1370 : "=r" ((UDItype)(wh)), \
1371 "=&r" ((UDItype)(wl)), \
1372 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1373 : "r" ((UDItype)(u)), \
1374 "r" ((UDItype)(v)) \
1375 __CLOBBER_CC); \
1376 } while (0)
1377 #define UMUL_TIME 96
1378 #define UDIV_TIME 230
1379 #endif /* sparc64 */
1380
1381 #if defined (__vax__) && W_TYPE_SIZE == 32
1382 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1383 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1384 : "=g" ((USItype) (sh)), \
1385 "=&g" ((USItype) (sl)) \
1386 : "%0" ((USItype) (ah)), \
1387 "g" ((USItype) (bh)), \
1388 "%1" ((USItype) (al)), \
1389 "g" ((USItype) (bl)))
1390 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1391 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1392 : "=g" ((USItype) (sh)), \
1393 "=&g" ((USItype) (sl)) \
1394 : "0" ((USItype) (ah)), \
1395 "g" ((USItype) (bh)), \
1396 "1" ((USItype) (al)), \
1397 "g" ((USItype) (bl)))
1398 #define umul_ppmm(xh, xl, m0, m1) \
1399 do { \
1400 union { \
1401 UDItype __ll; \
1402 struct {USItype __l, __h;} __i; \
1403 } __xx; \
1404 USItype __m0 = (m0), __m1 = (m1); \
1405 __asm__ ("emul %1,%2,$0,%0" \
1406 : "=r" (__xx.__ll) \
1407 : "g" (__m0), \
1408 "g" (__m1)); \
1409 (xh) = __xx.__i.__h; \
1410 (xl) = __xx.__i.__l; \
1411 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1412 + (((SItype) __m1 >> 31) & __m0)); \
1413 } while (0)
1414 #define sdiv_qrnnd(q, r, n1, n0, d) \
1415 do { \
1416 union {DItype __ll; \
1417 struct {SItype __l, __h;} __i; \
1418 } __xx; \
1419 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1420 __asm__ ("ediv %3,%2,%0,%1" \
1421 : "=g" (q), "=g" (r) \
1422 : "g" (__xx.__ll), "g" (d)); \
1423 } while (0)
1424 #endif /* __vax__ */
1425
1426 #ifdef _TMS320C6X
1427 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1428 do \
1429 { \
1430 UDItype __ll; \
1431 __asm__ ("addu .l1 %1, %2, %0" \
1432 : "=a" (__ll) : "a" (al), "a" (bl)); \
1433 (sl) = (USItype)__ll; \
1434 (sh) = ((USItype)(__ll >> 32)) + (ah) + (bh); \
1435 } \
1436 while (0)
1437
1438 #ifdef _TMS320C6400_PLUS
1439 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
1440 #define umul_ppmm(w1, w0, u, v) \
1441 do { \
1442 UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
1443 (w1) = (USItype) (__x >> 32); \
1444 (w0) = (USItype) (__x); \
1445 } while (0)
1446 #endif /* _TMS320C6400_PLUS */
1447
1448 #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
1449 #ifdef _TMS320C6400
1450 #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
1451 #endif
1452 #define UMUL_TIME 4
1453 #define UDIV_TIME 40
1454 #endif /* _TMS320C6X */
1455
1456 #if defined (__xtensa__) && W_TYPE_SIZE == 32
1457 /* This code is not Xtensa-configuration-specific, so rely on the compiler
1458 to expand builtin functions depending on what configuration features
1459 are available. This avoids library calls when the operation can be
1460 performed in-line. */
1461 #define umul_ppmm(w1, w0, u, v) \
1462 do { \
1463 DWunion __w; \
1464 __w.ll = __builtin_umulsidi3 (u, v); \
1465 w1 = __w.s.high; \
1466 w0 = __w.s.low; \
1467 } while (0)
1468 #define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
1469 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
1470 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
1471 #endif /* __xtensa__ */
1472
1473 #if defined xstormy16
1474 extern UHItype __stormy16_count_leading_zeros (UHItype);
1475 #define count_leading_zeros(count, x) \
1476 do \
1477 { \
1478 UHItype size; \
1479 \
1480 /* We assume that W_TYPE_SIZE is a multiple of 16... */ \
1481 for ((count) = 0, size = W_TYPE_SIZE; size; size -= 16) \
1482 { \
1483 UHItype c; \
1484 \
1485 c = __clzhi2 ((x) >> (size - 16)); \
1486 (count) += c; \
1487 if (c != 16) \
1488 break; \
1489 } \
1490 } \
1491 while (0)
1492 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1493 #endif
1494
1495 #if defined (__z8000__) && W_TYPE_SIZE == 16
1496 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1497 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1498 : "=r" ((unsigned int)(sh)), \
1499 "=&r" ((unsigned int)(sl)) \
1500 : "%0" ((unsigned int)(ah)), \
1501 "r" ((unsigned int)(bh)), \
1502 "%1" ((unsigned int)(al)), \
1503 "rQR" ((unsigned int)(bl)))
1504 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1505 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1506 : "=r" ((unsigned int)(sh)), \
1507 "=&r" ((unsigned int)(sl)) \
1508 : "0" ((unsigned int)(ah)), \
1509 "r" ((unsigned int)(bh)), \
1510 "1" ((unsigned int)(al)), \
1511 "rQR" ((unsigned int)(bl)))
1512 #define umul_ppmm(xh, xl, m0, m1) \
1513 do { \
1514 union {long int __ll; \
1515 struct {unsigned int __h, __l;} __i; \
1516 } __xx; \
1517 unsigned int __m0 = (m0), __m1 = (m1); \
1518 __asm__ ("mult %S0,%H3" \
1519 : "=r" (__xx.__i.__h), \
1520 "=r" (__xx.__i.__l) \
1521 : "%1" (__m0), \
1522 "rQR" (__m1)); \
1523 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1524 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1525 + (((signed int) __m1 >> 15) & __m0)); \
1526 } while (0)
1527 #endif /* __z8000__ */
1528
1529 #endif /* __GNUC__ */
1530
1531 /* If this machine has no inline assembler, use C macros. */
1532
1533 #if !defined (add_ssaaaa)
1534 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1535 do { \
1536 UWtype __x; \
1537 __x = (al) + (bl); \
1538 (sh) = (ah) + (bh) + (__x < (al)); \
1539 (sl) = __x; \
1540 } while (0)
1541 #endif
1542
1543 #if !defined (sub_ddmmss)
1544 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1545 do { \
1546 UWtype __x; \
1547 __x = (al) - (bl); \
1548 (sh) = (ah) - (bh) - (__x > (al)); \
1549 (sl) = __x; \
1550 } while (0)
1551 #endif
1552
1553 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1554 smul_ppmm. */
1555 #if !defined (umul_ppmm) && defined (smul_ppmm)
1556 #define umul_ppmm(w1, w0, u, v) \
1557 do { \
1558 UWtype __w1; \
1559 UWtype __xm0 = (u), __xm1 = (v); \
1560 smul_ppmm (__w1, w0, __xm0, __xm1); \
1561 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1562 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1563 } while (0)
1564 #endif
1565
1566 /* If we still don't have umul_ppmm, define it using plain C. */
1567 #if !defined (umul_ppmm)
1568 #define umul_ppmm(w1, w0, u, v) \
1569 do { \
1570 UWtype __x0, __x1, __x2, __x3; \
1571 UHWtype __ul, __vl, __uh, __vh; \
1572 \
1573 __ul = __ll_lowpart (u); \
1574 __uh = __ll_highpart (u); \
1575 __vl = __ll_lowpart (v); \
1576 __vh = __ll_highpart (v); \
1577 \
1578 __x0 = (UWtype) __ul * __vl; \
1579 __x1 = (UWtype) __ul * __vh; \
1580 __x2 = (UWtype) __uh * __vl; \
1581 __x3 = (UWtype) __uh * __vh; \
1582 \
1583 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1584 __x1 += __x2; /* but this indeed can */ \
1585 if (__x1 < __x2) /* did we get it? */ \
1586 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1587 \
1588 (w1) = __x3 + __ll_highpart (__x1); \
1589 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1590 } while (0)
1591 #endif
1592
1593 #if !defined (__umulsidi3)
1594 #define __umulsidi3(u, v) \
1595 ({DWunion __w; \
1596 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1597 __w.ll; })
1598 #endif
1599
1600 /* Define this unconditionally, so it can be used for debugging. */
1601 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1602 do { \
1603 UWtype __d1, __d0, __q1, __q0; \
1604 UWtype __r1, __r0, __m; \
1605 __d1 = __ll_highpart (d); \
1606 __d0 = __ll_lowpart (d); \
1607 \
1608 __r1 = (n1) % __d1; \
1609 __q1 = (n1) / __d1; \
1610 __m = (UWtype) __q1 * __d0; \
1611 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1612 if (__r1 < __m) \
1613 { \
1614 __q1--, __r1 += (d); \
1615 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1616 if (__r1 < __m) \
1617 __q1--, __r1 += (d); \
1618 } \
1619 __r1 -= __m; \
1620 \
1621 __r0 = __r1 % __d1; \
1622 __q0 = __r1 / __d1; \
1623 __m = (UWtype) __q0 * __d0; \
1624 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1625 if (__r0 < __m) \
1626 { \
1627 __q0--, __r0 += (d); \
1628 if (__r0 >= (d)) \
1629 if (__r0 < __m) \
1630 __q0--, __r0 += (d); \
1631 } \
1632 __r0 -= __m; \
1633 \
1634 (q) = (UWtype) __q1 * __ll_B | __q0; \
1635 (r) = __r0; \
1636 } while (0)
1637
1638 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1639 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1640 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1641 #define udiv_qrnnd(q, r, nh, nl, d) \
1642 do { \
1643 USItype __r; \
1644 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1645 (r) = __r; \
1646 } while (0)
1647 #endif
1648
1649 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1650 #if !defined (udiv_qrnnd)
1651 #define UDIV_NEEDS_NORMALIZATION 1
1652 #define udiv_qrnnd __udiv_qrnnd_c
1653 #endif
1654
1655 #if !defined (count_leading_zeros)
1656 #define count_leading_zeros(count, x) \
1657 do { \
1658 UWtype __xr = (x); \
1659 UWtype __a; \
1660 \
1661 if (W_TYPE_SIZE <= 32) \
1662 { \
1663 __a = __xr < ((UWtype)1<<2*__BITS4) \
1664 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1665 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1666 } \
1667 else \
1668 { \
1669 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1670 if (((__xr >> __a) & 0xff) != 0) \
1671 break; \
1672 } \
1673 \
1674 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1675 } while (0)
1676 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1677 #endif
1678
1679 #if !defined (count_trailing_zeros)
1680 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1681 defined in asm, but if it is not, the C version above is good enough. */
1682 #define count_trailing_zeros(count, x) \
1683 do { \
1684 UWtype __ctz_x = (x); \
1685 UWtype __ctz_c; \
1686 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1687 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1688 } while (0)
1689 #endif
1690
1691 #ifndef UDIV_NEEDS_NORMALIZATION
1692 #define UDIV_NEEDS_NORMALIZATION 0
1693 #endif
sources.redhat.com git mirror of glibc CVS