Install gcc-4.3.3-tdm-1-g++.tar.gz
[git/jnareb-git.git] / mingw / lib / gcc / mingw32 / 4.3.3 / include / cpuid.h
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1 /*
2 * Copyright (C) 2007, 2008 Free Software Foundation, Inc.
4 * This file is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2, or (at your option) any
7 * later version.
8 *
9 * In addition to the permissions in the GNU General Public License, the
10 * Free Software Foundation gives you unlimited permission to link the
11 * compiled version of this file with other programs, and to distribute
12 * those programs without any restriction coming from the use of this
13 * file. (The General Public License restrictions do apply in other
14 * respects; for example, they cover modification of the file, and
15 * distribution when not linked into another program.)
17 * This file is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 51 Franklin Street, Fifth Floor,
25 * Boston, MA 02110-1301, USA.
27 * As a special exception, if you link this library with files
28 * compiled with GCC to produce an executable, this does not cause
29 * the resulting executable to be covered by the GNU General Public License.
30 * This exception does not however invalidate any other reasons why
31 * the executable file might be covered by the GNU General Public License.
34 /* %ecx */
35 #define bit_SSE3 (1 << 0)
36 #define bit_SSSE3 (1 << 9)
37 #define bit_CMPXCHG16B (1 << 13)
38 #define bit_SSE4_1 (1 << 19)
39 #define bit_SSE4_2 (1 << 20)
40 #define bit_POPCNT (1 << 23)
42 /* %edx */
43 #define bit_CMPXCHG8B (1 << 8)
44 #define bit_CMOV (1 << 15)
45 #define bit_MMX (1 << 23)
46 #define bit_FXSAVE (1 << 24)
47 #define bit_SSE (1 << 25)
48 #define bit_SSE2 (1 << 26)
50 /* Extended Features */
51 /* %ecx */
52 #define bit_LAHF_LM (1 << 0)
53 #define bit_SSE4a (1 << 6)
54 #define bit_SSE5 (1 << 11)
56 /* %edx */
57 #define bit_LM (1 << 29)
58 #define bit_3DNOWP (1 << 30)
59 #define bit_3DNOW (1 << 31)
62 #if defined(__i386__) && defined(__PIC__)
63 /* %ebx may be the PIC register. */
64 #if __GNUC__ >= 3
65 #define __cpuid(level, a, b, c, d) \
66 __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \
67 "cpuid\n\t" \
68 "xchg{l}\t{%%}ebx, %1\n\t" \
69 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
70 : "0" (level))
71 #else
72 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
73 nor alternatives in i386 code. */
74 #define __cpuid(level, a, b, c, d) \
75 __asm__ ("xchgl\t%%ebx, %1\n\t" \
76 "cpuid\n\t" \
77 "xchgl\t%%ebx, %1\n\t" \
78 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
79 : "0" (level))
80 #endif
81 #else
82 #define __cpuid(level, a, b, c, d) \
83 __asm__ ("cpuid\n\t" \
84 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
85 : "0" (level))
86 #endif
88 /* Return highest supported input value for cpuid instruction. ext can
89 be either 0x0 or 0x8000000 to return highest supported value for
90 basic or extended cpuid information. Function returns 0 if cpuid
91 is not supported or whatever cpuid returns in eax register. If sig
92 pointer is non-null, then first four bytes of the signature
93 (as found in ebx register) are returned in location pointed by sig. */
95 static __inline unsigned int
96 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
98 unsigned int __eax, __ebx, __ecx, __edx;
100 #ifndef __x86_64__
101 #if __GNUC__ >= 3
102 /* See if we can use cpuid. On AMD64 we always can. */
103 __asm__ ("pushf{l|d}\n\t"
104 "pushf{l|d}\n\t"
105 "pop{l}\t%0\n\t"
106 "mov{l}\t{%0, %1|%1, %0}\n\t"
107 "xor{l}\t{%2, %0|%0, %2}\n\t"
108 "push{l}\t%0\n\t"
109 "popf{l|d}\n\t"
110 "pushf{l|d}\n\t"
111 "pop{l}\t%0\n\t"
112 "popf{l|d}\n\t"
113 : "=&r" (__eax), "=&r" (__ebx)
114 : "i" (0x00200000));
115 #else
116 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
117 nor alternatives in i386 code. */
118 __asm__ ("pushfl\n\t"
119 "pushfl\n\t"
120 "popl\t%0\n\t"
121 "movl\t%0, %1\n\t"
122 "xorl\t%2, %0\n\t"
123 "pushl\t%0\n\t"
124 "popfl\n\t"
125 "pushfl\n\t"
126 "popl\t%0\n\t"
127 "popfl\n\t"
128 : "=&r" (__eax), "=&r" (__ebx)
129 : "i" (0x00200000));
130 #endif
132 if (!((__eax ^ __ebx) & 0x00200000))
133 return 0;
134 #endif
136 /* Host supports cpuid. Return highest supported cpuid input value. */
137 __cpuid (__ext, __eax, __ebx, __ecx, __edx);
139 if (__sig)
140 *__sig = __ebx;
142 return __eax;
145 /* Return cpuid data for requested cpuid level, as found in returned
146 eax, ebx, ecx and edx registers. The function checks if cpuid is
147 supported and returns 1 for valid cpuid information or 0 for
148 unsupported cpuid level. All pointers are required to be non-null. */
150 static __inline int
151 __get_cpuid (unsigned int __level,
152 unsigned int *__eax, unsigned int *__ebx,
153 unsigned int *__ecx, unsigned int *__edx)
155 unsigned int __ext = __level & 0x80000000;
157 if (__get_cpuid_max (__ext, 0) < __level)
158 return 0;
160 __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
161 return 1;