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  28 <h1><a name="vhdl_netlister_readme" id="vhdl_netlister_readme">VHDL netlister README</a></h1>
  29 <div class="level1">
  30 <pre class="code">The VHDL backend
  31
  32 Written by Magnus Danielson and improved by Thomas Heidel
  33
  34
  35 A few things you have to care about:
  36
  37 1. In order to generate valid component declarations, you
  38    have to add an additional attribute to each pin.
  39    &quot;type=IN&quot; or &quot;type=OUT&quot; or &quot;type=INOUT&quot;
  40
  41 2. The &quot;device&quot; attribute must be unique to a symbol!
  42    The verilog symbols of the same type for example, have all
  43    the same device attribute and will therefore not work.
  44
  45 3. Make sure your component-library picks up the vhdl symbols instead
  46    of the verilog symbols  Library paths that show up last are searched
  47    first!
  48 </pre>
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