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  28 <h1><a name="executable_instruction_opcodes" id="executable_instruction_opcodes">Executable Instruction Opcodes</a></h1>
  29 <div class="level1">
  30 <pre class="code">/*
  31  * Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
  32  *
  33  *  $Id: opcodes.txt,v 1.69 2005/11/26 17:16:05 steve Exp $
  34  */
  35
  36
  37
  38 EXECUTABLE INSTRUCTION OPCODES
  39
  40 Instruction opcodes all start with a % character and have 0 or more
  41 operands. In no case are there more then 3 operands. This chapter
  42 describes the specific behavior of each opcode, in enough detail
  43 (I hope) that its complete effect can be predicted.
  44
  45 General principles of Arithmetic:
  46
  47 The binary arithmetic instruction in general take three parameters,
  48 the left operand, the right operand, and the base. The left operand is
  49 replaced with the result, which is the same width as the left and
  50 right operands.
  51
  52
  53 * %add &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  54
  55 This instruction adds the right vector into the left vector, the
  56 vectors having the width &lt;wid&gt;. If any of the bits of either vector
  57 are x or z, the result is x. Otherwise, the result is the arithmetic
  58 sum.
  59
  60 See also the %sub instruction.
  61
  62
  63 * %add/wr &lt;bit-l&gt;, &lt;bit-r&gt;
  64
  65 This is the real valued version of the %add instruction. The arguments
  66 are word indices of the operands. The right operand is added into the
  67 left operand.
  68
  69 See also the %sub/wr instruction.
  70
  71
  72 * %addi &lt;bit-l&gt;, &lt;imm&gt;, &lt;wid&gt;
  73
  74 This instruction adds the immediate value (no x or z bits) into the
  75 left vector. The imm value is limited to 16 significant bits, but it
  76 is zero extended to match any width.
  77
  78 * %and &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  79
  80 Perform the bitwise AND of the two vectors, and store the result in
  81 the left vector. Each bit is calculated independent of other bits. AND
  82 means the following:
  83
  84         0 and ? --&gt; 0
  85         ? and 0 --&gt; 0
  86         1 and 1 --&gt; 1
  87         otherwise   x
  88
  89 * %assign/m &lt;memory-label&gt;, &lt;delay&gt;, &lt;bit&gt; (OBSOLETE)
  90
  91 This instruction does a non-blocking assignment to a bit in a memory
  92 from the specified thread register &lt;bit&gt;.  The memory bit is addressed
  93 by index register 3.  Bit address zero is the LSB of the first memory
  94 word.
  95
  96 * %assign/mv &lt;memory-label&gt;, &lt;delay&gt;, &lt;bit&gt;
  97
  98 the %assign/mv instruction assigns a vector value to a word in the
  99 labeled memory. The &lt;delay&gt; is the delay in simulation time to the
 100 assignment (0 for non-blocking assignment) and the &lt;bit&gt; is the base
 101 of the vector to write.
 102
 103 The width of the word is retrieved from index register 0.
 104
 105 The address of the word in the memory is from index register 3. The
 106 address is canonical form.
 107
 108 * %assign/v0 &lt;var-label&gt;, &lt;delay&gt;, &lt;bit&gt;
 109 * %assign/v0/d &lt;var-label&gt;, &lt;delayx&gt;, &lt;bit&gt;
 110
 111 The %assign/v0 instruction is a vector version of non-blocking
 112 assignment. The &lt;delay&gt; is the number of clock ticks in the future
 113 where the assignment should be schedule, and the &lt;bit&gt; is the base of
 114 the vector to be assigned to the destination. The vector width is in
 115 index register 0.
 116
 117 The %assign/v0/d variation puts the delay instead into an integer
 118 register that is given by the &lt;delayx&gt; value. This should not be 0, of
 119 course, because integer 0 is taken with the vector width.
 120
 121 The &lt;var-label&gt; references a .var object that can receive non-blocking
 122 assignments. For blocking assignments, see %set/v.
 123
 124 * %assign/v0x1 &lt;var-label&gt;, &lt;delay&gt;, &lt;bit&gt;
 125
 126 This is similar to the %assign/v0 instruction, but adds the index-1
 127 index register with the canonical index of the destination where the
 128 vector is to be written. This allows for part writes into the vector.
 129
 130 * %assign/wr &lt;vpi-label&gt;, &lt;delay&gt;, &lt;index&gt;
 131
 132 This instruction causes a non-blocking assign of the indexed value to
 133 the real object addressed by the &lt;vpi-label&gt; label.
 134
 135 * %assign/x0 &lt;var-label&gt;, &lt;delay&gt;, &lt;bit&gt; (OBSOLETE -- See %assign/v0x)
 136
 137 This does a non-blocking assignment to a functor, similar to the
 138 %assign instruction. The &lt;var-label&gt; identifies the base functor of
 139 the affected variable, and the &lt;delay&gt; gives the delay when the
 140 assignment takes place. The delay may be 0. The actual functor used is
 141 calculated by using &lt;var-label&gt; as a base, and indexing with the
 142 index[0] index register. This supports indexed assignment.
 143
 144 The &lt;bit&gt; is the address of the thread register that contains the bit
 145 value to assign.
 146
 147
 148 * %blend &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 149
 150 This instruction blends the bits of a vector into the destination in a
 151 manner like the expression (x ? &lt;a&gt; : &lt;b&gt;). The truth table is:
 152
 153         1  1 --&gt; 1
 154         0  0 --&gt; 0
 155         z  z --&gt; z
 156         x  x --&gt; x
 157         .... --&gt; x
 158
 159 In other words, if the bits are identical, then take that
 160 value. Otherwise, the value is x.
 161
 162 * %breakpoint
 163
 164 This instruction unconditionally breaks the simulator into the
 165 interactive debugger. The idea is to stop the simulator here and give
 166 the user a chance to display the state of the simulation using
 167 debugger commands.
 168
 169 This may not work on all platforms. If run-time debugging is compiled
 170 out, then this function is a no-op.
 171
 172 * %cassign/v &lt;var-label&gt;, &lt;bit&gt;, &lt;wid&gt;
 173
 174 Perform a continuous assign of a constant value to the target
 175 variable. This is similar to %set, but it uses the cassign port
 176 (port-1) of the signal functor instead of the normal assign, so the
 177 signal responds differently. See &quot;VARIABLE STATEMENTS&quot; in the
 178 README.txt file.
 179
 180
 181 * %cmp/u &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 182 * %cmp/s &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 183
 184 These instructions perform a generic comparison of two vectors of equal
 185 size. The &lt;bit-l&gt; and &lt;bit-r&gt; numbers address the least-significant
 186 bit of each vector, and &lt;wid&gt; is the width. If either operand is 0,
 187 1, 2 or 3 then it is taken to be a constant replicated to the selected
 188 width.
 189
 190 The results of the comparison go into bits 4, 5, 6 and 7:
 191
 192         4: eq  (equal)
 193         5: lt  (less than)
 194         6: eeq (case equal)
 195
 196 The eeq bit is set to 1 if all the bits in the vectors are exactly the
 197 same, or 0 otherwise. The eq bit is true if the values are logically
 198 the same. That is, x and z are considered equal. In other words the eq
 199 bit is the same as ``==&#039;&#039; and the eeq bit ``===&#039;&#039;.
 200
 201 The lt bit is 1 if the left vector is less then the right vector, or 0
 202 if greater then or equal to the right vector. It is the equivalent of
 203 the Verilog &lt; operator. Combinations of these three bits can be used
 204 to implement all the Verilog comparison operators.
 205
 206 The %cmp/u and %cmp/s differ only in the handling of the lt bit. The
 207 %cmp/u does an unsigned compare, whereas the %cmp/s does a signed
 208 compare. In either case, if either operand contains x or z, then lt
 209 bit gets the x value.
 210
 211
 212 * %cmp/wr &lt;bit-l&gt;, &lt;bit-r&gt;
 213
 214 [compare real values.]
 215
 216 * %cmp/ws &lt;bit-l&gt;, &lt;bit-r&gt;
 217 * %cmp/wu &lt;bit-l&gt;, &lt;bit-r&gt;
 218
 219 [compare signed/unsigned integer words.]
 220
 221 * %cmp/z &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 222 * %cmp/x &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 223
 224 These instructions are for implementing the casez and casex
 225 comparisons. These work similar to the %cmp/u instructions, except
 226 only an eq bit is calculated. These comparisons both treat z values in
 227 the left or right operand as don&#039;t care positions. The %cmp/x
 228 instruction will also treat x values in either operand as don&#039;t care.
 229
 230 Only bit 4 is set by these instructions.
 231
 232
 233 * %cvt/ir &lt;bit-l&gt;, &lt;bit-r&gt;
 234 * %cvt/ri &lt;bit-l&gt;, &lt;bit-r&gt;
 235 * %cvt/vr &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 236
 237 Copy a word from r to l, converting it from real to integer (ir) or
 238 integer to real (ri) in the process. The source and destination may
 239 be the same word address, leading to a convert in place.
 240
 241 The %cvt/vr opcode converts a real word &lt;bit-r&gt; to a thread vector
 242 starting at &lt;bit-l&gt; and with the width &lt;wid&gt;. Non-integer precision is
 243 lost in the conversion.
 244
 245 * %deassign &lt;var-label&gt;
 246
 247 Deactivate and disconnect a procedural continuous assignment to a
 248 variable. The &lt;var-label&gt; identifies the affected variable.
 249
 250 * %delay &lt;delay&gt;
 251
 252 This opcode pauses the thread, and causes it to be rescheduled for a
 253 time in the future. The &lt;amount&gt; is the number of the ticks in the
 254 future to reschedule, and is &gt;= 0. If the %delay is zero, then the
 255 thread yields the processor for another thread, but will be resumed in
 256 the current time step.
 257
 258 * %delayx &lt;idx&gt;
 259
 260 This is similar to the %delay opcode, except that the parameter
 261 selects an index register, which contains the actual delay. This
 262 supports run-time calculated delays.
 263
 264 * %disable &lt;scope-label&gt;
 265
 266 This instruction terminates threads that are part of a specific
 267 scope. The label identifies the scope in question, and the threads are
 268 the threads that are currently within that scope.
 269
 270
 271 * %div &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 272 * %div/s &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 273
 274 This instruction arithmetically divides the &lt;bit-l&gt; vector by the
 275 &lt;bit-r&gt; vector, and leaves the result in the &lt;bit-l&gt; vector. IF any of
 276 the bits in either vector are x or z, the entire result is x.
 277
 278 The %div/s instruction is the same as %div, but does signed division.
 279
 280
 281 * %div/wr &lt;bit-l&gt;, &lt;bit-r&gt;
 282
 283 This opcode divides the left operand by the right operand. If the
 284 right operand is 0, then the result is NaN.
 285
 286
 287 * %force/v &lt;label&gt;, &lt;bit&gt;, &lt;wid&gt;
 288
 289 Force a constant value to the target variable. This is similar to %set
 290 and %cassign/v, but it uses the force port (port-2) of the signal
 291 functor instead of the normal assign port (port-0), so the signal
 292 responds differently. See &quot;VARIABLE STATEMENTS&quot; and &quot;NET STATEMENTS&quot;
 293 in the README.txt file.
 294
 295 * %force/x0 &lt;label&gt;, &lt;bit&gt;, &lt;wid&gt;
 296
 297 Force a constant value to part target variable. This is similar to
 298 %set/x instruction, but it uses the force port (port-2) of the signal
 299 functor instead of the normal assign port (port-0), so the signal
 300 responds differently. See &quot;VARIABLE STATEMENTS&quot; and &quot;NET STATEMENTS&quot;
 301 in the README.txt file.
 302
 303 * %fork &lt;code-label&gt;, &lt;scope-label&gt;
 304
 305 This instruction is similar to %jmp, except that it creates a new
 306 thread to start executing at the specified address. The new thread is
 307 created and pushed onto the child stack.  It is also marked runnable,
 308 but is not necessarily started until the current thread yields.
 309
 310 The %fork instruction has no effect other then to push a child thread.
 311
 312 See also %join.
 313
 314
 315 * %inv &lt;bit&gt;, &lt;wid&gt;
 316
 317 Perform a bitwise invert of the vector starting at &lt;bit&gt;. The result
 318 replaces the input. Invert means the following, independently for each
 319 bit:
 320
 321         0  --&gt; 1
 322         1  --&gt; 0
 323         x  --&gt; x
 324         z  --&gt; x
 325
 326
 327 * %ix/get &lt;idx&gt;, &lt;bit&gt;, &lt;wid&gt;
 328
 329 This instruction loads a thread vector starting at &lt;bit&gt;, size &lt;wid&gt;,
 330 into the index register &lt;idx&gt;. The &lt;bit&gt; is the lsb of the value in
 331 thread bit space, and &lt;wid&gt; is the width of the vector.
 332
 333 The function converts the 4-value bits into a binary number, without
 334 sign extension. If any of the bits of the vector is x or z, then the
 335 index register gets the value 0.
 336
 337 The function also writes into bit 4 a 1 if any of the bits of the
 338 input vector are x or z. This is a flag that the 0 value written into
 339 the index register is really the result of calculating from unknown
 340 bits.
 341
 342         4: unknown value
 343         5: (reserved)
 344         6: (reserved)
 345
 346
 347 * %ix/load &lt;idx&gt;, &lt;value&gt;
 348
 349 This instruction loads an immediate value into the addressed index
 350 register. The index register holds numeric values, so the &lt;value&gt; is a
 351 number. The idx value selects the index register, and may be 0, 1, 2
 352 or 3. This is different from %ix/get, which loads the index register
 353 from a value in the thread bit vector.
 354
 355
 356 * %ix/add &lt;idx&gt;, &lt;value&gt;
 357 * %ix/sub &lt;idx&gt;, &lt;value&gt;
 358 * %ix/mul &lt;idx&gt;, &lt;value&gt;
 359
 360 This instruction adds, subtracts, or multiplies an immediate value to
 361 the addressed index register. The index register holds numeric values,
 362 so the &lt;value&gt; is a number. The &lt;idx&gt; value selects the index register,
 363 and may be 0, 1, 2 or 3.
 364
 365
 366 * %jmp &lt;code-label&gt;
 367
 368 The %jmp instruction performs an unconditional branch to a given
 369 location. The parameter is the label of the destination instruction.
 370
 371 * %jmp/[01xz] &lt;code-label&gt;, &lt;bit&gt;
 372
 373 This is a conditional version of the %jmp instruction. In this case,
 374 a single bit (addressed by &lt;bit&gt;) is tested. If it is one of the
 375 values in the part after the /, the jump is taken. For example:
 376
 377         %jmp/xz T_label, 8;
 378
 379 will jump to T_label if bit 8 is x or z.
 380
 381 * %join
 382
 383 This is the partner to %fork. This instruction causes the thread to
 384 wait for the top thread in the child stack to terminate, then
 385 continues. It has no effect in the current thread other then to wait
 386 until the top child is cleared.
 387
 388 It is an error to execute %join if there are no children in the child
 389 stack. Every %join in the thread must have a matching %fork that
 390 spawned off a child thread.
 391
 392 If the matching child instruction is still running, a %join suspends
 393 the calling thread until the child ends. If the child is already
 394 ended, then the %join does not block or yield the thread.
 395
 396 * %load/m &lt;bit&gt;, &lt;memory-label&gt; (OBSOLETE)
 397
 398 This instruction loads a value from a memory bit into the specified
 399 thread register bit. The memory bit is addressed by index register 3.
 400 Bit address zero is the LSB of the first memory word.  This
 401 instruction loads only a single bit.
 402
 403 * %load/mv &lt;bit&gt;, &lt;memory-label&gt;, &lt;wid&gt;
 404
 405 this instruction loads a word from the specified memory. The word
 406 address is in index register 3. The width should match the width of
 407 the memory word.
 408
 409 * %load/nx &lt;bit&gt;, &lt;vpi-label&gt;, &lt;idx&gt;
 410
 411 This instruction load a value from a .net object bit. Since .net
 412 objects don&#039;t really exist (they are only named indirection into the
 413 netlist) this instruction indexes into the .net list of bits.
 414
 415 * %load/v &lt;bit&gt;, &lt;functor-label&gt;, &lt;wid&gt;
 416
 417 This instruction loads a vector value from the given functor node into
 418 the specified thread register bit. The functor-label can refer to a
 419 .net, a .var or a .functor with a vector output. The entire vector,
 420 from the least significant up to &lt;wid&gt; bits, is loaded starting at
 421 thread bit &lt;bit&gt;. It is an error for the width to not match the vector
 422 width at the functor.
 423
 424 * %load/wr &lt;bit&gt;, &lt;vpi-label&gt;
 425
 426 This instruction reads a real value from the vpi-like object to a word
 427 register.
 428
 429 * %load/x &lt;bit&gt;, &lt;functor-label&gt;, &lt;idx&gt;
 430 * %load/x.p &lt;bit&gt;, &lt;functor-label&gt;, &lt;idx&gt;
 431
 432 This is an indexed load. It uses the contents of the specified index
 433 register to select a bit from a vector functor at &lt;functor-label&gt;. The
 434 bit is pulled from the indexed bit of the addressed functor and loaded
 435 into the destination thread bit. If the indexed value is beyond the
 436 width of the vector, then the result is X.
 437
 438 The %load/x.p is the same, but when the operation is done, it
 439 increments the specified index register. This provides a basic
 440 auto-increment feature.
 441
 442 * %loadi/wr &lt;bit&gt;, &lt;mant&gt;, &lt;exp&gt;
 443
 444 This opcode loads an immediate value, floating point, into the word
 445 register selected by &lt;bit&gt;. The mantissa is an unsigned integer value,
 446 up to 32 bits, that multiplied by 2**(&lt;exp&gt;-0x1000) to make a real
 447 value. The sign bit is OR-ed into the &lt;exp&gt; value at bit 0x2000, and
 448 is removed from the &lt;exp&gt; before calculating the real value.
 449
 450
 451 * %mod   &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 452 * %mod/s &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 453
 454 This instruction calculates the modulus %r of the left operand, and
 455 replaces the left operand with the result. The &lt;wid&gt; gives the width
 456 of the left and the right vectors, and the left vector is completely
 457 replaced with the result.
 458
 459 The /s form does signed %.
 460
 461 * %mov &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 462
 463 This instruction copies a vector from one place in register space to
 464 another. The destination and source vectors are assumed to be the same
 465 width and non-overlapping. The &lt;dst&gt; may not be 0-3, but if the &lt;src&gt;
 466 is one of the 4 constant bits, the effect is to replicate the value
 467 into the destination vector. This is useful for filling a vector.
 468
 469
 470 * %mul &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 471
 472 This instruction multiplies the left vector by the right vector, the
 473 vectors having the width &lt;wid&gt;. If any of the bits of either vector
 474 are x or z, the result is x. Otherwise, the result is the arithmetic
 475 product.
 476
 477
 478 * %mul/wr &lt;bit-l&gt;, &lt;bit-r&gt;
 479
 480 This opcode multiplies two real words together. The result replaces
 481 the left operand.
 482
 483
 484 * %muli &lt;bit-l&gt;, &lt;imm&gt;, &lt;wid&gt;
 485
 486 This instruction is the same as %mul, but the second operand is an
 487 immediate value that is padded to the width of the result.
 488
 489
 490 * %nand &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 491
 492 Perform the bitwise NAND of the two vectors, and store the result in
 493 the left vector. Each bit is calculated independent of other bits. NAND
 494 means the following:
 495
 496         0 and ? --&gt; 1
 497         ? and 0 --&gt; 1
 498         1 and 1 --&gt; 0
 499         otherwise   x
 500
 501
 502 * %nor &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 503
 504 Perform the bitwise nor of the vectors. Each bit in the &lt;dst&gt; is
 505 combined with the corresponding bit in the source, according to the
 506 truth table:
 507
 508         1 nor ? --&gt; 0
 509         ? nor 1 --&gt; 0
 510         0 nor 0 --&gt; 1
 511         otherwise  x
 512
 513
 514 * %nor/r &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 515
 516 The %nor/r instruction is a reduction nor. That is, the &lt;src&gt; is a
 517 vector with width, but the result is a single bit. The &lt;src&gt; vector is
 518 not affected by the operation unless the &lt;dst&gt; bit is within the
 519 vector. The result is calculated before the &lt;dst&gt; bit is written, so
 520 it is valid to place the &lt;dst&gt; within the &lt;src&gt;.
 521
 522 The actual operation performed is the inverted or of all the bits in
 523 the vector.
 524
 525
 526 * %or &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 527
 528 Perform the bitwise or of the vectors. Each bit in the &lt;dst&gt; is
 529 combined with the corresponding bit in the source, according to the
 530 truth table:
 531
 532         1 or ? --&gt; 1
 533         ? or 1 --&gt; 1
 534         0 or 0 --&gt; 0
 535         otherwise  x
 536
 537
 538 * %or/r &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 539
 540 This is a reduction version of the %or opcode. The &lt;src&gt; is a vector,
 541 and the &lt;dst&gt; is a writable scalar. The &lt;dst&gt; gets the value of the
 542 or of all the bits of the src vector.
 543
 544
 545 * %release/net &lt;functor-label&gt;
 546 * %release/reg &lt;functor-label&gt;
 547
 548 Release the force on the signal that is represented by the functor
 549 &lt;functor-label&gt;.  The force was previously activated with a %force/v
 550 statement.  If no force was active on this functor the statement does
 551 nothing. The %release/net sends to the labeled functor the release
 552 command with net semantics: the unforced value is propagated to the
 553 output of the signal after the release is complete. The %release/reg
 554 sends the release command with reg semantics: the signal holds its
 555 forced value until another value propagates through.
 556
 557 * %set/v &lt;var-label&gt;, &lt;bit&gt;, &lt;wid&gt;
 558
 559 This sets a vector to a variable, and is used to implement blocking
 560 assignments. The &lt;var-label&gt; identifies the variable to receive the
 561 new value. Once the set completes, the value is immediately available
 562 to be read out of the variable. The &lt;bit&gt; is the address of the thread
 563 register that contains the LSB of the vector, and the &lt;wid&gt; is the
 564 size of the vector. The width must exactly match the width of the
 565 signal.
 566
 567 * %set/mv &lt;memory-label&gt;, &lt;bit&gt;, &lt;wid&gt;
 568
 569 This sets a thread vector to a memory word. The &lt;memory-label&gt;
 570 addresses a memory device, and the &lt;bit&gt;,&lt;wid&gt; describe a vector to be
 571 written. Index register 3 contains the address of the word within the
 572 memory. The address (in canonical form) is precalculated and loaded
 573 into index register 3.
 574
 575
 576 * %set/wr &lt;vpi-label&gt;, &lt;bit&gt;
 577
 578 This instruction writes a real word to the specified VPI-like object.
 579
 580 * %set/x0 &lt;var-label&gt;, &lt;bit&gt;, &lt;wid&gt;
 581
 582 This sets the part of a signal vector, the address calculated by
 583 using the index register 0 to index the base within the vector of
 584 &lt;var-label&gt;. The destination must be a signal of some sort. Otherwise,
 585 the instruction will fail.
 586
 587 The addressing is canonical (0-based) so the compiler must figure out
 588 non-zero offsets, if any. The width is the width of the part being
 589 written. The other bits of the vector are not touched.
 590
 591 The index may be signed, and if less then 0, the beginning bits are
 592 not assigned. Also, if the bits go beyond the end of the signal, those
 593 bits are not written anywhere.
 594
 595
 596 * %shiftl/i0 &lt;bit&gt;, &lt;wid&gt;
 597
 598 This instruction shifts the vector left (towards more significant
 599 bits) by the amount in index register 0. The &lt;bit&gt; is the address of
 600 the lsb of the vector, and &lt;wid&gt; the width of the vector. The shift is
 601 done in place. Zero values are shifted in.
 602
 603 * %shiftr/i0 &lt;bit&gt;, &lt;wid&gt;
 604 * %shiftr/s/i0 &lt;bit&gt;, &lt;wid&gt;
 605
 606 This instruction shifts the vector right (towards the less significant
 607 bits) by the amount in the index register 0. The &lt;bit&gt; is the address
 608 of the lsb of the vector, and &lt;wid&gt; is the width of the vector. The
 609 shift is done in place.
 610
 611 %shiftr/i0 is an unsigned down shift, so zeros are shifted into the
 612 top bits. %shiftr/s/i0 is a signed shift, so the value is sign-extended.
 613
 614 * %sub &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 615
 616 This instruction arithmetically subtracts the right vector out of the
 617 left vector. It accomplishes this by adding to the left vector 1 plus
 618 the 1s complement of the right vector. The carry value is dropped, and
 619 the result, placed in &lt;bit-l&gt;, is the subtraction of &lt;bit-r&gt; from the
 620 input &lt;bit-l&gt;. Both vectors have the same width. If any bits in either
 621 operand are x, then the entire result is x.
 622
 623 See also the %add instruction.
 624
 625 * %subi &lt;bit-l&gt;, &lt;imm&gt;, &lt;wid&gt;
 626
 627 This instruction arithmetically subtracts the immediate value from the
 628 left vector. The &lt;imm&gt; value is a 16bit unsigned value zero-extended to
 629 the &lt;wid&gt; of the left vector. The result replaces the left vector.
 630
 631 See also the %addi instruction.
 632
 633
 634 * %sub/wr &lt;bit-l&gt;, &lt;bit-r&gt;
 635
 636 This instruction operates on real values in word registers. The right
 637 indexed value is subtracted from the left indexed value, and the
 638 result placed in the left index.
 639
 640
 641 * %vpi_call &lt;name&gt; [, ...]
 642
 643 This instruction makes a call to a system task that was declared using
 644 VPI. The operands are compiled down to a vpiHandle for the call. The
 645 instruction contains only the vpiHandle for the call. See the vpi.txt
 646 file for more on system task/function calls.
 647
 648
 649 * %vpi_func &lt;name&gt;, &lt;dst&gt;, &lt;wid&gt; [, ...]
 650
 651 This instruction is similar to %vpi_call, except that it is for
 652 calling system functions. The difference here is the &lt;dst&gt; and &lt;wid&gt;
 653 parameters that specify where the return value is to go. The normal
 654 means that the VPI code uses to write the return value causes those
 655 bits to go here.
 656
 657
 658 * %wait &lt;functor-label&gt;
 659
 660 When a thread executes this instruction, it places itself in the
 661 sensitive list for the addressed functor. The functor holds all the
 662 threads that await the functor. When the defined sort of event occurs
 663 on the functor, a thread schedule event is created for all the threads
 664 in its list and the list is cleared.
 665
 666 * %xnor &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 667
 668 This does a bitwise exclusive nor (~^) of the &lt;src&gt; and &lt;dst&gt; vector,
 669 and leaves the result in the &lt;dst&gt; vector. xnor is this:
 670
 671         0 xnor 0 --&gt; 1
 672         0 xnor 1 --&gt; 0
 673         1 xnor 0 --&gt; 0
 674         1 xnor 1 --&gt; 1
 675         otherwise    x
 676
 677
 678 * %xor &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 679
 680 This does a bitwise exclusive or (^) of the &lt;src&gt; and &lt;dst&gt; vector,
 681 and leaves the result in the &lt;dst&gt; vector. xor is this:
 682
 683         0 xnor 0 --&gt; 0
 684         0 xnor 1 --&gt; 1
 685         1 xnor 0 --&gt; 1
 686         1 xnor 1 --&gt; 0
 687         otherwise    x
 688
 689
 690 /*
 691  * Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
 692  *
 693  *    This source code is free software; you can redistribute it
 694  *    and/or modify it in source code form under the terms of the GNU
 695  *    General Public License as published by the Free Software
 696  *    Foundation; either version 2 of the License, or (at your option)
 697  *    any later version.
 698  *
 699  *    This program is distributed in the hope that it will be useful,
 700  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 701  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 702  *    GNU General Public License for more details.
 703  *
 704  *    You should have received a copy of the GNU General Public License
 705  *    along with this program; if not, write to the Free Software
 706  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 707  */</pre>
 708
 709 </div>
 710 </div>
 711 </body>
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