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  28 <h1><a name="icarus_verilog_extensions" id="icarus_verilog_extensions">Icarus Verilog Extensions</a></h1>
  29 <div class="level1">
  30 <pre class="code">Icarus Verilog Extensions
  31
  32 Icarus Verilog supports certain extensions to the baseline IEEE1364
  33 standard. Some of these are picked from extended variants of the
  34 language, such as SystemVerilog, and some are expressions of internal
  35 behavior of Icarus Verilog, made available as a tool debugging aid.
  36
  37 * Builtin System Functions
  38
  39 ** Extended Verilog Data Types
  40
  41 This feature is turned off if the generation flag &quot;-g&quot; is set to other
  42 then the default &quot;2x&quot;.  For example, &quot;iverilog -g2x&quot; enables extended
  43 data types, and &quot;iverilog -g2&quot; disables them.
  44
  45 Icarus Verilog adds support for extended data types. This extended
  46 type syntax is based on a proposal by Cadence Design Systems,
  47 originally as an update to the IEEE1364. That original proposal has
  48 apparently been absorbed by the IEEE1800 SystemVerilog
  49 standard. Icarus Verilog currently only takes the new primitive types
  50 from the proposal.
  51
  52 Extended data types separates the concept of net/variable from the
  53 data type. Both nets and variables can declared with any data
  54 type. The primitive types available are:
  55
  56     logic  - The familiar 0, 1, x and z, optionally with strength.
  57     bool   - Limited to only 0 and 1
  58     real   - 64bit real values
  59
  60 Nets with logic type may have multiple drivers with strength, and the
  61 value is resolved the usual way. Only logic values may be driven to
  62 logic nets, so bool values driven onto logic nets are implicitly
  63 converted to logic.
  64
  65 Nets with any other type may not have multiple drivers. The compiler
  66 should detect the multiple drivers and report an error.
  67
  68 - Declarations
  69
  70 The declaration of a net is extended to include the type of the wire,
  71 with the syntax:
  72
  73     wire &lt;type&gt; &lt;wire-assignment-list&gt;... ;
  74
  75 The &lt;type&gt;, if omitted, is taken to be logic. The &quot;wire&quot; can be any of
  76 the net keywords. Wires can be logic, bool, real, or vectors of logic
  77 or bool. Some valid examples:
  78
  79     wire real foo = 1.0;
  80     tri logic bus[31:0];
  81     wire bool addr[23:0];
  82     ... and so on.
  83
  84 The declarations of variables is similar. The &quot;reg&quot; keyword is used to
  85 specify that this is a variable. Variables can have the same data
  86 types as nets.
  87
  88 - Ports
  89
  90 Module and task ports in standard verilog are restricted to logic
  91 types. This extension removes that restriction, allowing any type to
  92 pass through the port consistent with the continuous assignment
  93 connectivity that is implied by the type.
  94
  95 - Expressions
  96
  97 Expressions in the face of real values is covered by the baseline
  98 Verilog standard.
  99
 100 The bool type supports the same operators as the logic type, with the
 101 obvious differences imposed by the limited domain.
 102
 103 Comparison operators (not case compare) return logic if either of
 104 their operands is logic. If both are bool or real (including mix of
 105 bool and real) then the result is bool. This is because comparison of
 106 bools and reals always return exactly true or false.
 107
 108 Case comparison returns bool. This differs from baseline Verilog,
 109 which strictly speaking returns a logic, but only 0 or 1 values.
 110
 111 All the arithmetic operators return bool if both of their operands are
 112 bool or real. Otherwise, they return logic.</pre>
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