gnetlist/docs/README.sysc

   1 TITLE:
   2
   3      Gnetlist SystemC Backend
   4
   5 OBJECTIVE:
   6
   7      Transform a geda schematic into a transaction based structural systemc module.
   8
   9 LIMITATIONS:
  10
  11      1.- Only transaction based wires are considered (wire_name<user_type>).
  12      2.- Unnamed wires are eliminated.
  13      3.- In/out ports have to be inserted manually in the sysc code.
  14      4.- Duplicated include headers are not eliminated by the backend.
  15      5.- The maximum number of object constructor parameters is 31 (attr1->attr31).
  16
  17 LINKS:
  18
  19      GPL Electronic Design Automation (geda-gnetlist): http://www.geda.seul.org
  20      SystemC: http://www.systemc.org
  21
  22 ACK:
  23
  24      Based on gnet-verilog.scm by Mike Jarabek.
  25
  26 EXAMPLE:
  27
  28      Schematic:
  29
  30      src1                         alg1                      snk1
  31      ______________               _______________           _______________
  32      | source     |  a<user_type> |  algorithm  |  b<float> |        sink |
  33      |         OUT|__ _________ __|IN        OUT|__ _____ __|IN           |
  34      |            |               |             |           |             |
  35      | infile.data|               |             |           | outfile.data|
  36      |____________|               |_____________|           |_____________|
  37
  38
  39      Attributes:
  40
  41             Schematic:
  42                      module_name=test_sch2sysc
  43
  44             Wires:
  45                      netname=a<user_type>
  46                      netname=b<float>
  47             Symbols:
  48                      refdes=src1 attr1=infile.data
  49                      refdes=alg1
  50                      refdes=snk1 attr1=outfile.data
  51                      refdes=pina
  52                      refdes=pinb
  53
  54      SystemC:
  55
  56                 #include "systemc.h"
  57                 #include "sink.h"
  58                 #include "source.h"
  59                 #include "algorithm.h"
  60
  61                 SC_MODULE (test_sch2sysc)
  62                 {
  63                         /* Port directions begin here */
  64
  65                         /* Wires from the design */
  66                         sc_signal<float> b;
  67                         sc_signal<packet_type> a;
  68
  69                         /* Package instantiations */
  70                         sink snk1;
  71                         source src1;
  72                         algorithm alg1;
  73
  74                         SC_CTOR(test_sch2sysc):
  75                                 snk1("snk1","outfile.data"),
  76                                 src1("src1","infile.data"),
  77                                 alg1("alg1")
  78                         {
  79                                 snk1.IN(b);
  80                                 src1.OUT(a);
  81                                 alg1.IN(a);
  82                                 alg1.OUT(b);
  83                         }
  84                 };
  85