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28 <h1><a name="icarus_verilog_compiler_man-page" id="icarus_verilog_compiler_man-page">Icarus Verilog compiler man-page</a></h1>
34 NAME
35 iverilog - Icarus Verilog compiler
38 SYNOPSIS
39 iverilog [-ESVv] [-Bpath] [-ccmdfile] [-g1|-g2|-g2x] [-Dmacro[=defn]]
40 [-pflag=value] [-Iincludedir] [-mmodule] [-Mfile] [-Nfile] [-ooutput-
41 filename] [-stopmodule] [-ttype] [-Tmin/typ/max] [-Wclass] [-ypath]
42 sourcefile
45 DESCRIPTION
46 iverilog is a compiler that translates Verilog source code into exe-
47 cutable programs for simulation, or other netlist formats for further
48 processing. The currently supported targets are vvp for simulation, and
49 xnf and fpga for synthesis. Other target types are added as code gener-
50 ators are implemented.
53 OPTIONS
54 iverilog accepts the following options:
56 -Bbase The iverilog program uses external programs and configuration
57 files to preprocess and compile the Verilog source. Normally,
58 the path used to locate these tools is built into the iverilog
59 program. However, the -B switch allows the user to select a
60 different set of programs. The path given is used to locate
61 ivlpp, ivl, code generators and the VPI modules.
63 -cfile This flag specifies an input file that contains a list of Ver-
64 ilog source files. This is similar to the command file of other
65 Verilog simulators, in that it is a file that contains the file
66 names instead of taking them on the command line. See Command
67 Files below.
69 -Dmacro Defines macro macro with the string ‘1’ as its definition. This
70 form is normally only used to trigger ifdef conditionals in the
71 Verilog source.
73 -Dmacro=defn
74 Defines macro macro as defn.
76 -E Preprocess the Verilog source, but do not compile it. The out-
77 put file is the Verilog input, but with file inclusions and
78 macro references expanded and removed. This is useful, for
79 example, to preprocess Verilog source for use by other compil-
80 ers.
82 -g1|-g2|-g2x
83 Select the Verilog language generation to support in the com-
85 or Verilog with extension(2x). Normally, Icarus Verilog
86 defaults to the latest known generation of the language. This
87 flag is most useful to restrict the language to a set supported
88 by tools of specific generations, for compatibility with other
89 tools.
91 -Iincludedir
92 Append directory includedir to list of directories searched for
93 Verilog include files. The -I switch may be used many times to
94 specify several directories to search, the directories are
95 searched in the order they appear on the command line.
97 -Mpath Write into the file specified by path a list of files that con-
98 tribute to the compilation of the design. This includes files
99 that are included by include directives and files that are
100 automatically loaded by library support. The output is one file
101 name per line, with no leading or trailing space.
103 -mmodule
104 Add this module to the list of VPI modules to be loaded by the
105 simulation. Many modules can be specified, and all will be
106 loaded, in the order specified. The system module is implicit
107 and always included.
109 -Npath This is used for debugging the compiler proper. Dump the final
110 netlist form of the design to the specified file. It otherwise
111 does not affect operation of the compiler. The dump happens
112 after the design is elaborated and optimized.
114 -o filename
115 Place output in the file filename. If no output file name is
116 specified, iverilog uses the default name a.out.
118 -pflag=value
119 Assign a value to a target specific flag. The -p switch may be
120 used as often as necessary to specify all the desired flags.
121 The flags that are used depend on the target that is selected,
122 and are described in target specific documentation. Flags that
123 are not used are ignored.
125 -S Synthesize. Normally, if the target can accept behavioral
126 descriptions the compiler will leave processes in behavioral
127 form. The -S switch causes the compiler to perform synthesis
128 even if it is not necessary for the target. If the target type
129 is a netlist format, the -S switch is unnecessary and has no
130 effect.
132 -s topmodule
133 Specify the top level module to elaborate. Icarus Verilog will
134 by default choose modules that are not instantiated in any
135 other modules, but sometimes that is not sufficient, or instan-
136 tiates too many modules. If the user specifies one or more root
137 modules with -s flags, then they will be used as root modules
138 instead.
140 -Tmin|typ|max
141 Use this switch to select min, typ or max times from
142 min:typ:max expressions. Normally, the compiler will simply use
143 the typ value from these expressions (with a warning) but this
144 switch will tell the compiler explicitly which value to use.
145 This will suppress the warning that the compiler is making a
146 choice.
148 -ttarget
149 Use this switch to specify the target output format. See the
150 TARGETS section below for a list of valid output formats.
152 -v Turn on verbose messages. This will print the command lines
153 that are executed to perform the actual compilation, along with
154 version information from the various components, as well as the
155 version of the product as a whole. You will notice that the
156 command lines include a reference to a key temporary file that
157 passes information to the compiler proper. To keep that file
158 from being deleted at the end of the process, provide a file
159 name of your own in the environment variable IVERILOG_ICONFIG.
161 -V Print the version of the compiler, and exit.
163 -Wclass Turn on different classes of warnings. See the WARNING TYPES
164 section below for descriptions of the different warning groups.
165 If multiple -W switches are used, the warning set is the union
166 of all the requested classes.
168 -ylibdir
169 Append the directory to the library module search path. When
170 the compiler finds an undefined module, it looks in these
171 directories for files with the right name.
174 MODULE LIBRARIES
175 The Icarus Verilog compiler supports module libraries as directories
176 that contain Verilog source files. During elaboration, the compiler
177 notices the instantiation of undefined module types. If the user speci-
178 fies library search directories, the compiler will search the directory
179 for files with the name of the missing module type. If it finds such a
180 file, it loads it as a Verilog source file, they tries again to elabo-
181 rate the module.
183 Library module files should contain only a single module, but this is
184 not a requirement. Library modules may reference other modules in the
185 library or in the main design.
188 TARGETS
189 The Icarus Verilog compiler supports a variety of targets, for differ-
190 ent purposes, and the -t switch is used to select the desired target.
193 null The null target causes no code to be generated. It is useful
194 for checking the syntax of the Verilog source.
196 vvp This is the default. The vvp target generates code for the vvp
197 runtime. The output is a complete program that simulates the
198 design but must be run by the vvp command.
200 xnf This is the Xilinx Netlist Format used by many tools for plac-
201 ing devices in FPGAs or other programmable devices. This target
202 is obsolete, use the fpga target instead.
204 fpga This is a synthesis target that supports a variety of fpga
205 devices, mostly by EDIF format output. The Icarus Verilog fpga
206 code generator can generate complete designs or EDIF macros
207 that can in turn be imported into larger designs by other
208 tools. The fpga target implies the synthesis -S flag.
211 WARNING TYPES
212 These are the types of warnings that can be selected by the -W switch.
213 All the warning types (other then all) can also be prefixed with no- to
214 turn off that warning. This is most useful after a -Wall argument to
215 suppress isolated warning types.
218 all This enables all supported warning categories.
221 implicit
222 This enables warnings for creation of implicit declarations.
223 For example, if a scalar wire X is used but not declared in the
224 Verilog source, this will print a warning at its first use.
227 portbind
228 This enables warnings for ports of module instantiations that
229 are not connected but probably should be. Dangling input ports,
230 for example, will generate a warning.
233 timescale
234 This enables warnings for inconsistent use of the timescale
235 directive. It detects if some modules have no timescale, or if
236 modules inherit timescale from another file. Both probably mean
237 that timescales are inconsistent, and simulation timing can be
238 confusing and dependent on compilation order.
241 SYSTEM FUNCTION TABLE FILES
242 If the source file name as a .sft suffix, then it is taken to be a sys-
243 tem function table file. A System function table file is used to
244 describe to the compiler the return types for system functions. This is
245 necessary because the compiler needs this information to elaborate
246 expressions that contain these system functions, but cannot run the
247 sizetf functions since it has no run-time.
249 The format of the table is ASCII, one function per line. Empty lines
250 are ignored, and lines that start with the ’#’ character are comment
251 lines. Each non-comment line starts with the function name, then the
252 vpi type (i.e. vpiSysFuncReal). The following types are supported:
255 vpiSysFuncReal
256 The function returns a real/realtime value.
259 vpiSysFuncInt
260 The function returns an integer.
264 The function returns a vector with the given width, and is
265 signed or unsigned according to the flag.
268 COMMAND FILES
269 The command file allows the user to place source file names and certain
270 command line switches into a text file instead of on a long command
271 line. Command files can include C or C++ style comments, as well as #
272 comments, if the # starts the line.
275 file name
276 A simple file name or file path is taken to be the name of a
277 Verilog source file. The path starts with the first non-white-
278 space character. Variables are substitued in file names.
281 -y libdir
282 A -y token prefixes a library directory in the command file,
283 exactly like it does on the command line. The parameter to the
284 -y flag may be on the same line or the next non-comment line.
286 Variables in the libdir are substituted.
289 +incdir+includedir
290 The +incdir+ token in command files gives directories to search
291 for include files in much the same way that -I flags work on
292 the command line. The difference is that multiple +includedir
293 directories are valid parameters to a single +incdir+ token,
294 although you may also have multiple +incdir+ lines.
296 Variables in the includedir are substituted.
299 +libext+ext
300 The +libext token in command files fives file extensions to try
301 when looking for a library file. This is useful in conjunction
302 with -y flags to list suffixes to try in each directory before
303 moving on to the next library directory.
306 +libdir+dir
307 This is another way to specify library directories. See the -y
308 flag.
311 +libdir-nocase+dir
312 This is like the +libdir statement, but file names inside the
313 directories declared here are case insensitive. The missing
314 module name in a lookup need not match the file name case, as
319 +define+NAME=value
320 The +define+ token is the same as the -D option on the command
321 line. The value part of the token is optional.
324 +toupper-filename
325 This token causes file names after this in the command file to
326 be translated to uppercase. This helps with situations where a
327 directory has passed through a DOS machine, and in the process
328 the file names become munged.
331 +tolower-filename
332 This is similar to the +toupper-filename hack described above.
335 VARIABLES IN COMMAND FILES
336 In certain cases, iverilog supports variables in command files. These
338 environment variable to read. The entire string is replaced with the
339 contents of that variable. Variables are only substitued in contexts
340 that explicitly support them, including file and directory strings.
342 Variable values come from the operating system environment, and not
343 from preprocessor defines elsewhere in the file or the command line.
346 EXAMPLES
347 These examples assume that you have a Verilog source file called
348 hello.v in the current directory
350 To compile hello.v to an executable file called a.out:
352 iverilog hello.v
354 To compile hello.v to an executable file called hello:
356 iverilog -o hello hello.v
358 To compile and run explicitly using the vvp runtime:
360 iverilog -ohello.vvp -tvvp hello.v
362 To compile hello.v to a file in XNF-format called hello.xnf
364 iverilog -txnf -ohello.xnf hello.v
368 AUTHOR
369 Steve Williams (steve@icarus.com)
372 SEE ALSO
376 COPYRIGHT
377 Copyright © 2002 Stephen Williams
379 This document can be freely redistributed according to the terms of the
380 GNU General Public License version 2.0
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