docs/wiki/geda-systemc_netlister_readme.html

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  13 <h1 class="sectionedit1" id="systemc_netlister_readme">SystemC netlister README</h1>
  14 <div class="level1">
  15 <pre class="code">TITLE:
  16
  17      Gnetlist SystemC Backend
  18
  19 OBJECTIVE:
  20
  21      Transform a geda schematic into a transaction based structural systemc module.
  22
  23 LIMITATIONS:
  24
  25      1.- Only transaction based wires are considered (wire_name&lt;user_type&gt;).
  26      2.- Unnamed wires are eliminated.
  27      3.- In/out ports have to be inserted manually in the sysc code.
  28      4.- Duplicated include headers are not eliminated by the backend.
  29      5.- The maximum number of object constructor parameters is 31 (attr1-&gt;attr31).
  30
  31 LINKS:
  32
  33      GPL Electronic Design Automation (geda-gnetlist): http://www.geda-project.org
  34      SystemC: http://www.systemc.org
  35
  36 ACK:
  37
  38      Based on gnet-verilog.scm by Mike Jarabek.
  39
  40 EXAMPLE:
  41
  42      Schematic:
  43
  44      src1                         alg1                      snk1
  45      ______________               _______________           _______________
  46      | source     |  a&lt;user_type&gt; |  algorithm  |  b&lt;float&gt; |        sink |
  47      |         OUT|__ _________ __|IN        OUT|__ _____ __|IN           |
  48      |            |               |             |           |             |
  49      | infile.data|               |             |           | outfile.data|
  50      |____________|               |_____________|           |_____________|
  51
  52
  53      Attributes:
  54
  55             Schematic:
  56                      module_name=test_sch2sysc
  57
  58             Wires:
  59                      netname=a&lt;user_type&gt;
  60                      netname=b&lt;float&gt;
  61             Symbols:
  62                      refdes=src1 attr1=infile.data
  63                      refdes=alg1
  64                      refdes=snk1 attr1=outfile.data
  65                      refdes=pina
  66                      refdes=pinb
  67
  68      SystemC:
  69
  70                 #include &quot;systemc.h&quot;
  71                 #include &quot;sink.h&quot;
  72                 #include &quot;source.h&quot;
  73                 #include &quot;algorithm.h&quot;
  74
  75                 SC_MODULE (test_sch2sysc)
  76                 {
  77                         /* Port directions begin here */
  78
  79                         /* Wires from the design */
  80                         sc_signal&lt;float&gt; b;
  81                         sc_signal&lt;packet_type&gt; a;
  82
  83                         /* Package instantiations */
  84                         sink snk1;
  85                         source src1;
  86                         algorithm alg1;
  87
  88                         SC_CTOR(test_sch2sysc):
  89                                 snk1(&quot;snk1&quot;,&quot;outfile.data&quot;),
  90                                 src1(&quot;src1&quot;,&quot;infile.data&quot;),
  91                                 alg1(&quot;alg1&quot;)
  92                         {
  93                                 snk1.IN(b);
  94                                 src1.OUT(a);
  95                                 alg1.IN(a);
  96                                 alg1.OUT(b);
  97                         }
  98                 };
  99 </pre>
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