tests/ctags/traffic_signal.v

   1 // http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
   2
   3 // Digital model of a traffic light
   4 // By Dan Hyde August 10, 1995
   5 module traffic;
   6 parameter on = 1, off = 0, red_tics = 35,
   7           amber_tics = 3, green_tics = 20;
   8 reg clock, red, amber, green;
   9
  10 // will stop the simulation after 1000 time units
  11 initial begin: stop_at
  12    #1000; $stop;
  13 end
  14
  15 // initialize the lights and set up monitoring of registers
  16 initial begin: Init
  17     red = off; amber = off; green = off;
  18     $display("                 Time green amber red");
  19     $monitor("%3d    %b     %b    %b", $time, green, amber, red);
  20 end
  21
  22 // task to wait for 'tics' positive edge clocks
  23 // before turning light off
  24 task light;
  25    output color;
  26    input [31:0] tics;
  27    begin
  28       repeat(tics)  // wait to detect tics positive edges on clock
  29          @(posedge clock);
  30       color = off;
  31    end
  32 endtask
  33
  34 // waveform for clock period of 2 time units
  35 always begin: clock_wave
  36   #1 clock = 0;
  37   #1 clock = 1;
  38 end
  39
  40 always begin: main_process
  41    red = on;
  42    light(red, red_tics);  // call task to wait
  43    green = on;
  44    light(green, green_tics);
  45    amber = on;
  46    light(amber, amber_tics);
  47 end
  48
  49 endmodule