2 * Copyright (c) 2003, Darren Hiebert
4 * This source code is released for free distribution under the terms of the
5 * GNU General Public License.
7 * This module contains functions for generating tags for the Verilog HDL
8 * (Hardware Description Language).
10 * Language definition documents:
11 * http://www.eg.bucknell.edu/~cs320/verilog/verilog-manual.html
12 * http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html
13 * http://www.verilog.com/VerilogBNF.html
14 * http://eesun.free.fr/DOC/VERILOG/verilog_manual1.html
20 #include "general.h" /* must always come first */
34 typedef enum eException
{ ExceptionNone
, ExceptionEOF
} exception_t
;
57 static int Lang_verilog
;
58 static jmp_buf Exception
;
60 static kindOption VerilogKinds
[] = {
61 { TRUE
, 'c', "variable", "constants (define, parameter, specparam)" },
62 { TRUE
, 'e', "typedef", "events" },
63 { TRUE
, 'f', "function", "functions" },
64 { TRUE
, 'm', "class", "modules" },
65 { TRUE
, 'n', "variable", "net data types" },
66 { TRUE
, 'p', "variable", "ports" },
67 { TRUE
, 'r', "variable", "register data types" },
68 { TRUE
, 't', "function", "tasks" }
71 static keywordAssoc VerilogKeywordTable
[] = {
72 { "`define", K_CONSTANT
},
74 { "function", K_FUNCTION
},
77 { "integer", K_REGISTER
},
78 { "module", K_MODULE
},
80 { "parameter", K_CONSTANT
},
81 { "real", K_REGISTER
},
82 { "realtime", K_REGISTER
},
83 { "reg", K_REGISTER
},
84 { "specparam", K_CONSTANT
},
88 { "time", K_REGISTER
},
101 * FUNCTION DEFINITIONS
104 static void initialize (const langType language
)
108 sizeof (VerilogKeywordTable
) / sizeof (VerilogKeywordTable
[0]);
109 Lang_verilog
= language
;
110 for (i
= 0 ; i
< count
; ++i
)
112 const keywordAssoc
* const p
= &VerilogKeywordTable
[i
];
113 addKeyword (p
->keyword
, language
, (int) p
->kind
);
117 static void vUngetc (int c
)
119 Assert (Ungetc
== '\0');
123 static int vGetc (void)
135 int c2
= fileGetc ();
137 longjmp (Exception
, (int) ExceptionEOF
);
138 else if (c2
== '/') /* strip comment until end-of-line */
142 while (c
!= '\n' && c
!= EOF
);
144 else if (c2
== '*') /* strip block comment */
146 c
= skipOverCComment();
153 else if (c
== '"') /* strip string contents */
158 while (c2
!= '"' && c2
!= EOF
);
162 longjmp (Exception
, (int) ExceptionEOF
);
166 static boolean
isIdentifierCharacter (const int c
)
168 return (boolean
)(isalnum (c
) || c
== '_' || c
== '`');
171 static int skipWhite (int c
)
178 static int skipPastMatch (const char *const pair
)
180 const int begin
= pair
[0], end
= pair
[1];
191 while (matchLevel
> 0);
195 static boolean
readIdentifier (vString
*const name
, int c
)
198 if (isIdentifierCharacter (c
))
200 while (isIdentifierCharacter (c
))
202 vStringPut (name
, c
);
206 vStringTerminate (name
);
208 return (boolean
)(name
->length
> 0);
211 static void tagNameList (const verilogKind kind
, int c
)
213 vString
*name
= vStringNew ();
215 Assert (isIdentifierCharacter (c
));
219 if (isIdentifierCharacter (c
))
221 readIdentifier (name
, c
);
222 makeSimpleTag (name
, VerilogKinds
, kind
);
226 c
= skipWhite (vGetc ());
228 c
= skipPastMatch ("[]");
233 skipPastMatch ("{}");
238 while (c
!= ',' && c
!= ';');
243 c
= skipWhite (vGetc ());
249 vStringDelete (name
);
253 static void findTag (vString
*const name
)
255 const verilogKind kind
= (verilogKind
) lookupKeyword (vStringValue (name
), Lang_verilog
);
256 if (kind
== K_CONSTANT
&& vStringItem (name
, 0) == '`')
258 /* Bug #961001: Verilog compiler directives are line-based. */
259 int c
= skipWhite (vGetc ());
260 readIdentifier (name
, c
);
261 makeSimpleTag (name
, VerilogKinds
, kind
);
262 /* Skip the rest of the line. */
268 else if (kind
!= K_UNDEFINED
)
270 int c
= skipWhite (vGetc ());
272 /* Many keywords can have bit width.
273 * reg [3:0] net_name;
274 * inout [(`DBUSWIDTH-1):0] databus;
277 c
= skipPastMatch ("()");
280 c
= skipPastMatch ("[]");
286 c
= skipPastMatch ("()");
289 if (isIdentifierCharacter (c
))
290 tagNameList (kind
, c
);
294 static void findVerilogTags (void)
296 vString
*const name
= vStringNew ();
297 volatile boolean newStatement
= TRUE
;
298 volatile int c
= '\0';
299 exception_t exception
= (exception_t
) setjmp (Exception
);
301 if (exception
== ExceptionNone
) while (c
!= EOF
)
316 if (newStatement
&& readIdentifier (name
, c
))
318 newStatement
= FALSE
;
322 vStringDelete (name
);
325 extern parserDefinition
* VerilogParser (void)
327 static const char *const extensions
[] = { "v", NULL
};
328 parserDefinition
* def
= parserNew ("Verilog");
329 def
->kinds
= VerilogKinds
;
330 def
->kindCount
= KIND_COUNT (VerilogKinds
);
331 def
->extensions
= extensions
;
332 def
->parser
= findVerilogTags
;
333 def
->initialize
= initialize
;
337 /* vi:set tabstop=4 shiftwidth=4: */