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Add VHDL unit tests from uctags and remove the giant test.vhd
[geany-mirror.git]
/
tests
/
ctags
/
vhdl-port.vhd
blob
22e83f30ff49c10be743b2b64dd2f2541b8f8cd6
1
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
2
entity
logical_ops_1
is
3
port
(
a
,
b
,
c
,
d
:
in
bit
;
4
m
:
out
bit
);
5
end
logical_ops_1
;